arch/alpha/include/asm/core_tsunami.h

   1 #ifndef __ALPHA_TSUNAMI__H__
   2 #define __ALPHA_TSUNAMI__H__
   3
   4 #include <linux/types.h>
   5 #include <linux/pci.h>
   6 #include <asm/compiler.h>
   7
   8 /*
   9  * TSUNAMI/TYPHOON are the internal names for the core logic chipset which
  10  * provides memory controller and PCI access for the 21264 based systems.
  11  *
  12  * This file is based on:
  13  *
  14  * Tsunami System Programmers Manual
  15  * Preliminary, Chapters 2-5
  16  *
  17  */
  18
  19 /* XXX: Do we need to conditionalize on this?  */
  20 #ifdef USE_48_BIT_KSEG
  21 #define TS_BIAS 0x80000000000UL
  22 #else
  23 #define TS_BIAS 0x10000000000UL
  24 #endif
  25
  26 /*
  27  * CChip, DChip, and PChip registers
  28  */
  29
  30 typedef struct {
  31         volatile unsigned long csr __attribute__((aligned(64)));
  32 } tsunami_64;
  33
  34 typedef struct {
  35         tsunami_64      csc;
  36         tsunami_64      mtr;
  37         tsunami_64      misc;
  38         tsunami_64      mpd;
  39         tsunami_64      aar0;
  40         tsunami_64      aar1;
  41         tsunami_64      aar2;
  42         tsunami_64      aar3;
  43         tsunami_64      dim0;
  44         tsunami_64      dim1;
  45         tsunami_64      dir0;
  46         tsunami_64      dir1;
  47         tsunami_64      drir;
  48         tsunami_64      prben;
  49         tsunami_64      iic;    /* a.k.a. iic0 */
  50         tsunami_64      wdr;    /* a.k.a. iic1 */
  51         tsunami_64      mpr0;
  52         tsunami_64      mpr1;
  53         tsunami_64      mpr2;
  54         tsunami_64      mpr3;
  55         tsunami_64      mctl;
  56         tsunami_64      __pad1;
  57         tsunami_64      ttr;
  58         tsunami_64      tdr;
  59         tsunami_64      dim2;
  60         tsunami_64      dim3;
  61         tsunami_64      dir2;
  62         tsunami_64      dir3;
  63         tsunami_64      iic2;
  64         tsunami_64      iic3;
  65 } tsunami_cchip;
  66
  67 typedef struct {
  68         tsunami_64      dsc;
  69         tsunami_64      str;
  70         tsunami_64      drev;
  71 } tsunami_dchip;
  72
  73 typedef struct {
  74         tsunami_64      wsba[4];
  75         tsunami_64      wsm[4];
  76         tsunami_64      tba[4];
  77         tsunami_64      pctl;
  78         tsunami_64      plat;
  79         tsunami_64      reserved;
  80         tsunami_64      perror;
  81         tsunami_64      perrmask;
  82         tsunami_64      perrset;
  83         tsunami_64      tlbiv;
  84         tsunami_64      tlbia;
  85         tsunami_64      pmonctl;
  86         tsunami_64      pmoncnt;
  87 } tsunami_pchip;
  88
  89 #define TSUNAMI_cchip  ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL))
  90 #define TSUNAMI_dchip  ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL))
  91 #define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL))
  92 #define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL))
  93 extern int TSUNAMI_bootcpu;
  94
  95 /*
  96  * TSUNAMI Pchip Error register.
  97  */
  98
  99 #define perror_m_lost 0x1
 100 #define perror_m_serr 0x2
 101 #define perror_m_perr 0x4
 102 #define perror_m_dcrto 0x8
 103 #define perror_m_sge 0x10
 104 #define perror_m_ape 0x20
 105 #define perror_m_ta 0x40
 106 #define perror_m_rdpe 0x80
 107 #define perror_m_nds 0x100
 108 #define perror_m_rto 0x200
 109 #define perror_m_uecc 0x400
 110 #define perror_m_cre 0x800
 111 #define perror_m_addrl 0xFFFFFFFF0000UL
 112 #define perror_m_addrh 0x7000000000000UL
 113 #define perror_m_cmd 0xF0000000000000UL
 114 #define perror_m_syn 0xFF00000000000000UL
 115 union TPchipPERROR {
 116         struct  {
 117                 unsigned int perror_v_lost : 1;
 118                 unsigned perror_v_serr : 1;
 119                 unsigned perror_v_perr : 1;
 120                 unsigned perror_v_dcrto : 1;
 121                 unsigned perror_v_sge : 1;
 122                 unsigned perror_v_ape : 1;
 123                 unsigned perror_v_ta : 1;
 124                 unsigned perror_v_rdpe : 1;
 125                 unsigned perror_v_nds : 1;
 126                 unsigned perror_v_rto : 1;
 127                 unsigned perror_v_uecc : 1;
 128                 unsigned perror_v_cre : 1;
 129                 unsigned perror_v_rsvd1 : 4;
 130                 unsigned perror_v_addrl : 32;
 131                 unsigned perror_v_addrh : 3;
 132                 unsigned perror_v_rsvd2 : 1;
 133                 unsigned perror_v_cmd : 4;
 134                 unsigned perror_v_syn : 8;
 135         } perror_r_bits;
 136         int perror_q_whole [2];
 137 };
 138
 139 /*
 140  * TSUNAMI Pchip Window Space Base Address register.
 141  */
 142 #define wsba_m_ena 0x1
 143 #define wsba_m_sg 0x2
 144 #define wsba_m_ptp 0x4
 145 #define wsba_m_addr 0xFFF00000
 146 #define wmask_k_sz1gb 0x3FF00000
 147 union TPchipWSBA {
 148         struct  {
 149                 unsigned wsba_v_ena : 1;
 150                 unsigned wsba_v_sg : 1;
 151                 unsigned wsba_v_ptp : 1;
 152                 unsigned wsba_v_rsvd1 : 17;
 153                 unsigned wsba_v_addr : 12;
 154                 unsigned wsba_v_rsvd2 : 32;
 155         } wsba_r_bits;
 156         int wsba_q_whole [2];
 157 };
 158
 159 /*
 160  * TSUNAMI Pchip Control Register
 161  */
 162 #define pctl_m_fdsc 0x1
 163 #define pctl_m_fbtb 0x2
 164 #define pctl_m_thdis 0x4
 165 #define pctl_m_chaindis 0x8
 166 #define pctl_m_tgtlat 0x10
 167 #define pctl_m_hole 0x20
 168 #define pctl_m_mwin 0x40
 169 #define pctl_m_arbena 0x80
 170 #define pctl_m_prigrp 0x7F00
 171 #define pctl_m_ppri 0x8000
 172 #define pctl_m_rsvd1 0x30000
 173 #define pctl_m_eccen 0x40000
 174 #define pctl_m_padm 0x80000
 175 #define pctl_m_cdqmax 0xF00000
 176 #define pctl_m_rev 0xFF000000
 177 #define pctl_m_crqmax 0xF00000000UL
 178 #define pctl_m_ptpmax 0xF000000000UL
 179 #define pctl_m_pclkx 0x30000000000UL
 180 #define pctl_m_fdsdis 0x40000000000UL
 181 #define pctl_m_fdwdis 0x80000000000UL
 182 #define pctl_m_ptevrfy 0x100000000000UL
 183 #define pctl_m_rpp 0x200000000000UL
 184 #define pctl_m_pid 0xC00000000000UL
 185 #define pctl_m_rsvd2 0xFFFF000000000000UL
 186
 187 union TPchipPCTL {
 188         struct {
 189                 unsigned pctl_v_fdsc : 1;
 190                 unsigned pctl_v_fbtb : 1;
 191                 unsigned pctl_v_thdis : 1;
 192                 unsigned pctl_v_chaindis : 1;
 193                 unsigned pctl_v_tgtlat : 1;
 194                 unsigned pctl_v_hole : 1;
 195                 unsigned pctl_v_mwin : 1;
 196                 unsigned pctl_v_arbena : 1;
 197                 unsigned pctl_v_prigrp : 7;
 198                 unsigned pctl_v_ppri : 1;
 199                 unsigned pctl_v_rsvd1 : 2;
 200                 unsigned pctl_v_eccen : 1;
 201                 unsigned pctl_v_padm : 1;
 202                 unsigned pctl_v_cdqmax : 4;
 203                 unsigned pctl_v_rev : 8;
 204                 unsigned pctl_v_crqmax : 4;
 205                 unsigned pctl_v_ptpmax : 4;
 206                 unsigned pctl_v_pclkx : 2;
 207                 unsigned pctl_v_fdsdis : 1;
 208                 unsigned pctl_v_fdwdis : 1;
 209                 unsigned pctl_v_ptevrfy : 1;
 210                 unsigned pctl_v_rpp : 1;
 211                 unsigned pctl_v_pid : 2;
 212                 unsigned pctl_v_rsvd2 : 16;
 213         } pctl_r_bits;
 214         int pctl_q_whole [2];
 215 };
 216
 217 /*
 218  * TSUNAMI Pchip Error Mask Register.
 219  */
 220 #define perrmask_m_lost 0x1
 221 #define perrmask_m_serr 0x2
 222 #define perrmask_m_perr 0x4
 223 #define perrmask_m_dcrto 0x8
 224 #define perrmask_m_sge 0x10
 225 #define perrmask_m_ape 0x20
 226 #define perrmask_m_ta 0x40
 227 #define perrmask_m_rdpe 0x80
 228 #define perrmask_m_nds 0x100
 229 #define perrmask_m_rto 0x200
 230 #define perrmask_m_uecc 0x400
 231 #define perrmask_m_cre 0x800
 232 #define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL
 233 union TPchipPERRMASK {
 234         struct  {
 235                 unsigned int perrmask_v_lost : 1;
 236                 unsigned perrmask_v_serr : 1;
 237                 unsigned perrmask_v_perr : 1;
 238                 unsigned perrmask_v_dcrto : 1;
 239                 unsigned perrmask_v_sge : 1;
 240                 unsigned perrmask_v_ape : 1;
 241                 unsigned perrmask_v_ta : 1;
 242                 unsigned perrmask_v_rdpe : 1;
 243                 unsigned perrmask_v_nds : 1;
 244                 unsigned perrmask_v_rto : 1;
 245                 unsigned perrmask_v_uecc : 1;
 246                 unsigned perrmask_v_cre : 1;
 247                 unsigned perrmask_v_rsvd1 : 20;
 248                 unsigned perrmask_v_rsvd2 : 32;
 249         } perrmask_r_bits;
 250         int perrmask_q_whole [2];
 251 };
 252
 253 /*
 254  * Memory spaces:
 255  */
 256 #define TSUNAMI_HOSE(h)         (((unsigned long)(h)) << 33)
 257 #define TSUNAMI_BASE            (IDENT_ADDR + TS_BIAS)
 258
 259 #define TSUNAMI_MEM(h)          (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL)
 260 #define _TSUNAMI_IACK_SC(h)     (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL)
 261 #define TSUNAMI_IO(h)           (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL)
 262 #define TSUNAMI_CONF(h)         (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL)
 263
 264 #define TSUNAMI_IACK_SC         _TSUNAMI_IACK_SC(0) /* hack! */
 265
 266
 267 /*
 268  * The canonical non-remaped I/O and MEM addresses have these values
 269  * subtracted out.  This is arranged so that folks manipulating ISA
 270  * devices can use their familiar numbers and have them map to bus 0.
 271  */
 272
 273 #define TSUNAMI_IO_BIAS          TSUNAMI_IO(0)
 274 #define TSUNAMI_MEM_BIAS         TSUNAMI_MEM(0)
 275
 276 /* The IO address space is larger than 0xffff */
 277 #define TSUNAMI_IO_SPACE        (TSUNAMI_CONF(0) - TSUNAMI_IO(0))
 278
 279 /* Offset between ram physical addresses and pci64 DAC bus addresses.  */
 280 #define TSUNAMI_DAC_OFFSET      (1UL << 40)
 281
 282 /*
 283  * Data structure for handling TSUNAMI machine checks:
 284  */
 285 struct el_TSUNAMI_sysdata_mcheck {
 286 };
 287
 288
 289 #ifdef __KERNEL__
 290
 291 #ifndef __EXTERN_INLINE
 292 #define __EXTERN_INLINE extern inline
 293 #define __IO_EXTERN_INLINE
 294 #endif
 295
 296 /*
 297  * I/O functions:
 298  *
 299  * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264)
 300  * can only use linear accesses to get at PCI memory and I/O spaces.
 301  */
 302
 303 /*
 304  * Memory functions.  all accesses are done through linear space.
 305  */
 306 extern void __iomem *tsunami_ioportmap(unsigned long addr);
 307 extern void __iomem *tsunami_ioremap(unsigned long addr, unsigned long size);
 308 __EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr)
 309 {
 310         return addr >= TSUNAMI_BASE;
 311 }
 312
 313 __EXTERN_INLINE int tsunami_is_mmio(const volatile void __iomem *xaddr)
 314 {
 315         unsigned long addr = (unsigned long) xaddr;
 316         return (addr & 0x100000000UL) == 0;
 317 }
 318
 319 #undef __IO_PREFIX
 320 #define __IO_PREFIX             tsunami
 321 #define tsunami_trivial_rw_bw   1
 322 #define tsunami_trivial_rw_lq   1
 323 #define tsunami_trivial_io_bw   1
 324 #define tsunami_trivial_io_lq   1
 325 #define tsunami_trivial_iounmap 1
 326 #include <asm/io_trivial.h>
 327
 328 #ifdef __IO_EXTERN_INLINE
 329 #undef __EXTERN_INLINE
 330 #undef __IO_EXTERN_INLINE
 331 #endif
 332
 333 #endif /* __KERNEL__ */
 334
 335 #endif /* __ALPHA_TSUNAMI__H__ */