arch/sh/include/asm/pci.h

   1 #ifndef __ASM_SH_PCI_H
   2 #define __ASM_SH_PCI_H
   3
   4 #ifdef __KERNEL__
   5
   6 #include <linux/dma-mapping.h>
   7
   8 /* Can be used to override the logic in pci_scan_bus for skipping
   9    already-configured bus numbers - to be used for buggy BIOSes
  10    or architectures with incomplete PCI setup by the loader */
  11
  12 #define pcibios_assign_all_busses()     1
  13
  14 /*
  15  * A board can define one or more PCI channels that represent built-in (or
  16  * external) PCI controllers.
  17  */
  18 struct pci_channel {
  19         struct pci_channel      *next;
  20
  21         struct pci_ops          *pci_ops;
  22         struct resource         *io_resource;
  23         struct resource         *mem_resource;
  24
  25         unsigned long           io_offset;
  26         unsigned long           mem_offset;
  27
  28         unsigned long           reg_base;
  29
  30         unsigned long           io_map_base;
  31 };
  32
  33 extern void register_pci_controller(struct pci_channel *hose);
  34
  35 extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
  36
  37 struct pci_dev;
  38
  39 #define HAVE_PCI_MMAP
  40 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  41         enum pci_mmap_state mmap_state, int write_combine);
  42 extern void pcibios_set_master(struct pci_dev *dev);
  43
  44 static inline void pcibios_penalize_isa_irq(int irq, int active)
  45 {
  46         /* We don't do dynamic PCI IRQ allocation */
  47 }
  48
  49 /* Dynamic DMA mapping stuff.
  50  * SuperH has everything mapped statically like x86.
  51  */
  52
  53 /* The PCI address space does equal the physical memory
  54  * address space.  The networking and block device layers use
  55  * this boolean for bounce buffer decisions.
  56  */
  57 #define PCI_DMA_BUS_IS_PHYS     (1)
  58
  59 #include <linux/types.h>
  60 #include <linux/slab.h>
  61 #include <asm/scatterlist.h>
  62 #include <linux/string.h>
  63 #include <asm/io.h>
  64
  65 /* pci_unmap_{single,page} being a nop depends upon the
  66  * configuration.
  67  */
  68 #ifdef CONFIG_SH_PCIDMA_NONCOHERENT
  69 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
  70         dma_addr_t ADDR_NAME;
  71 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
  72         __u32 LEN_NAME;
  73 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
  74         ((PTR)->ADDR_NAME)
  75 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
  76         (((PTR)->ADDR_NAME) = (VAL))
  77 #define pci_unmap_len(PTR, LEN_NAME)                    \
  78         ((PTR)->LEN_NAME)
  79 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
  80         (((PTR)->LEN_NAME) = (VAL))
  81 #else
  82 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
  83 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
  84 #define pci_unmap_addr(PTR, ADDR_NAME)          (0)
  85 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
  86 #define pci_unmap_len(PTR, LEN_NAME)            (0)
  87 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
  88 #endif
  89
  90 #ifdef CONFIG_PCI
  91 /*
  92  * None of the SH PCI controllers support MWI, it is always treated as a
  93  * direct memory write.
  94  */
  95 #define PCI_DISABLE_MWI
  96
  97 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  98                                         enum pci_dma_burst_strategy *strat,
  99                                         unsigned long *strategy_parameter)
 100 {
 101         unsigned long cacheline_size;
 102         u8 byte;
 103
 104         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
 105
 106         if (byte == 0)
 107                 cacheline_size = L1_CACHE_BYTES;
 108         else
 109                 cacheline_size = byte << 2;
 110
 111         *strat = PCI_DMA_BURST_MULTIPLE;
 112         *strategy_parameter = cacheline_size;
 113 }
 114 #endif
 115
 116 #ifdef CONFIG_SUPERH32
 117 /*
 118  * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
 119  * at the end of the address space in a special non-translatable area.
 120  */
 121 #define PCI_MEM_FIXED_START     0xfd000000
 122 #define PCI_MEM_FIXED_END       (PCI_MEM_FIXED_START + 0x01000000)
 123
 124 #define is_pci_memory_fixed_range(s, e) \
 125         ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
 126 #else
 127 #define is_pci_memory_fixed_range(s, e) (0)
 128 #endif
 129
 130 /* Board-specific fixup routines. */
 131 int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
 132
 133 extern void pcibios_resource_to_bus(struct pci_dev *dev,
 134         struct pci_bus_region *region, struct resource *res);
 135
 136 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 137                                     struct pci_bus_region *region);
 138
 139 /* Chances are this interrupt is wired PC-style ...  */
 140 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 141 {
 142         return channel ? 15 : 14;
 143 }
 144
 145 /* generic DMA-mapping stuff */
 146 #include <asm-generic/pci-dma-compat.h>
 147
 148 #endif /* __KERNEL__ */
 149 #endif /* __ASM_SH_PCI_H */
 150