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OMAP3 PM: CPUFreq driver for OMAP3
[linux-ginger.git] / drivers / net / 8139too.c
blob4a362875502661f8d3e7bae4adf78a3952114b43
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/delay.h>
105 #include <linux/ethtool.h>
106 #include <linux/mii.h>
107 #include <linux/completion.h>
108 #include <linux/crc32.h>
109 #include <linux/io.h>
110 #include <linux/uaccess.h>
111 #include <asm/irq.h>
112
113 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
114 #define PFX DRV_NAME ": "
115
116 /* Default Message level */
117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 NETIF_MSG_PROBE | \
119 NETIF_MSG_LINK)
120
121
122 /* define to 1, 2 or 3 to enable copious debugging info */
123 #define RTL8139_DEBUG 0
124
125 /* define to 1 to disable lightweight runtime debugging checks */
126 #undef RTL8139_NDEBUG
127
128
129 #ifdef RTL8139_NDEBUG
130 # define assert(expr) do {} while (0)
131 #else
132 # define assert(expr) \
133 if(unlikely(!(expr))) { \
134 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
135 #expr, __FILE__, __func__, __LINE__); \
136 }
137 #endif
138
139
140 /* A few user-configurable values. */
141 /* media options */
142 #define MAX_UNITS 8
143 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
144 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
145
146 /* Whether to use MMIO or PIO. Default to MMIO. */
147 #ifdef CONFIG_8139TOO_PIO
148 static int use_io = 1;
149 #else
150 static int use_io = 0;
151 #endif
152
153 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
154 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
155 static int multicast_filter_limit = 32;
156
157 /* bitmapped message enable number */
158 static int debug = -1;
159
160 /*
161 * Receive ring size
162 * Warning: 64K ring has hardware issues and may lock up.
163 */
164 #if defined(CONFIG_SH_DREAMCAST)
165 #define RX_BUF_IDX 0 /* 8K ring */
166 #else
167 #define RX_BUF_IDX 2 /* 32K ring */
168 #endif
169 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
170 #define RX_BUF_PAD 16
171 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
172
173 #if RX_BUF_LEN == 65536
174 #define RX_BUF_TOT_LEN RX_BUF_LEN
175 #else
176 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
177 #endif
178
179 /* Number of Tx descriptor registers. */
180 #define NUM_TX_DESC 4
181
182 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
183 #define MAX_ETH_FRAME_SIZE 1536
184
185 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
186 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
187 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
188
189 /* PCI Tuning Parameters
190 Threshold is bytes transferred to chip before transmission starts. */
191 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
192
193 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
194 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
195 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
196 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
197 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
198
199 /* Operational parameters that usually are not changed. */
200 /* Time in jiffies before concluding the transmitter is hung. */
201 #define TX_TIMEOUT (6*HZ)
202
203
204 enum {
205 HAS_MII_XCVR = 0x010000,
206 HAS_CHIP_XCVR = 0x020000,
207 HAS_LNK_CHNG = 0x040000,
208 };
209
210 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
211 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
212 #define RTL_MIN_IO_SIZE 0x80
213 #define RTL8139B_IO_SIZE 256
214
215 #define RTL8129_CAPS HAS_MII_XCVR
216 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
217
218 typedef enum {
219 RTL8139 = 0,
220 RTL8129,
221 } board_t;
222
223
224 /* indexed by board_t, above */
225 static const struct {
226 const char *name;
227 u32 hw_flags;
228 } board_info[] __devinitdata = {
229 { "RealTek RTL8139", RTL8139_CAPS },
230 { "RealTek RTL8129", RTL8129_CAPS },
231 };
232
233
234 static struct pci_device_id rtl8139_pci_tbl[] = {
235 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
236 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
237 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
238 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254
255 #ifdef CONFIG_SH_SECUREEDGE5410
256 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
257 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 #endif
259 #ifdef CONFIG_8139TOO_8129
260 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
261 #endif
262
263 /* some crazy cards report invalid vendor ids like
264 * 0x0001 here. The other ids are valid and constant,
265 * so we simply don't match on the main vendor id.
266 */
267 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
268 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
269 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
270
271 {0,}
272 };
273 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
274
275 static struct {
276 const char str[ETH_GSTRING_LEN];
277 } ethtool_stats_keys[] = {
278 { "early_rx" },
279 { "tx_buf_mapped" },
280 { "tx_timeouts" },
281 { "rx_lost_in_ring" },
282 };
283
284 /* The rest of these values should never change. */
285
286 /* Symbolic offsets to registers. */
287 enum RTL8139_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
289 MAR0 = 8, /* Multicast filter. */
290 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
291 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
292 RxBuf = 0x30,
293 ChipCmd = 0x37,
294 RxBufPtr = 0x38,
295 RxBufAddr = 0x3A,
296 IntrMask = 0x3C,
297 IntrStatus = 0x3E,
298 TxConfig = 0x40,
299 RxConfig = 0x44,
300 Timer = 0x48, /* A general-purpose counter. */
301 RxMissed = 0x4C, /* 24 bits valid, write clears. */
302 Cfg9346 = 0x50,
303 Config0 = 0x51,
304 Config1 = 0x52,
305 TimerInt = 0x54,
306 MediaStatus = 0x58,
307 Config3 = 0x59,
308 Config4 = 0x5A, /* absent on RTL-8139A */
309 HltClk = 0x5B,
310 MultiIntr = 0x5C,
311 TxSummary = 0x60,
312 BasicModeCtrl = 0x62,
313 BasicModeStatus = 0x64,
314 NWayAdvert = 0x66,
315 NWayLPAR = 0x68,
316 NWayExpansion = 0x6A,
317 /* Undocumented registers, but required for proper operation. */
318 FIFOTMS = 0x70, /* FIFO Control and test. */
319 CSCR = 0x74, /* Chip Status and Configuration Register. */
320 PARA78 = 0x78,
321 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
322 PARA7c = 0x7c, /* Magic transceiver parameter register. */
323 Config5 = 0xD8, /* absent on RTL-8139A */
324 };
325
326 enum ClearBitMasks {
327 MultiIntrClear = 0xF000,
328 ChipCmdClear = 0xE2,
329 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
330 };
331
332 enum ChipCmdBits {
333 CmdReset = 0x10,
334 CmdRxEnb = 0x08,
335 CmdTxEnb = 0x04,
336 RxBufEmpty = 0x01,
337 };
338
339 /* Interrupt register bits, using my own meaningful names. */
340 enum IntrStatusBits {
341 PCIErr = 0x8000,
342 PCSTimeout = 0x4000,
343 RxFIFOOver = 0x40,
344 RxUnderrun = 0x20,
345 RxOverflow = 0x10,
346 TxErr = 0x08,
347 TxOK = 0x04,
348 RxErr = 0x02,
349 RxOK = 0x01,
350
351 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
352 };
353
354 enum TxStatusBits {
355 TxHostOwns = 0x2000,
356 TxUnderrun = 0x4000,
357 TxStatOK = 0x8000,
358 TxOutOfWindow = 0x20000000,
359 TxAborted = 0x40000000,
360 TxCarrierLost = 0x80000000,
361 };
362 enum RxStatusBits {
363 RxMulticast = 0x8000,
364 RxPhysical = 0x4000,
365 RxBroadcast = 0x2000,
366 RxBadSymbol = 0x0020,
367 RxRunt = 0x0010,
368 RxTooLong = 0x0008,
369 RxCRCErr = 0x0004,
370 RxBadAlign = 0x0002,
371 RxStatusOK = 0x0001,
372 };
373
374 /* Bits in RxConfig. */
375 enum rx_mode_bits {
376 AcceptErr = 0x20,
377 AcceptRunt = 0x10,
378 AcceptBroadcast = 0x08,
379 AcceptMulticast = 0x04,
380 AcceptMyPhys = 0x02,
381 AcceptAllPhys = 0x01,
382 };
383
384 /* Bits in TxConfig. */
385 enum tx_config_bits {
386 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
387 TxIFGShift = 24,
388 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
389 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
390 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
391 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
392
393 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
394 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
395 TxClearAbt = (1 << 0), /* Clear abort (WO) */
396 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
397 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
398
399 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
400 };
401
402 /* Bits in Config1 */
403 enum Config1Bits {
404 Cfg1_PM_Enable = 0x01,
405 Cfg1_VPD_Enable = 0x02,
406 Cfg1_PIO = 0x04,
407 Cfg1_MMIO = 0x08,
408 LWAKE = 0x10, /* not on 8139, 8139A */
409 Cfg1_Driver_Load = 0x20,
410 Cfg1_LED0 = 0x40,
411 Cfg1_LED1 = 0x80,
412 SLEEP = (1 << 1), /* only on 8139, 8139A */
413 PWRDN = (1 << 0), /* only on 8139, 8139A */
414 };
415
416 /* Bits in Config3 */
417 enum Config3Bits {
418 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
419 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
420 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
421 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
422 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
423 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
424 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
425 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
426 };
427
428 /* Bits in Config4 */
429 enum Config4Bits {
430 LWPTN = (1 << 2), /* not on 8139, 8139A */
431 };
432
433 /* Bits in Config5 */
434 enum Config5Bits {
435 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
436 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
437 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
438 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
439 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
440 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
441 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
442 };
443
444 enum RxConfigBits {
445 /* rx fifo threshold */
446 RxCfgFIFOShift = 13,
447 RxCfgFIFONone = (7 << RxCfgFIFOShift),
448
449 /* Max DMA burst */
450 RxCfgDMAShift = 8,
451 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
452
453 /* rx ring buffer length */
454 RxCfgRcv8K = 0,
455 RxCfgRcv16K = (1 << 11),
456 RxCfgRcv32K = (1 << 12),
457 RxCfgRcv64K = (1 << 11) | (1 << 12),
458
459 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
460 RxNoWrap = (1 << 7),
461 };
462
463 /* Twister tuning parameters from RealTek.
464 Completely undocumented, but required to tune bad links on some boards. */
465 enum CSCRBits {
466 CSCR_LinkOKBit = 0x0400,
467 CSCR_LinkChangeBit = 0x0800,
468 CSCR_LinkStatusBits = 0x0f000,
469 CSCR_LinkDownOffCmd = 0x003c0,
470 CSCR_LinkDownCmd = 0x0f3c0,
471 };
472
473 enum Cfg9346Bits {
474 Cfg9346_Lock = 0x00,
475 Cfg9346_Unlock = 0xC0,
476 };
477
478 typedef enum {
479 CH_8139 = 0,
480 CH_8139_K,
481 CH_8139A,
482 CH_8139A_G,
483 CH_8139B,
484 CH_8130,
485 CH_8139C,
486 CH_8100,
487 CH_8100B_8139D,
488 CH_8101,
489 } chip_t;
490
491 enum chip_flags {
492 HasHltClk = (1 << 0),
493 HasLWake = (1 << 1),
494 };
495
496 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
497 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
498 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
499
500 /* directly indexed by chip_t, above */
501 static const struct {
502 const char *name;
503 u32 version; /* from RTL8139C/RTL8139D docs */
504 u32 flags;
505 } rtl_chip_info[] = {
506 { "RTL-8139",
507 HW_REVID(1, 0, 0, 0, 0, 0, 0),
508 HasHltClk,
509 },
510
511 { "RTL-8139 rev K",
512 HW_REVID(1, 1, 0, 0, 0, 0, 0),
513 HasHltClk,
514 },
515
516 { "RTL-8139A",
517 HW_REVID(1, 1, 1, 0, 0, 0, 0),
518 HasHltClk, /* XXX undocumented? */
519 },
520
521 { "RTL-8139A rev G",
522 HW_REVID(1, 1, 1, 0, 0, 1, 0),
523 HasHltClk, /* XXX undocumented? */
524 },
525
526 { "RTL-8139B",
527 HW_REVID(1, 1, 1, 1, 0, 0, 0),
528 HasLWake,
529 },
530
531 { "RTL-8130",
532 HW_REVID(1, 1, 1, 1, 1, 0, 0),
533 HasLWake,
534 },
535
536 { "RTL-8139C",
537 HW_REVID(1, 1, 1, 0, 1, 0, 0),
538 HasLWake,
539 },
540
541 { "RTL-8100",
542 HW_REVID(1, 1, 1, 1, 0, 1, 0),
543 HasLWake,
544 },
545
546 { "RTL-8100B/8139D",
547 HW_REVID(1, 1, 1, 0, 1, 0, 1),
548 HasHltClk /* XXX undocumented? */
549 | HasLWake,
550 },
551
552 { "RTL-8101",
553 HW_REVID(1, 1, 1, 0, 1, 1, 1),
554 HasLWake,
555 },
556 };
557
558 struct rtl_extra_stats {
559 unsigned long early_rx;
560 unsigned long tx_buf_mapped;
561 unsigned long tx_timeouts;
562 unsigned long rx_lost_in_ring;
563 };
564
565 struct rtl8139_private {
566 void __iomem *mmio_addr;
567 int drv_flags;
568 struct pci_dev *pci_dev;
569 u32 msg_enable;
570 struct napi_struct napi;
571 struct net_device *dev;
572
573 unsigned char *rx_ring;
574 unsigned int cur_rx; /* RX buf index of next pkt */
575 dma_addr_t rx_ring_dma;
576
577 unsigned int tx_flag;
578 unsigned long cur_tx;
579 unsigned long dirty_tx;
580 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
581 unsigned char *tx_bufs; /* Tx bounce buffer region. */
582 dma_addr_t tx_bufs_dma;
583
584 signed char phys[4]; /* MII device addresses. */
585
586 /* Twister tune state. */
587 char twistie, twist_row, twist_col;
588
589 unsigned int watchdog_fired : 1;
590 unsigned int default_port : 4; /* Last dev->if_port value. */
591 unsigned int have_thread : 1;
592
593 spinlock_t lock;
594 spinlock_t rx_lock;
595
596 chip_t chipset;
597 u32 rx_config;
598 struct rtl_extra_stats xstats;
599
600 struct delayed_work thread;
601
602 struct mii_if_info mii;
603 unsigned int regs_len;
604 unsigned long fifo_copy_timeout;
605 };
606
607 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
608 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
609 MODULE_LICENSE("GPL");
610 MODULE_VERSION(DRV_VERSION);
611
612 module_param(use_io, int, 0);
613 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
614 module_param(multicast_filter_limit, int, 0);
615 module_param_array(media, int, NULL, 0);
616 module_param_array(full_duplex, int, NULL, 0);
617 module_param(debug, int, 0);
618 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
619 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
620 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
621 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
622
623 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
624 static int rtl8139_open (struct net_device *dev);
625 static int mdio_read (struct net_device *dev, int phy_id, int location);
626 static void mdio_write (struct net_device *dev, int phy_id, int location,
627 int val);
628 static void rtl8139_start_thread(struct rtl8139_private *tp);
629 static void rtl8139_tx_timeout (struct net_device *dev);
630 static void rtl8139_init_ring (struct net_device *dev);
631 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
632 struct net_device *dev);
633 #ifdef CONFIG_NET_POLL_CONTROLLER
634 static void rtl8139_poll_controller(struct net_device *dev);
635 #endif
636 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
637 static int rtl8139_poll(struct napi_struct *napi, int budget);
638 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
639 static int rtl8139_close (struct net_device *dev);
640 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
641 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
642 static void rtl8139_set_rx_mode (struct net_device *dev);
643 static void __set_rx_mode (struct net_device *dev);
644 static void rtl8139_hw_start (struct net_device *dev);
645 static void rtl8139_thread (struct work_struct *work);
646 static void rtl8139_tx_timeout_task(struct work_struct *work);
647 static const struct ethtool_ops rtl8139_ethtool_ops;
648
649 /* write MMIO register, with flush */
650 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
651 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
652 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
653 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
654
655 /* write MMIO register */
656 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
657 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
658 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
659
660 /* read MMIO register */
661 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
662 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
663 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
664
665
666 static const u16 rtl8139_intr_mask =
667 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
668 TxErr | TxOK | RxErr | RxOK;
669
670 static const u16 rtl8139_norx_intr_mask =
671 PCIErr | PCSTimeout | RxUnderrun |
672 TxErr | TxOK | RxErr ;
673
674 #if RX_BUF_IDX == 0
675 static const unsigned int rtl8139_rx_config =
676 RxCfgRcv8K | RxNoWrap |
677 (RX_FIFO_THRESH << RxCfgFIFOShift) |
678 (RX_DMA_BURST << RxCfgDMAShift);
679 #elif RX_BUF_IDX == 1
680 static const unsigned int rtl8139_rx_config =
681 RxCfgRcv16K | RxNoWrap |
682 (RX_FIFO_THRESH << RxCfgFIFOShift) |
683 (RX_DMA_BURST << RxCfgDMAShift);
684 #elif RX_BUF_IDX == 2
685 static const unsigned int rtl8139_rx_config =
686 RxCfgRcv32K | RxNoWrap |
687 (RX_FIFO_THRESH << RxCfgFIFOShift) |
688 (RX_DMA_BURST << RxCfgDMAShift);
689 #elif RX_BUF_IDX == 3
690 static const unsigned int rtl8139_rx_config =
691 RxCfgRcv64K |
692 (RX_FIFO_THRESH << RxCfgFIFOShift) |
693 (RX_DMA_BURST << RxCfgDMAShift);
694 #else
695 #error "Invalid configuration for 8139_RXBUF_IDX"
696 #endif
697
698 static const unsigned int rtl8139_tx_config =
699 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
700
701 static void __rtl8139_cleanup_dev (struct net_device *dev)
702 {
703 struct rtl8139_private *tp = netdev_priv(dev);
704 struct pci_dev *pdev;
705
706 assert (dev != NULL);
707 assert (tp->pci_dev != NULL);
708 pdev = tp->pci_dev;
709
710 if (tp->mmio_addr)
711 pci_iounmap (pdev, tp->mmio_addr);
712
713 /* it's ok to call this even if we have no regions to free */
714 pci_release_regions (pdev);
715
716 free_netdev(dev);
717 pci_set_drvdata (pdev, NULL);
718 }
719
720
721 static void rtl8139_chip_reset (void __iomem *ioaddr)
722 {
723 int i;
724
725 /* Soft reset the chip. */
726 RTL_W8 (ChipCmd, CmdReset);
727
728 /* Check that the chip has finished the reset. */
729 for (i = 1000; i > 0; i--) {
730 barrier();
731 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
732 break;
733 udelay (10);
734 }
735 }
736
737
738 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
739 {
740 void __iomem *ioaddr;
741 struct net_device *dev;
742 struct rtl8139_private *tp;
743 u8 tmp8;
744 int rc, disable_dev_on_err = 0;
745 unsigned int i;
746 unsigned long pio_start, pio_end, pio_flags, pio_len;
747 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
748 u32 version;
749
750 assert (pdev != NULL);
751
752 /* dev and priv zeroed in alloc_etherdev */
753 dev = alloc_etherdev (sizeof (*tp));
754 if (dev == NULL) {
755 dev_err(&pdev->dev, "Unable to alloc new net device\n");
756 return ERR_PTR(-ENOMEM);
757 }
758 SET_NETDEV_DEV(dev, &pdev->dev);
759
760 tp = netdev_priv(dev);
761 tp->pci_dev = pdev;
762
763 /* enable device (incl. PCI PM wakeup and hotplug setup) */
764 rc = pci_enable_device (pdev);
765 if (rc)
766 goto err_out;
767
768 pio_start = pci_resource_start (pdev, 0);
769 pio_end = pci_resource_end (pdev, 0);
770 pio_flags = pci_resource_flags (pdev, 0);
771 pio_len = pci_resource_len (pdev, 0);
772
773 mmio_start = pci_resource_start (pdev, 1);
774 mmio_end = pci_resource_end (pdev, 1);
775 mmio_flags = pci_resource_flags (pdev, 1);
776 mmio_len = pci_resource_len (pdev, 1);
777
778 /* set this immediately, we need to know before
779 * we talk to the chip directly */
780 pr_debug("PIO region size == 0x%02lX\n", pio_len);
781 pr_debug("MMIO region size == 0x%02lX\n", mmio_len);
782
783 retry:
784 if (use_io) {
785 /* make sure PCI base addr 0 is PIO */
786 if (!(pio_flags & IORESOURCE_IO)) {
787 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
788 rc = -ENODEV;
789 goto err_out;
790 }
791 /* check for weird/broken PCI region reporting */
792 if (pio_len < RTL_MIN_IO_SIZE) {
793 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
794 rc = -ENODEV;
795 goto err_out;
796 }
797 } else {
798 /* make sure PCI base addr 1 is MMIO */
799 if (!(mmio_flags & IORESOURCE_MEM)) {
800 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
801 rc = -ENODEV;
802 goto err_out;
803 }
804 if (mmio_len < RTL_MIN_IO_SIZE) {
805 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
806 rc = -ENODEV;
807 goto err_out;
808 }
809 }
810
811 rc = pci_request_regions (pdev, DRV_NAME);
812 if (rc)
813 goto err_out;
814 disable_dev_on_err = 1;
815
816 /* enable PCI bus-mastering */
817 pci_set_master (pdev);
818
819 if (use_io) {
820 ioaddr = pci_iomap(pdev, 0, 0);
821 if (!ioaddr) {
822 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
823 rc = -EIO;
824 goto err_out;
825 }
826 dev->base_addr = pio_start;
827 tp->regs_len = pio_len;
828 } else {
829 /* ioremap MMIO region */
830 ioaddr = pci_iomap(pdev, 1, 0);
831 if (ioaddr == NULL) {
832 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
833 pci_release_regions(pdev);
834 use_io = 1;
835 goto retry;
836 }
837 dev->base_addr = (long) ioaddr;
838 tp->regs_len = mmio_len;
839 }
840 tp->mmio_addr = ioaddr;
841
842 /* Bring old chips out of low-power mode. */
843 RTL_W8 (HltClk, 'R');
844
845 /* check for missing/broken hardware */
846 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
847 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
848 rc = -EIO;
849 goto err_out;
850 }
851
852 /* identify chip attached to board */
853 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
854 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
855 if (version == rtl_chip_info[i].version) {
856 tp->chipset = i;
857 goto match;
858 }
859
860 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
861 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
862 dev_dbg(&pdev->dev, "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
863 tp->chipset = 0;
864
865 match:
866 pr_debug("chipset id (%d) == index %d, '%s'\n",
867 version, i, rtl_chip_info[i].name);
868
869 if (tp->chipset >= CH_8139B) {
870 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
871 pr_debug("PCI PM wakeup\n");
872 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
873 (tmp8 & LWAKE))
874 new_tmp8 &= ~LWAKE;
875 new_tmp8 |= Cfg1_PM_Enable;
876 if (new_tmp8 != tmp8) {
877 RTL_W8 (Cfg9346, Cfg9346_Unlock);
878 RTL_W8 (Config1, tmp8);
879 RTL_W8 (Cfg9346, Cfg9346_Lock);
880 }
881 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
882 tmp8 = RTL_R8 (Config4);
883 if (tmp8 & LWPTN) {
884 RTL_W8 (Cfg9346, Cfg9346_Unlock);
885 RTL_W8 (Config4, tmp8 & ~LWPTN);
886 RTL_W8 (Cfg9346, Cfg9346_Lock);
887 }
888 }
889 } else {
890 pr_debug("Old chip wakeup\n");
891 tmp8 = RTL_R8 (Config1);
892 tmp8 &= ~(SLEEP | PWRDN);
893 RTL_W8 (Config1, tmp8);
894 }
895
896 rtl8139_chip_reset (ioaddr);
897
898 return dev;
899
900 err_out:
901 __rtl8139_cleanup_dev (dev);
902 if (disable_dev_on_err)
903 pci_disable_device (pdev);
904 return ERR_PTR(rc);
905 }
906
907 static const struct net_device_ops rtl8139_netdev_ops = {
908 .ndo_open = rtl8139_open,
909 .ndo_stop = rtl8139_close,
910 .ndo_get_stats = rtl8139_get_stats,
911 .ndo_change_mtu = eth_change_mtu,
912 .ndo_validate_addr = eth_validate_addr,
913 .ndo_set_mac_address = rtl8139_set_mac_address,
914 .ndo_start_xmit = rtl8139_start_xmit,
915 .ndo_set_multicast_list = rtl8139_set_rx_mode,
916 .ndo_do_ioctl = netdev_ioctl,
917 .ndo_tx_timeout = rtl8139_tx_timeout,
918 #ifdef CONFIG_NET_POLL_CONTROLLER
919 .ndo_poll_controller = rtl8139_poll_controller,
920 #endif
921 };
922
923 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
924 const struct pci_device_id *ent)
925 {
926 struct net_device *dev = NULL;
927 struct rtl8139_private *tp;
928 int i, addr_len, option;
929 void __iomem *ioaddr;
930 static int board_idx = -1;
931
932 assert (pdev != NULL);
933 assert (ent != NULL);
934
935 board_idx++;
936
937 /* when we're built into the kernel, the driver version message
938 * is only printed if at least one 8139 board has been found
939 */
940 #ifndef MODULE
941 {
942 static int printed_version;
943 if (!printed_version++)
944 pr_info(RTL8139_DRIVER_NAME "\n");
945 }
946 #endif
947
948 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
949 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
950 dev_info(&pdev->dev,
951 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
952 pdev->vendor, pdev->device, pdev->revision);
953 return -ENODEV;
954 }
955
956 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
957 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
958 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
959 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
960 pr_info("8139too: OQO Model 2 detected. Forcing PIO\n");
961 use_io = 1;
962 }
963
964 dev = rtl8139_init_board (pdev);
965 if (IS_ERR(dev))
966 return PTR_ERR(dev);
967
968 assert (dev != NULL);
969 tp = netdev_priv(dev);
970 tp->dev = dev;
971
972 ioaddr = tp->mmio_addr;
973 assert (ioaddr != NULL);
974
975 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
976 for (i = 0; i < 3; i++)
977 ((__le16 *) (dev->dev_addr))[i] =
978 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
979 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
980
981 /* The Rtl8139-specific entries in the device structure. */
982 dev->netdev_ops = &rtl8139_netdev_ops;
983 dev->ethtool_ops = &rtl8139_ethtool_ops;
984 dev->watchdog_timeo = TX_TIMEOUT;
985 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
986
987 /* note: the hardware is not capable of sg/csum/highdma, however
988 * through the use of skb_copy_and_csum_dev we enable these
989 * features
990 */
991 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
992
993 dev->irq = pdev->irq;
994
995 /* tp zeroed and aligned in alloc_etherdev */
996 tp = netdev_priv(dev);
997
998 /* note: tp->chipset set in rtl8139_init_board */
999 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1000 tp->mmio_addr = ioaddr;
1001 tp->msg_enable =
1002 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1003 spin_lock_init (&tp->lock);
1004 spin_lock_init (&tp->rx_lock);
1005 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1006 tp->mii.dev = dev;
1007 tp->mii.mdio_read = mdio_read;
1008 tp->mii.mdio_write = mdio_write;
1009 tp->mii.phy_id_mask = 0x3f;
1010 tp->mii.reg_num_mask = 0x1f;
1011
1012 /* dev is fully set up and ready to use now */
1013 pr_debug("about to register device named %s (%p)...\n", dev->name, dev);
1014 i = register_netdev (dev);
1015 if (i) goto err_out;
1016
1017 pci_set_drvdata (pdev, dev);
1018
1019 pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",
1020 dev->name,
1021 board_info[ent->driver_data].name,
1022 dev->base_addr,
1023 dev->dev_addr,
1024 dev->irq);
1025
1026 pr_debug("%s: Identified 8139 chip type '%s'\n",
1027 dev->name, rtl_chip_info[tp->chipset].name);
1028
1029 /* Find the connected MII xcvrs.
1030 Doing this in open() would allow detecting external xcvrs later, but
1031 takes too much time. */
1032 #ifdef CONFIG_8139TOO_8129
1033 if (tp->drv_flags & HAS_MII_XCVR) {
1034 int phy, phy_idx = 0;
1035 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1036 int mii_status = mdio_read(dev, phy, 1);
1037 if (mii_status != 0xffff && mii_status != 0x0000) {
1038 u16 advertising = mdio_read(dev, phy, 4);
1039 tp->phys[phy_idx++] = phy;
1040 pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n",
1041 dev->name, phy, mii_status, advertising);
1042 }
1043 }
1044 if (phy_idx == 0) {
1045 pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n",
1046 dev->name);
1047 tp->phys[0] = 32;
1048 }
1049 } else
1050 #endif
1051 tp->phys[0] = 32;
1052 tp->mii.phy_id = tp->phys[0];
1053
1054 /* The lower four bits are the media type. */
1055 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1056 if (option > 0) {
1057 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1058 tp->default_port = option & 0xFF;
1059 if (tp->default_port)
1060 tp->mii.force_media = 1;
1061 }
1062 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1063 tp->mii.full_duplex = full_duplex[board_idx];
1064 if (tp->mii.full_duplex) {
1065 pr_info("%s: Media type forced to Full Duplex.\n", dev->name);
1066 /* Changing the MII-advertised media because might prevent
1067 re-connection. */
1068 tp->mii.force_media = 1;
1069 }
1070 if (tp->default_port) {
1071 pr_info(" Forcing %dMbps %s-duplex operation.\n",
1072 (option & 0x20 ? 100 : 10),
1073 (option & 0x10 ? "full" : "half"));
1074 mdio_write(dev, tp->phys[0], 0,
1075 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1076 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1077 }
1078
1079 /* Put the chip into low-power mode. */
1080 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1081 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1082
1083 return 0;
1084
1085 err_out:
1086 __rtl8139_cleanup_dev (dev);
1087 pci_disable_device (pdev);
1088 return i;
1089 }
1090
1091
1092 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1093 {
1094 struct net_device *dev = pci_get_drvdata (pdev);
1095
1096 assert (dev != NULL);
1097
1098 flush_scheduled_work();
1099
1100 unregister_netdev (dev);
1101
1102 __rtl8139_cleanup_dev (dev);
1103 pci_disable_device (pdev);
1104 }
1105
1106
1107 /* Serial EEPROM section. */
1108
1109 /* EEPROM_Ctrl bits. */
1110 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1111 #define EE_CS 0x08 /* EEPROM chip select. */
1112 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1113 #define EE_WRITE_0 0x00
1114 #define EE_WRITE_1 0x02
1115 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1116 #define EE_ENB (0x80 | EE_CS)
1117
1118 /* Delay between EEPROM clock transitions.
1119 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1120 */
1121
1122 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1123
1124 /* The EEPROM commands include the alway-set leading bit. */
1125 #define EE_WRITE_CMD (5)
1126 #define EE_READ_CMD (6)
1127 #define EE_ERASE_CMD (7)
1128
1129 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1130 {
1131 int i;
1132 unsigned retval = 0;
1133 int read_cmd = location | (EE_READ_CMD << addr_len);
1134
1135 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1136 RTL_W8 (Cfg9346, EE_ENB);
1137 eeprom_delay ();
1138
1139 /* Shift the read command bits out. */
1140 for (i = 4 + addr_len; i >= 0; i--) {
1141 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1142 RTL_W8 (Cfg9346, EE_ENB | dataval);
1143 eeprom_delay ();
1144 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1145 eeprom_delay ();
1146 }
1147 RTL_W8 (Cfg9346, EE_ENB);
1148 eeprom_delay ();
1149
1150 for (i = 16; i > 0; i--) {
1151 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1152 eeprom_delay ();
1153 retval =
1154 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1155 0);
1156 RTL_W8 (Cfg9346, EE_ENB);
1157 eeprom_delay ();
1158 }
1159
1160 /* Terminate the EEPROM access. */
1161 RTL_W8 (Cfg9346, ~EE_CS);
1162 eeprom_delay ();
1163
1164 return retval;
1165 }
1166
1167 /* MII serial management: mostly bogus for now. */
1168 /* Read and write the MII management registers using software-generated
1169 serial MDIO protocol.
1170 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1171 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1172 "overclocking" issues. */
1173 #define MDIO_DIR 0x80
1174 #define MDIO_DATA_OUT 0x04
1175 #define MDIO_DATA_IN 0x02
1176 #define MDIO_CLK 0x01
1177 #define MDIO_WRITE0 (MDIO_DIR)
1178 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1179
1180 #define mdio_delay() RTL_R8(Config4)
1181
1182
1183 static const char mii_2_8139_map[8] = {
1184 BasicModeCtrl,
1185 BasicModeStatus,
1186 0,
1187 0,
1188 NWayAdvert,
1189 NWayLPAR,
1190 NWayExpansion,
1191 0
1192 };
1193
1194
1195 #ifdef CONFIG_8139TOO_8129
1196 /* Syncronize the MII management interface by shifting 32 one bits out. */
1197 static void mdio_sync (void __iomem *ioaddr)
1198 {
1199 int i;
1200
1201 for (i = 32; i >= 0; i--) {
1202 RTL_W8 (Config4, MDIO_WRITE1);
1203 mdio_delay ();
1204 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1205 mdio_delay ();
1206 }
1207 }
1208 #endif
1209
1210 static int mdio_read (struct net_device *dev, int phy_id, int location)
1211 {
1212 struct rtl8139_private *tp = netdev_priv(dev);
1213 int retval = 0;
1214 #ifdef CONFIG_8139TOO_8129
1215 void __iomem *ioaddr = tp->mmio_addr;
1216 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1217 int i;
1218 #endif
1219
1220 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1221 void __iomem *ioaddr = tp->mmio_addr;
1222 return location < 8 && mii_2_8139_map[location] ?
1223 RTL_R16 (mii_2_8139_map[location]) : 0;
1224 }
1225
1226 #ifdef CONFIG_8139TOO_8129
1227 mdio_sync (ioaddr);
1228 /* Shift the read command bits out. */
1229 for (i = 15; i >= 0; i--) {
1230 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1231
1232 RTL_W8 (Config4, MDIO_DIR | dataval);
1233 mdio_delay ();
1234 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1235 mdio_delay ();
1236 }
1237
1238 /* Read the two transition, 16 data, and wire-idle bits. */
1239 for (i = 19; i > 0; i--) {
1240 RTL_W8 (Config4, 0);
1241 mdio_delay ();
1242 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1243 RTL_W8 (Config4, MDIO_CLK);
1244 mdio_delay ();
1245 }
1246 #endif
1247
1248 return (retval >> 1) & 0xffff;
1249 }
1250
1251
1252 static void mdio_write (struct net_device *dev, int phy_id, int location,
1253 int value)
1254 {
1255 struct rtl8139_private *tp = netdev_priv(dev);
1256 #ifdef CONFIG_8139TOO_8129
1257 void __iomem *ioaddr = tp->mmio_addr;
1258 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1259 int i;
1260 #endif
1261
1262 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1263 void __iomem *ioaddr = tp->mmio_addr;
1264 if (location == 0) {
1265 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1266 RTL_W16 (BasicModeCtrl, value);
1267 RTL_W8 (Cfg9346, Cfg9346_Lock);
1268 } else if (location < 8 && mii_2_8139_map[location])
1269 RTL_W16 (mii_2_8139_map[location], value);
1270 return;
1271 }
1272
1273 #ifdef CONFIG_8139TOO_8129
1274 mdio_sync (ioaddr);
1275
1276 /* Shift the command bits out. */
1277 for (i = 31; i >= 0; i--) {
1278 int dataval =
1279 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1280 RTL_W8 (Config4, dataval);
1281 mdio_delay ();
1282 RTL_W8 (Config4, dataval | MDIO_CLK);
1283 mdio_delay ();
1284 }
1285 /* Clear out extra bits. */
1286 for (i = 2; i > 0; i--) {
1287 RTL_W8 (Config4, 0);
1288 mdio_delay ();
1289 RTL_W8 (Config4, MDIO_CLK);
1290 mdio_delay ();
1291 }
1292 #endif
1293 }
1294
1295
1296 static int rtl8139_open (struct net_device *dev)
1297 {
1298 struct rtl8139_private *tp = netdev_priv(dev);
1299 int retval;
1300 void __iomem *ioaddr = tp->mmio_addr;
1301
1302 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1303 if (retval)
1304 return retval;
1305
1306 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1307 &tp->tx_bufs_dma, GFP_KERNEL);
1308 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1309 &tp->rx_ring_dma, GFP_KERNEL);
1310 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1311 free_irq(dev->irq, dev);
1312
1313 if (tp->tx_bufs)
1314 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1315 tp->tx_bufs, tp->tx_bufs_dma);
1316 if (tp->rx_ring)
1317 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1318 tp->rx_ring, tp->rx_ring_dma);
1319
1320 return -ENOMEM;
1321
1322 }
1323
1324 napi_enable(&tp->napi);
1325
1326 tp->mii.full_duplex = tp->mii.force_media;
1327 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1328
1329 rtl8139_init_ring (dev);
1330 rtl8139_hw_start (dev);
1331 netif_start_queue (dev);
1332
1333 if (netif_msg_ifup(tp))
1334 pr_debug("%s: rtl8139_open() ioaddr %#llx IRQ %d"
1335 " GP Pins %2.2x %s-duplex.\n", dev->name,
1336 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1337 dev->irq, RTL_R8 (MediaStatus),
1338 tp->mii.full_duplex ? "full" : "half");
1339
1340 rtl8139_start_thread(tp);
1341
1342 return 0;
1343 }
1344
1345
1346 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1347 {
1348 struct rtl8139_private *tp = netdev_priv(dev);
1349
1350 if (tp->phys[0] >= 0) {
1351 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1352 }
1353 }
1354
1355 /* Start the hardware at open or resume. */
1356 static void rtl8139_hw_start (struct net_device *dev)
1357 {
1358 struct rtl8139_private *tp = netdev_priv(dev);
1359 void __iomem *ioaddr = tp->mmio_addr;
1360 u32 i;
1361 u8 tmp;
1362
1363 /* Bring old chips out of low-power mode. */
1364 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1365 RTL_W8 (HltClk, 'R');
1366
1367 rtl8139_chip_reset (ioaddr);
1368
1369 /* unlock Config[01234] and BMCR register writes */
1370 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1371 /* Restore our idea of the MAC address. */
1372 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1373 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1374
1375 tp->cur_rx = 0;
1376
1377 /* init Rx ring buffer DMA address */
1378 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1379
1380 /* Must enable Tx/Rx before setting transfer thresholds! */
1381 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1382
1383 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1384 RTL_W32 (RxConfig, tp->rx_config);
1385 RTL_W32 (TxConfig, rtl8139_tx_config);
1386
1387 rtl_check_media (dev, 1);
1388
1389 if (tp->chipset >= CH_8139B) {
1390 /* Disable magic packet scanning, which is enabled
1391 * when PM is enabled in Config1. It can be reenabled
1392 * via ETHTOOL_SWOL if desired. */
1393 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1394 }
1395
1396 pr_debug("init buffer addresses\n");
1397
1398 /* Lock Config[01234] and BMCR register writes */
1399 RTL_W8 (Cfg9346, Cfg9346_Lock);
1400
1401 /* init Tx buffer DMA addresses */
1402 for (i = 0; i < NUM_TX_DESC; i++)
1403 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1404
1405 RTL_W32 (RxMissed, 0);
1406
1407 rtl8139_set_rx_mode (dev);
1408
1409 /* no early-rx interrupts */
1410 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1411
1412 /* make sure RxTx has started */
1413 tmp = RTL_R8 (ChipCmd);
1414 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1415 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1416
1417 /* Enable all known interrupts by setting the interrupt mask. */
1418 RTL_W16 (IntrMask, rtl8139_intr_mask);
1419 }
1420
1421
1422 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1423 static void rtl8139_init_ring (struct net_device *dev)
1424 {
1425 struct rtl8139_private *tp = netdev_priv(dev);
1426 int i;
1427
1428 tp->cur_rx = 0;
1429 tp->cur_tx = 0;
1430 tp->dirty_tx = 0;
1431
1432 for (i = 0; i < NUM_TX_DESC; i++)
1433 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1434 }
1435
1436
1437 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1438 static int next_tick = 3 * HZ;
1439
1440 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1441 static inline void rtl8139_tune_twister (struct net_device *dev,
1442 struct rtl8139_private *tp) {}
1443 #else
1444 enum TwisterParamVals {
1445 PARA78_default = 0x78fa8388,
1446 PARA7c_default = 0xcb38de43, /* param[0][3] */
1447 PARA7c_xxx = 0xcb38de43,
1448 };
1449
1450 static const unsigned long param[4][4] = {
1451 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1452 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1453 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1454 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1455 };
1456
1457 static void rtl8139_tune_twister (struct net_device *dev,
1458 struct rtl8139_private *tp)
1459 {
1460 int linkcase;
1461 void __iomem *ioaddr = tp->mmio_addr;
1462
1463 /* This is a complicated state machine to configure the "twister" for
1464 impedance/echos based on the cable length.
1465 All of this is magic and undocumented.
1466 */
1467 switch (tp->twistie) {
1468 case 1:
1469 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1470 /* We have link beat, let us tune the twister. */
1471 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1472 tp->twistie = 2; /* Change to state 2. */
1473 next_tick = HZ / 10;
1474 } else {
1475 /* Just put in some reasonable defaults for when beat returns. */
1476 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1477 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1478 RTL_W32 (PARA78, PARA78_default);
1479 RTL_W32 (PARA7c, PARA7c_default);
1480 tp->twistie = 0; /* Bail from future actions. */
1481 }
1482 break;
1483 case 2:
1484 /* Read how long it took to hear the echo. */
1485 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1486 if (linkcase == 0x7000)
1487 tp->twist_row = 3;
1488 else if (linkcase == 0x3000)
1489 tp->twist_row = 2;
1490 else if (linkcase == 0x1000)
1491 tp->twist_row = 1;
1492 else
1493 tp->twist_row = 0;
1494 tp->twist_col = 0;
1495 tp->twistie = 3; /* Change to state 2. */
1496 next_tick = HZ / 10;
1497 break;
1498 case 3:
1499 /* Put out four tuning parameters, one per 100msec. */
1500 if (tp->twist_col == 0)
1501 RTL_W16 (FIFOTMS, 0);
1502 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1503 [(int) tp->twist_col]);
1504 next_tick = HZ / 10;
1505 if (++tp->twist_col >= 4) {
1506 /* For short cables we are done.
1507 For long cables (row == 3) check for mistune. */
1508 tp->twistie =
1509 (tp->twist_row == 3) ? 4 : 0;
1510 }
1511 break;
1512 case 4:
1513 /* Special case for long cables: check for mistune. */
1514 if ((RTL_R16 (CSCR) &
1515 CSCR_LinkStatusBits) == 0x7000) {
1516 tp->twistie = 0;
1517 break;
1518 } else {
1519 RTL_W32 (PARA7c, 0xfb38de03);
1520 tp->twistie = 5;
1521 next_tick = HZ / 10;
1522 }
1523 break;
1524 case 5:
1525 /* Retune for shorter cable (column 2). */
1526 RTL_W32 (FIFOTMS, 0x20);
1527 RTL_W32 (PARA78, PARA78_default);
1528 RTL_W32 (PARA7c, PARA7c_default);
1529 RTL_W32 (FIFOTMS, 0x00);
1530 tp->twist_row = 2;
1531 tp->twist_col = 0;
1532 tp->twistie = 3;
1533 next_tick = HZ / 10;
1534 break;
1535
1536 default:
1537 /* do nothing */
1538 break;
1539 }
1540 }
1541 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1542
1543 static inline void rtl8139_thread_iter (struct net_device *dev,
1544 struct rtl8139_private *tp,
1545 void __iomem *ioaddr)
1546 {
1547 int mii_lpa;
1548
1549 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1550
1551 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1552 int duplex = (mii_lpa & LPA_100FULL)
1553 || (mii_lpa & 0x01C0) == 0x0040;
1554 if (tp->mii.full_duplex != duplex) {
1555 tp->mii.full_duplex = duplex;
1556
1557 if (mii_lpa) {
1558 pr_info("%s: Setting %s-duplex based on MII #%d link"
1559 " partner ability of %4.4x.\n",
1560 dev->name,
1561 tp->mii.full_duplex ? "full" : "half",
1562 tp->phys[0], mii_lpa);
1563 } else {
1564 pr_info("%s: media is unconnected, link down, or incompatible connection\n",
1565 dev->name);
1566 }
1567 #if 0
1568 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1569 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1570 RTL_W8 (Cfg9346, Cfg9346_Lock);
1571 #endif
1572 }
1573 }
1574
1575 next_tick = HZ * 60;
1576
1577 rtl8139_tune_twister (dev, tp);
1578
1579 pr_debug("%s: Media selection tick, Link partner %4.4x.\n",
1580 dev->name, RTL_R16 (NWayLPAR));
1581 pr_debug("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1582 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1583 pr_debug("%s: Chip config %2.2x %2.2x.\n",
1584 dev->name, RTL_R8 (Config0),
1585 RTL_R8 (Config1));
1586 }
1587
1588 static void rtl8139_thread (struct work_struct *work)
1589 {
1590 struct rtl8139_private *tp =
1591 container_of(work, struct rtl8139_private, thread.work);
1592 struct net_device *dev = tp->mii.dev;
1593 unsigned long thr_delay = next_tick;
1594
1595 rtnl_lock();
1596
1597 if (!netif_running(dev))
1598 goto out_unlock;
1599
1600 if (tp->watchdog_fired) {
1601 tp->watchdog_fired = 0;
1602 rtl8139_tx_timeout_task(work);
1603 } else
1604 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1605
1606 if (tp->have_thread)
1607 schedule_delayed_work(&tp->thread, thr_delay);
1608 out_unlock:
1609 rtnl_unlock ();
1610 }
1611
1612 static void rtl8139_start_thread(struct rtl8139_private *tp)
1613 {
1614 tp->twistie = 0;
1615 if (tp->chipset == CH_8139_K)
1616 tp->twistie = 1;
1617 else if (tp->drv_flags & HAS_LNK_CHNG)
1618 return;
1619
1620 tp->have_thread = 1;
1621 tp->watchdog_fired = 0;
1622
1623 schedule_delayed_work(&tp->thread, next_tick);
1624 }
1625
1626 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1627 {
1628 tp->cur_tx = 0;
1629 tp->dirty_tx = 0;
1630
1631 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1632 }
1633
1634 static void rtl8139_tx_timeout_task (struct work_struct *work)
1635 {
1636 struct rtl8139_private *tp =
1637 container_of(work, struct rtl8139_private, thread.work);
1638 struct net_device *dev = tp->mii.dev;
1639 void __iomem *ioaddr = tp->mmio_addr;
1640 int i;
1641 u8 tmp8;
1642
1643 pr_debug("%s: Transmit timeout, status %2.2x %4.4x %4.4x media %2.2x.\n",
1644 dev->name, RTL_R8 (ChipCmd),
1645 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1646 /* Emit info to figure out what went wrong. */
1647 pr_debug("%s: Tx queue start entry %ld dirty entry %ld.\n",
1648 dev->name, tp->cur_tx, tp->dirty_tx);
1649 for (i = 0; i < NUM_TX_DESC; i++)
1650 pr_debug("%s: Tx descriptor %d is %8.8lx.%s\n",
1651 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1652 i == tp->dirty_tx % NUM_TX_DESC ?
1653 " (queue head)" : "");
1654
1655 tp->xstats.tx_timeouts++;
1656
1657 /* disable Tx ASAP, if not already */
1658 tmp8 = RTL_R8 (ChipCmd);
1659 if (tmp8 & CmdTxEnb)
1660 RTL_W8 (ChipCmd, CmdRxEnb);
1661
1662 spin_lock_bh(&tp->rx_lock);
1663 /* Disable interrupts by clearing the interrupt mask. */
1664 RTL_W16 (IntrMask, 0x0000);
1665
1666 /* Stop a shared interrupt from scavenging while we are. */
1667 spin_lock_irq(&tp->lock);
1668 rtl8139_tx_clear (tp);
1669 spin_unlock_irq(&tp->lock);
1670
1671 /* ...and finally, reset everything */
1672 if (netif_running(dev)) {
1673 rtl8139_hw_start (dev);
1674 netif_wake_queue (dev);
1675 }
1676 spin_unlock_bh(&tp->rx_lock);
1677 }
1678
1679 static void rtl8139_tx_timeout (struct net_device *dev)
1680 {
1681 struct rtl8139_private *tp = netdev_priv(dev);
1682
1683 tp->watchdog_fired = 1;
1684 if (!tp->have_thread) {
1685 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1686 schedule_delayed_work(&tp->thread, next_tick);
1687 }
1688 }
1689
1690 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1691 struct net_device *dev)
1692 {
1693 struct rtl8139_private *tp = netdev_priv(dev);
1694 void __iomem *ioaddr = tp->mmio_addr;
1695 unsigned int entry;
1696 unsigned int len = skb->len;
1697 unsigned long flags;
1698
1699 /* Calculate the next Tx descriptor entry. */
1700 entry = tp->cur_tx % NUM_TX_DESC;
1701
1702 /* Note: the chip doesn't have auto-pad! */
1703 if (likely(len < TX_BUF_SIZE)) {
1704 if (len < ETH_ZLEN)
1705 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1706 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1707 dev_kfree_skb(skb);
1708 } else {
1709 dev_kfree_skb(skb);
1710 dev->stats.tx_dropped++;
1711 return NETDEV_TX_OK;
1712 }
1713
1714 spin_lock_irqsave(&tp->lock, flags);
1715 /*
1716 * Writing to TxStatus triggers a DMA transfer of the data
1717 * copied to tp->tx_buf[entry] above. Use a memory barrier
1718 * to make sure that the device sees the updated data.
1719 */
1720 wmb();
1721 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1722 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1723
1724 dev->trans_start = jiffies;
1725
1726 tp->cur_tx++;
1727
1728 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1729 netif_stop_queue (dev);
1730 spin_unlock_irqrestore(&tp->lock, flags);
1731
1732 if (netif_msg_tx_queued(tp))
1733 pr_debug("%s: Queued Tx packet size %u to slot %d.\n",
1734 dev->name, len, entry);
1735
1736 return NETDEV_TX_OK;
1737 }
1738
1739
1740 static void rtl8139_tx_interrupt (struct net_device *dev,
1741 struct rtl8139_private *tp,
1742 void __iomem *ioaddr)
1743 {
1744 unsigned long dirty_tx, tx_left;
1745
1746 assert (dev != NULL);
1747 assert (ioaddr != NULL);
1748
1749 dirty_tx = tp->dirty_tx;
1750 tx_left = tp->cur_tx - dirty_tx;
1751 while (tx_left > 0) {
1752 int entry = dirty_tx % NUM_TX_DESC;
1753 int txstatus;
1754
1755 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1756
1757 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1758 break; /* It still hasn't been Txed */
1759
1760 /* Note: TxCarrierLost is always asserted at 100mbps. */
1761 if (txstatus & (TxOutOfWindow | TxAborted)) {
1762 /* There was an major error, log it. */
1763 if (netif_msg_tx_err(tp))
1764 pr_debug("%s: Transmit error, Tx status %8.8x.\n",
1765 dev->name, txstatus);
1766 dev->stats.tx_errors++;
1767 if (txstatus & TxAborted) {
1768 dev->stats.tx_aborted_errors++;
1769 RTL_W32 (TxConfig, TxClearAbt);
1770 RTL_W16 (IntrStatus, TxErr);
1771 wmb();
1772 }
1773 if (txstatus & TxCarrierLost)
1774 dev->stats.tx_carrier_errors++;
1775 if (txstatus & TxOutOfWindow)
1776 dev->stats.tx_window_errors++;
1777 } else {
1778 if (txstatus & TxUnderrun) {
1779 /* Add 64 to the Tx FIFO threshold. */
1780 if (tp->tx_flag < 0x00300000)
1781 tp->tx_flag += 0x00020000;
1782 dev->stats.tx_fifo_errors++;
1783 }
1784 dev->stats.collisions += (txstatus >> 24) & 15;
1785 dev->stats.tx_bytes += txstatus & 0x7ff;
1786 dev->stats.tx_packets++;
1787 }
1788
1789 dirty_tx++;
1790 tx_left--;
1791 }
1792
1793 #ifndef RTL8139_NDEBUG
1794 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1795 pr_err("%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1796 dev->name, dirty_tx, tp->cur_tx);
1797 dirty_tx += NUM_TX_DESC;
1798 }
1799 #endif /* RTL8139_NDEBUG */
1800
1801 /* only wake the queue if we did work, and the queue is stopped */
1802 if (tp->dirty_tx != dirty_tx) {
1803 tp->dirty_tx = dirty_tx;
1804 mb();
1805 netif_wake_queue (dev);
1806 }
1807 }
1808
1809
1810 /* TODO: clean this up! Rx reset need not be this intensive */
1811 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1812 struct rtl8139_private *tp, void __iomem *ioaddr)
1813 {
1814 u8 tmp8;
1815 #ifdef CONFIG_8139_OLD_RX_RESET
1816 int tmp_work;
1817 #endif
1818
1819 if (netif_msg_rx_err (tp))
1820 pr_debug("%s: Ethernet frame had errors, status %8.8x.\n",
1821 dev->name, rx_status);
1822 dev->stats.rx_errors++;
1823 if (!(rx_status & RxStatusOK)) {
1824 if (rx_status & RxTooLong) {
1825 pr_debug("%s: Oversized Ethernet frame, status %4.4x!\n",
1826 dev->name, rx_status);
1827 /* A.C.: The chip hangs here. */
1828 }
1829 if (rx_status & (RxBadSymbol | RxBadAlign))
1830 dev->stats.rx_frame_errors++;
1831 if (rx_status & (RxRunt | RxTooLong))
1832 dev->stats.rx_length_errors++;
1833 if (rx_status & RxCRCErr)
1834 dev->stats.rx_crc_errors++;
1835 } else {
1836 tp->xstats.rx_lost_in_ring++;
1837 }
1838
1839 #ifndef CONFIG_8139_OLD_RX_RESET
1840 tmp8 = RTL_R8 (ChipCmd);
1841 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1842 RTL_W8 (ChipCmd, tmp8);
1843 RTL_W32 (RxConfig, tp->rx_config);
1844 tp->cur_rx = 0;
1845 #else
1846 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1847
1848 /* disable receive */
1849 RTL_W8_F (ChipCmd, CmdTxEnb);
1850 tmp_work = 200;
1851 while (--tmp_work > 0) {
1852 udelay(1);
1853 tmp8 = RTL_R8 (ChipCmd);
1854 if (!(tmp8 & CmdRxEnb))
1855 break;
1856 }
1857 if (tmp_work <= 0)
1858 pr_warning(PFX "rx stop wait too long\n");
1859 /* restart receive */
1860 tmp_work = 200;
1861 while (--tmp_work > 0) {
1862 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1863 udelay(1);
1864 tmp8 = RTL_R8 (ChipCmd);
1865 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1866 break;
1867 }
1868 if (tmp_work <= 0)
1869 pr_warning(PFX "tx/rx enable wait too long\n");
1870
1871 /* and reinitialize all rx related registers */
1872 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1873 /* Must enable Tx/Rx before setting transfer thresholds! */
1874 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1875
1876 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1877 RTL_W32 (RxConfig, tp->rx_config);
1878 tp->cur_rx = 0;
1879
1880 pr_debug("init buffer addresses\n");
1881
1882 /* Lock Config[01234] and BMCR register writes */
1883 RTL_W8 (Cfg9346, Cfg9346_Lock);
1884
1885 /* init Rx ring buffer DMA address */
1886 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1887
1888 /* A.C.: Reset the multicast list. */
1889 __set_rx_mode (dev);
1890 #endif
1891 }
1892
1893 #if RX_BUF_IDX == 3
1894 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1895 u32 offset, unsigned int size)
1896 {
1897 u32 left = RX_BUF_LEN - offset;
1898
1899 if (size > left) {
1900 skb_copy_to_linear_data(skb, ring + offset, left);
1901 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1902 } else
1903 skb_copy_to_linear_data(skb, ring + offset, size);
1904 }
1905 #endif
1906
1907 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1908 {
1909 void __iomem *ioaddr = tp->mmio_addr;
1910 u16 status;
1911
1912 status = RTL_R16 (IntrStatus) & RxAckBits;
1913
1914 /* Clear out errors and receive interrupts */
1915 if (likely(status != 0)) {
1916 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1917 tp->dev->stats.rx_errors++;
1918 if (status & RxFIFOOver)
1919 tp->dev->stats.rx_fifo_errors++;
1920 }
1921 RTL_W16_F (IntrStatus, RxAckBits);
1922 }
1923 }
1924
1925 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1926 int budget)
1927 {
1928 void __iomem *ioaddr = tp->mmio_addr;
1929 int received = 0;
1930 unsigned char *rx_ring = tp->rx_ring;
1931 unsigned int cur_rx = tp->cur_rx;
1932 unsigned int rx_size = 0;
1933
1934 pr_debug("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1935 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1936 RTL_R16 (RxBufAddr),
1937 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1938
1939 while (netif_running(dev) && received < budget
1940 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1941 u32 ring_offset = cur_rx % RX_BUF_LEN;
1942 u32 rx_status;
1943 unsigned int pkt_size;
1944 struct sk_buff *skb;
1945
1946 rmb();
1947
1948 /* read size+status of next frame from DMA ring buffer */
1949 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1950 rx_size = rx_status >> 16;
1951 pkt_size = rx_size - 4;
1952
1953 if (netif_msg_rx_status(tp))
1954 pr_debug("%s: rtl8139_rx() status %4.4x, size %4.4x,"
1955 " cur %4.4x.\n", dev->name, rx_status,
1956 rx_size, cur_rx);
1957 #if RTL8139_DEBUG > 2
1958 {
1959 int i;
1960 pr_debug("%s: Frame contents ", dev->name);
1961 for (i = 0; i < 70; i++)
1962 pr_cont(" %2.2x",
1963 rx_ring[ring_offset + i]);
1964 pr_cont(".\n");
1965 }
1966 #endif
1967
1968 /* Packet copy from FIFO still in progress.
1969 * Theoretically, this should never happen
1970 * since EarlyRx is disabled.
1971 */
1972 if (unlikely(rx_size == 0xfff0)) {
1973 if (!tp->fifo_copy_timeout)
1974 tp->fifo_copy_timeout = jiffies + 2;
1975 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1976 pr_debug("%s: hung FIFO. Reset.", dev->name);
1977 rx_size = 0;
1978 goto no_early_rx;
1979 }
1980 if (netif_msg_intr(tp)) {
1981 pr_debug("%s: fifo copy in progress.",
1982 dev->name);
1983 }
1984 tp->xstats.early_rx++;
1985 break;
1986 }
1987
1988 no_early_rx:
1989 tp->fifo_copy_timeout = 0;
1990
1991 /* If Rx err or invalid rx_size/rx_status received
1992 * (which happens if we get lost in the ring),
1993 * Rx process gets reset, so we abort any further
1994 * Rx processing.
1995 */
1996 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1997 (rx_size < 8) ||
1998 (!(rx_status & RxStatusOK)))) {
1999 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2000 received = -1;
2001 goto out;
2002 }
2003
2004 /* Malloc up new buffer, compatible with net-2e. */
2005 /* Omit the four octet CRC from the length. */
2006
2007 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
2008 if (likely(skb)) {
2009 skb_reserve (skb, NET_IP_ALIGN); /* 16 byte align the IP fields. */
2010 #if RX_BUF_IDX == 3
2011 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2012 #else
2013 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2014 #endif
2015 skb_put (skb, pkt_size);
2016
2017 skb->protocol = eth_type_trans (skb, dev);
2018
2019 dev->stats.rx_bytes += pkt_size;
2020 dev->stats.rx_packets++;
2021
2022 netif_receive_skb (skb);
2023 } else {
2024 if (net_ratelimit())
2025 pr_warning("%s: Memory squeeze, dropping packet.\n",
2026 dev->name);
2027 dev->stats.rx_dropped++;
2028 }
2029 received++;
2030
2031 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2032 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2033
2034 rtl8139_isr_ack(tp);
2035 }
2036
2037 if (unlikely(!received || rx_size == 0xfff0))
2038 rtl8139_isr_ack(tp);
2039
2040 pr_debug("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2041 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2042 RTL_R16 (RxBufAddr),
2043 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2044
2045 tp->cur_rx = cur_rx;
2046
2047 /*
2048 * The receive buffer should be mostly empty.
2049 * Tell NAPI to reenable the Rx irq.
2050 */
2051 if (tp->fifo_copy_timeout)
2052 received = budget;
2053
2054 out:
2055 return received;
2056 }
2057
2058
2059 static void rtl8139_weird_interrupt (struct net_device *dev,
2060 struct rtl8139_private *tp,
2061 void __iomem *ioaddr,
2062 int status, int link_changed)
2063 {
2064 pr_debug("%s: Abnormal interrupt, status %8.8x.\n",
2065 dev->name, status);
2066
2067 assert (dev != NULL);
2068 assert (tp != NULL);
2069 assert (ioaddr != NULL);
2070
2071 /* Update the error count. */
2072 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2073 RTL_W32 (RxMissed, 0);
2074
2075 if ((status & RxUnderrun) && link_changed &&
2076 (tp->drv_flags & HAS_LNK_CHNG)) {
2077 rtl_check_media(dev, 0);
2078 status &= ~RxUnderrun;
2079 }
2080
2081 if (status & (RxUnderrun | RxErr))
2082 dev->stats.rx_errors++;
2083
2084 if (status & PCSTimeout)
2085 dev->stats.rx_length_errors++;
2086 if (status & RxUnderrun)
2087 dev->stats.rx_fifo_errors++;
2088 if (status & PCIErr) {
2089 u16 pci_cmd_status;
2090 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2091 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2092
2093 pr_err("%s: PCI Bus error %4.4x.\n",
2094 dev->name, pci_cmd_status);
2095 }
2096 }
2097
2098 static int rtl8139_poll(struct napi_struct *napi, int budget)
2099 {
2100 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2101 struct net_device *dev = tp->dev;
2102 void __iomem *ioaddr = tp->mmio_addr;
2103 int work_done;
2104
2105 spin_lock(&tp->rx_lock);
2106 work_done = 0;
2107 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2108 work_done += rtl8139_rx(dev, tp, budget);
2109
2110 if (work_done < budget) {
2111 unsigned long flags;
2112 /*
2113 * Order is important since data can get interrupted
2114 * again when we think we are done.
2115 */
2116 spin_lock_irqsave(&tp->lock, flags);
2117 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2118 __napi_complete(napi);
2119 spin_unlock_irqrestore(&tp->lock, flags);
2120 }
2121 spin_unlock(&tp->rx_lock);
2122
2123 return work_done;
2124 }
2125
2126 /* The interrupt handler does all of the Rx thread work and cleans up
2127 after the Tx thread. */
2128 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2129 {
2130 struct net_device *dev = (struct net_device *) dev_instance;
2131 struct rtl8139_private *tp = netdev_priv(dev);
2132 void __iomem *ioaddr = tp->mmio_addr;
2133 u16 status, ackstat;
2134 int link_changed = 0; /* avoid bogus "uninit" warning */
2135 int handled = 0;
2136
2137 spin_lock (&tp->lock);
2138 status = RTL_R16 (IntrStatus);
2139
2140 /* shared irq? */
2141 if (unlikely((status & rtl8139_intr_mask) == 0))
2142 goto out;
2143
2144 handled = 1;
2145
2146 /* h/w no longer present (hotplug?) or major error, bail */
2147 if (unlikely(status == 0xFFFF))
2148 goto out;
2149
2150 /* close possible race's with dev_close */
2151 if (unlikely(!netif_running(dev))) {
2152 RTL_W16 (IntrMask, 0);
2153 goto out;
2154 }
2155
2156 /* Acknowledge all of the current interrupt sources ASAP, but
2157 an first get an additional status bit from CSCR. */
2158 if (unlikely(status & RxUnderrun))
2159 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2160
2161 ackstat = status & ~(RxAckBits | TxErr);
2162 if (ackstat)
2163 RTL_W16 (IntrStatus, ackstat);
2164
2165 /* Receive packets are processed by poll routine.
2166 If not running start it now. */
2167 if (status & RxAckBits){
2168 if (napi_schedule_prep(&tp->napi)) {
2169 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2170 __napi_schedule(&tp->napi);
2171 }
2172 }
2173
2174 /* Check uncommon events with one test. */
2175 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2176 rtl8139_weird_interrupt (dev, tp, ioaddr,
2177 status, link_changed);
2178
2179 if (status & (TxOK | TxErr)) {
2180 rtl8139_tx_interrupt (dev, tp, ioaddr);
2181 if (status & TxErr)
2182 RTL_W16 (IntrStatus, TxErr);
2183 }
2184 out:
2185 spin_unlock (&tp->lock);
2186
2187 pr_debug("%s: exiting interrupt, intr_status=%#4.4x.\n",
2188 dev->name, RTL_R16 (IntrStatus));
2189 return IRQ_RETVAL(handled);
2190 }
2191
2192 #ifdef CONFIG_NET_POLL_CONTROLLER
2193 /*
2194 * Polling receive - used by netconsole and other diagnostic tools
2195 * to allow network i/o with interrupts disabled.
2196 */
2197 static void rtl8139_poll_controller(struct net_device *dev)
2198 {
2199 disable_irq(dev->irq);
2200 rtl8139_interrupt(dev->irq, dev);
2201 enable_irq(dev->irq);
2202 }
2203 #endif
2204
2205 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2206 {
2207 struct rtl8139_private *tp = netdev_priv(dev);
2208 void __iomem *ioaddr = tp->mmio_addr;
2209 struct sockaddr *addr = p;
2210
2211 if (!is_valid_ether_addr(addr->sa_data))
2212 return -EADDRNOTAVAIL;
2213
2214 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2215
2216 spin_lock_irq(&tp->lock);
2217
2218 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2219 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2220 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2221 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2222
2223 spin_unlock_irq(&tp->lock);
2224
2225 return 0;
2226 }
2227
2228 static int rtl8139_close (struct net_device *dev)
2229 {
2230 struct rtl8139_private *tp = netdev_priv(dev);
2231 void __iomem *ioaddr = tp->mmio_addr;
2232 unsigned long flags;
2233
2234 netif_stop_queue(dev);
2235 napi_disable(&tp->napi);
2236
2237 if (netif_msg_ifdown(tp))
2238 pr_debug("%s: Shutting down ethercard, status was 0x%4.4x.\n",
2239 dev->name, RTL_R16 (IntrStatus));
2240
2241 spin_lock_irqsave (&tp->lock, flags);
2242
2243 /* Stop the chip's Tx and Rx DMA processes. */
2244 RTL_W8 (ChipCmd, 0);
2245
2246 /* Disable interrupts by clearing the interrupt mask. */
2247 RTL_W16 (IntrMask, 0);
2248
2249 /* Update the error counts. */
2250 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2251 RTL_W32 (RxMissed, 0);
2252
2253 spin_unlock_irqrestore (&tp->lock, flags);
2254
2255 free_irq (dev->irq, dev);
2256
2257 rtl8139_tx_clear (tp);
2258
2259 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2260 tp->rx_ring, tp->rx_ring_dma);
2261 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2262 tp->tx_bufs, tp->tx_bufs_dma);
2263 tp->rx_ring = NULL;
2264 tp->tx_bufs = NULL;
2265
2266 /* Green! Put the chip in low-power mode. */
2267 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2268
2269 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2270 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2271
2272 return 0;
2273 }
2274
2275
2276 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2277 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2278 other threads or interrupts aren't messing with the 8139. */
2279 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2280 {
2281 struct rtl8139_private *tp = netdev_priv(dev);
2282 void __iomem *ioaddr = tp->mmio_addr;
2283
2284 spin_lock_irq(&tp->lock);
2285 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2286 u8 cfg3 = RTL_R8 (Config3);
2287 u8 cfg5 = RTL_R8 (Config5);
2288
2289 wol->supported = WAKE_PHY | WAKE_MAGIC
2290 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2291
2292 wol->wolopts = 0;
2293 if (cfg3 & Cfg3_LinkUp)
2294 wol->wolopts |= WAKE_PHY;
2295 if (cfg3 & Cfg3_Magic)
2296 wol->wolopts |= WAKE_MAGIC;
2297 /* (KON)FIXME: See how netdev_set_wol() handles the
2298 following constants. */
2299 if (cfg5 & Cfg5_UWF)
2300 wol->wolopts |= WAKE_UCAST;
2301 if (cfg5 & Cfg5_MWF)
2302 wol->wolopts |= WAKE_MCAST;
2303 if (cfg5 & Cfg5_BWF)
2304 wol->wolopts |= WAKE_BCAST;
2305 }
2306 spin_unlock_irq(&tp->lock);
2307 }
2308
2309
2310 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2311 that wol points to kernel memory and other threads or interrupts
2312 aren't messing with the 8139. */
2313 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2314 {
2315 struct rtl8139_private *tp = netdev_priv(dev);
2316 void __iomem *ioaddr = tp->mmio_addr;
2317 u32 support;
2318 u8 cfg3, cfg5;
2319
2320 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2321 ? (WAKE_PHY | WAKE_MAGIC
2322 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2323 : 0);
2324 if (wol->wolopts & ~support)
2325 return -EINVAL;
2326
2327 spin_lock_irq(&tp->lock);
2328 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2329 if (wol->wolopts & WAKE_PHY)
2330 cfg3 |= Cfg3_LinkUp;
2331 if (wol->wolopts & WAKE_MAGIC)
2332 cfg3 |= Cfg3_Magic;
2333 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2334 RTL_W8 (Config3, cfg3);
2335 RTL_W8 (Cfg9346, Cfg9346_Lock);
2336
2337 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2338 /* (KON)FIXME: These are untested. We may have to set the
2339 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2340 documentation. */
2341 if (wol->wolopts & WAKE_UCAST)
2342 cfg5 |= Cfg5_UWF;
2343 if (wol->wolopts & WAKE_MCAST)
2344 cfg5 |= Cfg5_MWF;
2345 if (wol->wolopts & WAKE_BCAST)
2346 cfg5 |= Cfg5_BWF;
2347 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2348 spin_unlock_irq(&tp->lock);
2349
2350 return 0;
2351 }
2352
2353 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2354 {
2355 struct rtl8139_private *tp = netdev_priv(dev);
2356 strcpy(info->driver, DRV_NAME);
2357 strcpy(info->version, DRV_VERSION);
2358 strcpy(info->bus_info, pci_name(tp->pci_dev));
2359 info->regdump_len = tp->regs_len;
2360 }
2361
2362 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2363 {
2364 struct rtl8139_private *tp = netdev_priv(dev);
2365 spin_lock_irq(&tp->lock);
2366 mii_ethtool_gset(&tp->mii, cmd);
2367 spin_unlock_irq(&tp->lock);
2368 return 0;
2369 }
2370
2371 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2372 {
2373 struct rtl8139_private *tp = netdev_priv(dev);
2374 int rc;
2375 spin_lock_irq(&tp->lock);
2376 rc = mii_ethtool_sset(&tp->mii, cmd);
2377 spin_unlock_irq(&tp->lock);
2378 return rc;
2379 }
2380
2381 static int rtl8139_nway_reset(struct net_device *dev)
2382 {
2383 struct rtl8139_private *tp = netdev_priv(dev);
2384 return mii_nway_restart(&tp->mii);
2385 }
2386
2387 static u32 rtl8139_get_link(struct net_device *dev)
2388 {
2389 struct rtl8139_private *tp = netdev_priv(dev);
2390 return mii_link_ok(&tp->mii);
2391 }
2392
2393 static u32 rtl8139_get_msglevel(struct net_device *dev)
2394 {
2395 struct rtl8139_private *tp = netdev_priv(dev);
2396 return tp->msg_enable;
2397 }
2398
2399 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2400 {
2401 struct rtl8139_private *tp = netdev_priv(dev);
2402 tp->msg_enable = datum;
2403 }
2404
2405 static int rtl8139_get_regs_len(struct net_device *dev)
2406 {
2407 struct rtl8139_private *tp;
2408 /* TODO: we are too slack to do reg dumping for pio, for now */
2409 if (use_io)
2410 return 0;
2411 tp = netdev_priv(dev);
2412 return tp->regs_len;
2413 }
2414
2415 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2416 {
2417 struct rtl8139_private *tp;
2418
2419 /* TODO: we are too slack to do reg dumping for pio, for now */
2420 if (use_io)
2421 return;
2422 tp = netdev_priv(dev);
2423
2424 regs->version = RTL_REGS_VER;
2425
2426 spin_lock_irq(&tp->lock);
2427 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2428 spin_unlock_irq(&tp->lock);
2429 }
2430
2431 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2432 {
2433 switch (sset) {
2434 case ETH_SS_STATS:
2435 return RTL_NUM_STATS;
2436 default:
2437 return -EOPNOTSUPP;
2438 }
2439 }
2440
2441 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2442 {
2443 struct rtl8139_private *tp = netdev_priv(dev);
2444
2445 data[0] = tp->xstats.early_rx;
2446 data[1] = tp->xstats.tx_buf_mapped;
2447 data[2] = tp->xstats.tx_timeouts;
2448 data[3] = tp->xstats.rx_lost_in_ring;
2449 }
2450
2451 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2452 {
2453 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2454 }
2455
2456 static const struct ethtool_ops rtl8139_ethtool_ops = {
2457 .get_drvinfo = rtl8139_get_drvinfo,
2458 .get_settings = rtl8139_get_settings,
2459 .set_settings = rtl8139_set_settings,
2460 .get_regs_len = rtl8139_get_regs_len,
2461 .get_regs = rtl8139_get_regs,
2462 .nway_reset = rtl8139_nway_reset,
2463 .get_link = rtl8139_get_link,
2464 .get_msglevel = rtl8139_get_msglevel,
2465 .set_msglevel = rtl8139_set_msglevel,
2466 .get_wol = rtl8139_get_wol,
2467 .set_wol = rtl8139_set_wol,
2468 .get_strings = rtl8139_get_strings,
2469 .get_sset_count = rtl8139_get_sset_count,
2470 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2471 };
2472
2473 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2474 {
2475 struct rtl8139_private *tp = netdev_priv(dev);
2476 int rc;
2477
2478 if (!netif_running(dev))
2479 return -EINVAL;
2480
2481 spin_lock_irq(&tp->lock);
2482 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2483 spin_unlock_irq(&tp->lock);
2484
2485 return rc;
2486 }
2487
2488
2489 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2490 {
2491 struct rtl8139_private *tp = netdev_priv(dev);
2492 void __iomem *ioaddr = tp->mmio_addr;
2493 unsigned long flags;
2494
2495 if (netif_running(dev)) {
2496 spin_lock_irqsave (&tp->lock, flags);
2497 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2498 RTL_W32 (RxMissed, 0);
2499 spin_unlock_irqrestore (&tp->lock, flags);
2500 }
2501
2502 return &dev->stats;
2503 }
2504
2505 /* Set or clear the multicast filter for this adaptor.
2506 This routine is not state sensitive and need not be SMP locked. */
2507
2508 static void __set_rx_mode (struct net_device *dev)
2509 {
2510 struct rtl8139_private *tp = netdev_priv(dev);
2511 void __iomem *ioaddr = tp->mmio_addr;
2512 u32 mc_filter[2]; /* Multicast hash filter */
2513 int i, rx_mode;
2514 u32 tmp;
2515
2516 pr_debug("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2517 dev->name, dev->flags, RTL_R32 (RxConfig));
2518
2519 /* Note: do not reorder, GCC is clever about common statements. */
2520 if (dev->flags & IFF_PROMISC) {
2521 rx_mode =
2522 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2523 AcceptAllPhys;
2524 mc_filter[1] = mc_filter[0] = 0xffffffff;
2525 } else if ((dev->mc_count > multicast_filter_limit)
2526 || (dev->flags & IFF_ALLMULTI)) {
2527 /* Too many to filter perfectly -- accept all multicasts. */
2528 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2529 mc_filter[1] = mc_filter[0] = 0xffffffff;
2530 } else {
2531 struct dev_mc_list *mclist;
2532 rx_mode = AcceptBroadcast | AcceptMyPhys;
2533 mc_filter[1] = mc_filter[0] = 0;
2534 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2535 i++, mclist = mclist->next) {
2536 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2537
2538 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2539 rx_mode |= AcceptMulticast;
2540 }
2541 }
2542
2543 /* We can safely update without stopping the chip. */
2544 tmp = rtl8139_rx_config | rx_mode;
2545 if (tp->rx_config != tmp) {
2546 RTL_W32_F (RxConfig, tmp);
2547 tp->rx_config = tmp;
2548 }
2549 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2550 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2551 }
2552
2553 static void rtl8139_set_rx_mode (struct net_device *dev)
2554 {
2555 unsigned long flags;
2556 struct rtl8139_private *tp = netdev_priv(dev);
2557
2558 spin_lock_irqsave (&tp->lock, flags);
2559 __set_rx_mode(dev);
2560 spin_unlock_irqrestore (&tp->lock, flags);
2561 }
2562
2563 #ifdef CONFIG_PM
2564
2565 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2566 {
2567 struct net_device *dev = pci_get_drvdata (pdev);
2568 struct rtl8139_private *tp = netdev_priv(dev);
2569 void __iomem *ioaddr = tp->mmio_addr;
2570 unsigned long flags;
2571
2572 pci_save_state (pdev);
2573
2574 if (!netif_running (dev))
2575 return 0;
2576
2577 netif_device_detach (dev);
2578
2579 spin_lock_irqsave (&tp->lock, flags);
2580
2581 /* Disable interrupts, stop Tx and Rx. */
2582 RTL_W16 (IntrMask, 0);
2583 RTL_W8 (ChipCmd, 0);
2584
2585 /* Update the error counts. */
2586 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2587 RTL_W32 (RxMissed, 0);
2588
2589 spin_unlock_irqrestore (&tp->lock, flags);
2590
2591 pci_set_power_state (pdev, PCI_D3hot);
2592
2593 return 0;
2594 }
2595
2596
2597 static int rtl8139_resume (struct pci_dev *pdev)
2598 {
2599 struct net_device *dev = pci_get_drvdata (pdev);
2600
2601 pci_restore_state (pdev);
2602 if (!netif_running (dev))
2603 return 0;
2604 pci_set_power_state (pdev, PCI_D0);
2605 rtl8139_init_ring (dev);
2606 rtl8139_hw_start (dev);
2607 netif_device_attach (dev);
2608 return 0;
2609 }
2610
2611 #endif /* CONFIG_PM */
2612
2613
2614 static struct pci_driver rtl8139_pci_driver = {
2615 .name = DRV_NAME,
2616 .id_table = rtl8139_pci_tbl,
2617 .probe = rtl8139_init_one,
2618 .remove = __devexit_p(rtl8139_remove_one),
2619 #ifdef CONFIG_PM
2620 .suspend = rtl8139_suspend,
2621 .resume = rtl8139_resume,
2622 #endif /* CONFIG_PM */
2623 };
2624
2625
2626 static int __init rtl8139_init_module (void)
2627 {
2628 /* when we're a module, we always print a version message,
2629 * even if no 8139 board is found.
2630 */
2631 #ifdef MODULE
2632 pr_info(RTL8139_DRIVER_NAME "\n");
2633 #endif
2634
2635 return pci_register_driver(&rtl8139_pci_driver);
2636 }
2637
2638
2639 static void __exit rtl8139_cleanup_module (void)
2640 {
2641 pci_unregister_driver (&rtl8139_pci_driver);
2642 }
2643
2644
2645 module_init(rtl8139_init_module);
2646 module_exit(rtl8139_cleanup_module);
Linux for Ginger Game Console