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OMAP3 PM: CPUFreq driver for OMAP3
[linux-ginger.git] / drivers / net / s2io.c
blobddccf5fa56b63b998d2344e6e67cf6e7fd4977e4
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4 *
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
56
57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
59 #include <linux/module.h>
60 #include <linux/types.h>
61 #include <linux/errno.h>
62 #include <linux/ioport.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/kernel.h>
66 #include <linux/netdevice.h>
67 #include <linux/etherdevice.h>
68 #include <linux/mdio.h>
69 #include <linux/skbuff.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/stddef.h>
73 #include <linux/ioctl.h>
74 #include <linux/timex.h>
75 #include <linux/ethtool.h>
76 #include <linux/workqueue.h>
77 #include <linux/if_vlan.h>
78 #include <linux/ip.h>
79 #include <linux/tcp.h>
80 #include <linux/uaccess.h>
81 #include <linux/io.h>
82 #include <net/tcp.h>
83
84 #include <asm/system.h>
85 #include <asm/div64.h>
86 #include <asm/irq.h>
87
88 /* local include */
89 #include "s2io.h"
90 #include "s2io-regs.h"
91
92 #define DRV_VERSION "2.0.26.25"
93
94 /* S2io Driver name & version. */
95 static char s2io_driver_name[] = "Neterion";
96 static char s2io_driver_version[] = DRV_VERSION;
97
98 static int rxd_size[2] = {32, 48};
99 static int rxd_count[2] = {127, 85};
100
101 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
102 {
103 int ret;
104
105 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
106 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
107
108 return ret;
109 }
110
111 /*
112 * Cards with following subsystem_id have a link state indication
113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114 * macro below identifies these cards given the subsystem_id.
115 */
116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
117 (dev_type == XFRAME_I_DEVICE) ? \
118 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
119 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
120
121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
123
124 static inline int is_s2io_card_up(const struct s2io_nic *sp)
125 {
126 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127 }
128
129 /* Ethtool related variables and Macros. */
130 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
131 "Register test\t(offline)",
132 "Eeprom test\t(offline)",
133 "Link test\t(online)",
134 "RLDRAM test\t(offline)",
135 "BIST Test\t(offline)"
136 };
137
138 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
139 {"tmac_frms"},
140 {"tmac_data_octets"},
141 {"tmac_drop_frms"},
142 {"tmac_mcst_frms"},
143 {"tmac_bcst_frms"},
144 {"tmac_pause_ctrl_frms"},
145 {"tmac_ttl_octets"},
146 {"tmac_ucst_frms"},
147 {"tmac_nucst_frms"},
148 {"tmac_any_err_frms"},
149 {"tmac_ttl_less_fb_octets"},
150 {"tmac_vld_ip_octets"},
151 {"tmac_vld_ip"},
152 {"tmac_drop_ip"},
153 {"tmac_icmp"},
154 {"tmac_rst_tcp"},
155 {"tmac_tcp"},
156 {"tmac_udp"},
157 {"rmac_vld_frms"},
158 {"rmac_data_octets"},
159 {"rmac_fcs_err_frms"},
160 {"rmac_drop_frms"},
161 {"rmac_vld_mcst_frms"},
162 {"rmac_vld_bcst_frms"},
163 {"rmac_in_rng_len_err_frms"},
164 {"rmac_out_rng_len_err_frms"},
165 {"rmac_long_frms"},
166 {"rmac_pause_ctrl_frms"},
167 {"rmac_unsup_ctrl_frms"},
168 {"rmac_ttl_octets"},
169 {"rmac_accepted_ucst_frms"},
170 {"rmac_accepted_nucst_frms"},
171 {"rmac_discarded_frms"},
172 {"rmac_drop_events"},
173 {"rmac_ttl_less_fb_octets"},
174 {"rmac_ttl_frms"},
175 {"rmac_usized_frms"},
176 {"rmac_osized_frms"},
177 {"rmac_frag_frms"},
178 {"rmac_jabber_frms"},
179 {"rmac_ttl_64_frms"},
180 {"rmac_ttl_65_127_frms"},
181 {"rmac_ttl_128_255_frms"},
182 {"rmac_ttl_256_511_frms"},
183 {"rmac_ttl_512_1023_frms"},
184 {"rmac_ttl_1024_1518_frms"},
185 {"rmac_ip"},
186 {"rmac_ip_octets"},
187 {"rmac_hdr_err_ip"},
188 {"rmac_drop_ip"},
189 {"rmac_icmp"},
190 {"rmac_tcp"},
191 {"rmac_udp"},
192 {"rmac_err_drp_udp"},
193 {"rmac_xgmii_err_sym"},
194 {"rmac_frms_q0"},
195 {"rmac_frms_q1"},
196 {"rmac_frms_q2"},
197 {"rmac_frms_q3"},
198 {"rmac_frms_q4"},
199 {"rmac_frms_q5"},
200 {"rmac_frms_q6"},
201 {"rmac_frms_q7"},
202 {"rmac_full_q0"},
203 {"rmac_full_q1"},
204 {"rmac_full_q2"},
205 {"rmac_full_q3"},
206 {"rmac_full_q4"},
207 {"rmac_full_q5"},
208 {"rmac_full_q6"},
209 {"rmac_full_q7"},
210 {"rmac_pause_cnt"},
211 {"rmac_xgmii_data_err_cnt"},
212 {"rmac_xgmii_ctrl_err_cnt"},
213 {"rmac_accepted_ip"},
214 {"rmac_err_tcp"},
215 {"rd_req_cnt"},
216 {"new_rd_req_cnt"},
217 {"new_rd_req_rtry_cnt"},
218 {"rd_rtry_cnt"},
219 {"wr_rtry_rd_ack_cnt"},
220 {"wr_req_cnt"},
221 {"new_wr_req_cnt"},
222 {"new_wr_req_rtry_cnt"},
223 {"wr_rtry_cnt"},
224 {"wr_disc_cnt"},
225 {"rd_rtry_wr_ack_cnt"},
226 {"txp_wr_cnt"},
227 {"txd_rd_cnt"},
228 {"txd_wr_cnt"},
229 {"rxd_rd_cnt"},
230 {"rxd_wr_cnt"},
231 {"txf_rd_cnt"},
232 {"rxf_wr_cnt"}
233 };
234
235 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
236 {"rmac_ttl_1519_4095_frms"},
237 {"rmac_ttl_4096_8191_frms"},
238 {"rmac_ttl_8192_max_frms"},
239 {"rmac_ttl_gt_max_frms"},
240 {"rmac_osized_alt_frms"},
241 {"rmac_jabber_alt_frms"},
242 {"rmac_gt_max_alt_frms"},
243 {"rmac_vlan_frms"},
244 {"rmac_len_discard"},
245 {"rmac_fcs_discard"},
246 {"rmac_pf_discard"},
247 {"rmac_da_discard"},
248 {"rmac_red_discard"},
249 {"rmac_rts_discard"},
250 {"rmac_ingm_full_discard"},
251 {"link_fault_cnt"}
252 };
253
254 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
255 {"\n DRIVER STATISTICS"},
256 {"single_bit_ecc_errs"},
257 {"double_bit_ecc_errs"},
258 {"parity_err_cnt"},
259 {"serious_err_cnt"},
260 {"soft_reset_cnt"},
261 {"fifo_full_cnt"},
262 {"ring_0_full_cnt"},
263 {"ring_1_full_cnt"},
264 {"ring_2_full_cnt"},
265 {"ring_3_full_cnt"},
266 {"ring_4_full_cnt"},
267 {"ring_5_full_cnt"},
268 {"ring_6_full_cnt"},
269 {"ring_7_full_cnt"},
270 {"alarm_transceiver_temp_high"},
271 {"alarm_transceiver_temp_low"},
272 {"alarm_laser_bias_current_high"},
273 {"alarm_laser_bias_current_low"},
274 {"alarm_laser_output_power_high"},
275 {"alarm_laser_output_power_low"},
276 {"warn_transceiver_temp_high"},
277 {"warn_transceiver_temp_low"},
278 {"warn_laser_bias_current_high"},
279 {"warn_laser_bias_current_low"},
280 {"warn_laser_output_power_high"},
281 {"warn_laser_output_power_low"},
282 {"lro_aggregated_pkts"},
283 {"lro_flush_both_count"},
284 {"lro_out_of_sequence_pkts"},
285 {"lro_flush_due_to_max_pkts"},
286 {"lro_avg_aggr_pkts"},
287 {"mem_alloc_fail_cnt"},
288 {"pci_map_fail_cnt"},
289 {"watchdog_timer_cnt"},
290 {"mem_allocated"},
291 {"mem_freed"},
292 {"link_up_cnt"},
293 {"link_down_cnt"},
294 {"link_up_time"},
295 {"link_down_time"},
296 {"tx_tcode_buf_abort_cnt"},
297 {"tx_tcode_desc_abort_cnt"},
298 {"tx_tcode_parity_err_cnt"},
299 {"tx_tcode_link_loss_cnt"},
300 {"tx_tcode_list_proc_err_cnt"},
301 {"rx_tcode_parity_err_cnt"},
302 {"rx_tcode_abort_cnt"},
303 {"rx_tcode_parity_abort_cnt"},
304 {"rx_tcode_rda_fail_cnt"},
305 {"rx_tcode_unkn_prot_cnt"},
306 {"rx_tcode_fcs_err_cnt"},
307 {"rx_tcode_buf_size_err_cnt"},
308 {"rx_tcode_rxd_corrupt_cnt"},
309 {"rx_tcode_unkn_err_cnt"},
310 {"tda_err_cnt"},
311 {"pfc_err_cnt"},
312 {"pcc_err_cnt"},
313 {"tti_err_cnt"},
314 {"tpa_err_cnt"},
315 {"sm_err_cnt"},
316 {"lso_err_cnt"},
317 {"mac_tmac_err_cnt"},
318 {"mac_rmac_err_cnt"},
319 {"xgxs_txgxs_err_cnt"},
320 {"xgxs_rxgxs_err_cnt"},
321 {"rc_err_cnt"},
322 {"prc_pcix_err_cnt"},
323 {"rpa_err_cnt"},
324 {"rda_err_cnt"},
325 {"rti_err_cnt"},
326 {"mc_err_cnt"}
327 };
328
329 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
330 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
331 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
332
333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
335
336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
338
339 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
340 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
341
342 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
343 init_timer(&timer); \
344 timer.function = handle; \
345 timer.data = (unsigned long)arg; \
346 mod_timer(&timer, (jiffies + exp)) \
347
348 /* copy mac addr to def_mac_addr array */
349 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350 {
351 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357 }
358
359 /* Add the vlan */
360 static void s2io_vlan_rx_register(struct net_device *dev,
361 struct vlan_group *grp)
362 {
363 int i;
364 struct s2io_nic *nic = netdev_priv(dev);
365 unsigned long flags[MAX_TX_FIFOS];
366 struct config_param *config = &nic->config;
367 struct mac_info *mac_control = &nic->mac_control;
368
369 for (i = 0; i < config->tx_fifo_num; i++) {
370 struct fifo_info *fifo = &mac_control->fifos[i];
371
372 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
373 }
374
375 nic->vlgrp = grp;
376
377 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
378 struct fifo_info *fifo = &mac_control->fifos[i];
379
380 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
381 }
382 }
383
384 /* Unregister the vlan */
385 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
386 {
387 int i;
388 struct s2io_nic *nic = netdev_priv(dev);
389 unsigned long flags[MAX_TX_FIFOS];
390 struct config_param *config = &nic->config;
391 struct mac_info *mac_control = &nic->mac_control;
392
393 for (i = 0; i < config->tx_fifo_num; i++) {
394 struct fifo_info *fifo = &mac_control->fifos[i];
395
396 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
397 }
398
399 if (nic->vlgrp)
400 vlan_group_set_device(nic->vlgrp, vid, NULL);
401
402 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
403 struct fifo_info *fifo = &mac_control->fifos[i];
404
405 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
406 }
407 }
408
409 /*
410 * Constants to be programmed into the Xena's registers, to configure
411 * the XAUI.
412 */
413
414 #define END_SIGN 0x0
415 static const u64 herc_act_dtx_cfg[] = {
416 /* Set address */
417 0x8000051536750000ULL, 0x80000515367500E0ULL,
418 /* Write data */
419 0x8000051536750004ULL, 0x80000515367500E4ULL,
420 /* Set address */
421 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
422 /* Write data */
423 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
424 /* Set address */
425 0x801205150D440000ULL, 0x801205150D4400E0ULL,
426 /* Write data */
427 0x801205150D440004ULL, 0x801205150D4400E4ULL,
428 /* Set address */
429 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
430 /* Write data */
431 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
432 /* Done */
433 END_SIGN
434 };
435
436 static const u64 xena_dtx_cfg[] = {
437 /* Set address */
438 0x8000051500000000ULL, 0x80000515000000E0ULL,
439 /* Write data */
440 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
441 /* Set address */
442 0x8001051500000000ULL, 0x80010515000000E0ULL,
443 /* Write data */
444 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
445 /* Set address */
446 0x8002051500000000ULL, 0x80020515000000E0ULL,
447 /* Write data */
448 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
449 END_SIGN
450 };
451
452 /*
453 * Constants for Fixing the MacAddress problem seen mostly on
454 * Alpha machines.
455 */
456 static const u64 fix_mac[] = {
457 0x0060000000000000ULL, 0x0060600000000000ULL,
458 0x0040600000000000ULL, 0x0000600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0000600000000000ULL,
470 0x0040600000000000ULL, 0x0060600000000000ULL,
471 END_SIGN
472 };
473
474 MODULE_LICENSE("GPL");
475 MODULE_VERSION(DRV_VERSION);
476
477
478 /* Module Loadable parameters. */
479 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
480 S2IO_PARM_INT(rx_ring_num, 1);
481 S2IO_PARM_INT(multiq, 0);
482 S2IO_PARM_INT(rx_ring_mode, 1);
483 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
484 S2IO_PARM_INT(rmac_pause_time, 0x100);
485 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
486 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
487 S2IO_PARM_INT(shared_splits, 0);
488 S2IO_PARM_INT(tmac_util_period, 5);
489 S2IO_PARM_INT(rmac_util_period, 5);
490 S2IO_PARM_INT(l3l4hdr_size, 128);
491 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
492 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
493 /* Frequency of Rx desc syncs expressed as power of 2 */
494 S2IO_PARM_INT(rxsync_frequency, 3);
495 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
496 S2IO_PARM_INT(intr_type, 2);
497 /* Large receive offload feature */
498 static unsigned int lro_enable;
499 module_param_named(lro, lro_enable, uint, 0);
500
501 /* Max pkts to be aggregated by LRO at one time. If not specified,
502 * aggregation happens until we hit max IP pkt size(64K)
503 */
504 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
505 S2IO_PARM_INT(indicate_max_pkts, 0);
506
507 S2IO_PARM_INT(napi, 1);
508 S2IO_PARM_INT(ufo, 0);
509 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
510
511 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
512 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
513 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
514 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
515 static unsigned int rts_frm_len[MAX_RX_RINGS] =
516 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
517
518 module_param_array(tx_fifo_len, uint, NULL, 0);
519 module_param_array(rx_ring_sz, uint, NULL, 0);
520 module_param_array(rts_frm_len, uint, NULL, 0);
521
522 /*
523 * S2IO device table.
524 * This table lists all the devices that this driver supports.
525 */
526 static struct pci_device_id s2io_tbl[] __devinitdata = {
527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
532 PCI_ANY_ID, PCI_ANY_ID},
533 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
534 PCI_ANY_ID, PCI_ANY_ID},
535 {0,}
536 };
537
538 MODULE_DEVICE_TABLE(pci, s2io_tbl);
539
540 static struct pci_error_handlers s2io_err_handler = {
541 .error_detected = s2io_io_error_detected,
542 .slot_reset = s2io_io_slot_reset,
543 .resume = s2io_io_resume,
544 };
545
546 static struct pci_driver s2io_driver = {
547 .name = "S2IO",
548 .id_table = s2io_tbl,
549 .probe = s2io_init_nic,
550 .remove = __devexit_p(s2io_rem_nic),
551 .err_handler = &s2io_err_handler,
552 };
553
554 /* A simplifier macro used both by init and free shared_mem Fns(). */
555 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
556
557 /* netqueue manipulation helper functions */
558 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
559 {
560 if (!sp->config.multiq) {
561 int i;
562
563 for (i = 0; i < sp->config.tx_fifo_num; i++)
564 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
565 }
566 netif_tx_stop_all_queues(sp->dev);
567 }
568
569 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
570 {
571 if (!sp->config.multiq)
572 sp->mac_control.fifos[fifo_no].queue_state =
573 FIFO_QUEUE_STOP;
574
575 netif_tx_stop_all_queues(sp->dev);
576 }
577
578 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
579 {
580 if (!sp->config.multiq) {
581 int i;
582
583 for (i = 0; i < sp->config.tx_fifo_num; i++)
584 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
585 }
586 netif_tx_start_all_queues(sp->dev);
587 }
588
589 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
590 {
591 if (!sp->config.multiq)
592 sp->mac_control.fifos[fifo_no].queue_state =
593 FIFO_QUEUE_START;
594
595 netif_tx_start_all_queues(sp->dev);
596 }
597
598 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
599 {
600 if (!sp->config.multiq) {
601 int i;
602
603 for (i = 0; i < sp->config.tx_fifo_num; i++)
604 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
605 }
606 netif_tx_wake_all_queues(sp->dev);
607 }
608
609 static inline void s2io_wake_tx_queue(
610 struct fifo_info *fifo, int cnt, u8 multiq)
611 {
612
613 if (multiq) {
614 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
615 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
616 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
617 if (netif_queue_stopped(fifo->dev)) {
618 fifo->queue_state = FIFO_QUEUE_START;
619 netif_wake_queue(fifo->dev);
620 }
621 }
622 }
623
624 /**
625 * init_shared_mem - Allocation and Initialization of Memory
626 * @nic: Device private variable.
627 * Description: The function allocates all the memory areas shared
628 * between the NIC and the driver. This includes Tx descriptors,
629 * Rx descriptors and the statistics block.
630 */
631
632 static int init_shared_mem(struct s2io_nic *nic)
633 {
634 u32 size;
635 void *tmp_v_addr, *tmp_v_addr_next;
636 dma_addr_t tmp_p_addr, tmp_p_addr_next;
637 struct RxD_block *pre_rxd_blk = NULL;
638 int i, j, blk_cnt;
639 int lst_size, lst_per_page;
640 struct net_device *dev = nic->dev;
641 unsigned long tmp;
642 struct buffAdd *ba;
643 struct config_param *config = &nic->config;
644 struct mac_info *mac_control = &nic->mac_control;
645 unsigned long long mem_allocated = 0;
646
647 /* Allocation and initialization of TXDLs in FIFOs */
648 size = 0;
649 for (i = 0; i < config->tx_fifo_num; i++) {
650 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
651
652 size += tx_cfg->fifo_len;
653 }
654 if (size > MAX_AVAILABLE_TXDS) {
655 DBG_PRINT(ERR_DBG,
656 "Too many TxDs requested: %d, max supported: %d\n",
657 size, MAX_AVAILABLE_TXDS);
658 return -EINVAL;
659 }
660
661 size = 0;
662 for (i = 0; i < config->tx_fifo_num; i++) {
663 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
664
665 size = tx_cfg->fifo_len;
666 /*
667 * Legal values are from 2 to 8192
668 */
669 if (size < 2) {
670 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
671 "Valid lengths are 2 through 8192\n",
672 i, size);
673 return -EINVAL;
674 }
675 }
676
677 lst_size = (sizeof(struct TxD) * config->max_txds);
678 lst_per_page = PAGE_SIZE / lst_size;
679
680 for (i = 0; i < config->tx_fifo_num; i++) {
681 struct fifo_info *fifo = &mac_control->fifos[i];
682 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
683 int fifo_len = tx_cfg->fifo_len;
684 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
685
686 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
687 if (!fifo->list_info) {
688 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
689 return -ENOMEM;
690 }
691 mem_allocated += list_holder_size;
692 }
693 for (i = 0; i < config->tx_fifo_num; i++) {
694 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
695 lst_per_page);
696 struct fifo_info *fifo = &mac_control->fifos[i];
697 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
698
699 fifo->tx_curr_put_info.offset = 0;
700 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
701 fifo->tx_curr_get_info.offset = 0;
702 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
703 fifo->fifo_no = i;
704 fifo->nic = nic;
705 fifo->max_txds = MAX_SKB_FRAGS + 2;
706 fifo->dev = dev;
707
708 for (j = 0; j < page_num; j++) {
709 int k = 0;
710 dma_addr_t tmp_p;
711 void *tmp_v;
712 tmp_v = pci_alloc_consistent(nic->pdev,
713 PAGE_SIZE, &tmp_p);
714 if (!tmp_v) {
715 DBG_PRINT(INFO_DBG,
716 "pci_alloc_consistent failed for TxDL\n");
717 return -ENOMEM;
718 }
719 /* If we got a zero DMA address(can happen on
720 * certain platforms like PPC), reallocate.
721 * Store virtual address of page we don't want,
722 * to be freed later.
723 */
724 if (!tmp_p) {
725 mac_control->zerodma_virt_addr = tmp_v;
726 DBG_PRINT(INIT_DBG,
727 "%s: Zero DMA address for TxDL. "
728 "Virtual address %p\n",
729 dev->name, tmp_v);
730 tmp_v = pci_alloc_consistent(nic->pdev,
731 PAGE_SIZE, &tmp_p);
732 if (!tmp_v) {
733 DBG_PRINT(INFO_DBG,
734 "pci_alloc_consistent failed for TxDL\n");
735 return -ENOMEM;
736 }
737 mem_allocated += PAGE_SIZE;
738 }
739 while (k < lst_per_page) {
740 int l = (j * lst_per_page) + k;
741 if (l == tx_cfg->fifo_len)
742 break;
743 fifo->list_info[l].list_virt_addr =
744 tmp_v + (k * lst_size);
745 fifo->list_info[l].list_phy_addr =
746 tmp_p + (k * lst_size);
747 k++;
748 }
749 }
750 }
751
752 for (i = 0; i < config->tx_fifo_num; i++) {
753 struct fifo_info *fifo = &mac_control->fifos[i];
754 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
755
756 size = tx_cfg->fifo_len;
757 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
758 if (!fifo->ufo_in_band_v)
759 return -ENOMEM;
760 mem_allocated += (size * sizeof(u64));
761 }
762
763 /* Allocation and initialization of RXDs in Rings */
764 size = 0;
765 for (i = 0; i < config->rx_ring_num; i++) {
766 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
767 struct ring_info *ring = &mac_control->rings[i];
768
769 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
770 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
771 "multiple of RxDs per Block\n",
772 dev->name, i);
773 return FAILURE;
774 }
775 size += rx_cfg->num_rxd;
776 ring->block_count = rx_cfg->num_rxd /
777 (rxd_count[nic->rxd_mode] + 1);
778 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
779 }
780 if (nic->rxd_mode == RXD_MODE_1)
781 size = (size * (sizeof(struct RxD1)));
782 else
783 size = (size * (sizeof(struct RxD3)));
784
785 for (i = 0; i < config->rx_ring_num; i++) {
786 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
787 struct ring_info *ring = &mac_control->rings[i];
788
789 ring->rx_curr_get_info.block_index = 0;
790 ring->rx_curr_get_info.offset = 0;
791 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
792 ring->rx_curr_put_info.block_index = 0;
793 ring->rx_curr_put_info.offset = 0;
794 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
795 ring->nic = nic;
796 ring->ring_no = i;
797 ring->lro = lro_enable;
798
799 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
800 /* Allocating all the Rx blocks */
801 for (j = 0; j < blk_cnt; j++) {
802 struct rx_block_info *rx_blocks;
803 int l;
804
805 rx_blocks = &ring->rx_blocks[j];
806 size = SIZE_OF_BLOCK; /* size is always page size */
807 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
808 &tmp_p_addr);
809 if (tmp_v_addr == NULL) {
810 /*
811 * In case of failure, free_shared_mem()
812 * is called, which should free any
813 * memory that was alloced till the
814 * failure happened.
815 */
816 rx_blocks->block_virt_addr = tmp_v_addr;
817 return -ENOMEM;
818 }
819 mem_allocated += size;
820 memset(tmp_v_addr, 0, size);
821
822 size = sizeof(struct rxd_info) *
823 rxd_count[nic->rxd_mode];
824 rx_blocks->block_virt_addr = tmp_v_addr;
825 rx_blocks->block_dma_addr = tmp_p_addr;
826 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
827 if (!rx_blocks->rxds)
828 return -ENOMEM;
829 mem_allocated += size;
830 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
831 rx_blocks->rxds[l].virt_addr =
832 rx_blocks->block_virt_addr +
833 (rxd_size[nic->rxd_mode] * l);
834 rx_blocks->rxds[l].dma_addr =
835 rx_blocks->block_dma_addr +
836 (rxd_size[nic->rxd_mode] * l);
837 }
838 }
839 /* Interlinking all Rx Blocks */
840 for (j = 0; j < blk_cnt; j++) {
841 int next = (j + 1) % blk_cnt;
842 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
843 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
844 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
845 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
846
847 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
848 pre_rxd_blk->reserved_2_pNext_RxD_block =
849 (unsigned long)tmp_v_addr_next;
850 pre_rxd_blk->pNext_RxD_Blk_physical =
851 (u64)tmp_p_addr_next;
852 }
853 }
854 if (nic->rxd_mode == RXD_MODE_3B) {
855 /*
856 * Allocation of Storages for buffer addresses in 2BUFF mode
857 * and the buffers as well.
858 */
859 for (i = 0; i < config->rx_ring_num; i++) {
860 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
861 struct ring_info *ring = &mac_control->rings[i];
862
863 blk_cnt = rx_cfg->num_rxd /
864 (rxd_count[nic->rxd_mode] + 1);
865 size = sizeof(struct buffAdd *) * blk_cnt;
866 ring->ba = kmalloc(size, GFP_KERNEL);
867 if (!ring->ba)
868 return -ENOMEM;
869 mem_allocated += size;
870 for (j = 0; j < blk_cnt; j++) {
871 int k = 0;
872
873 size = sizeof(struct buffAdd) *
874 (rxd_count[nic->rxd_mode] + 1);
875 ring->ba[j] = kmalloc(size, GFP_KERNEL);
876 if (!ring->ba[j])
877 return -ENOMEM;
878 mem_allocated += size;
879 while (k != rxd_count[nic->rxd_mode]) {
880 ba = &ring->ba[j][k];
881 size = BUF0_LEN + ALIGN_SIZE;
882 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
883 if (!ba->ba_0_org)
884 return -ENOMEM;
885 mem_allocated += size;
886 tmp = (unsigned long)ba->ba_0_org;
887 tmp += ALIGN_SIZE;
888 tmp &= ~((unsigned long)ALIGN_SIZE);
889 ba->ba_0 = (void *)tmp;
890
891 size = BUF1_LEN + ALIGN_SIZE;
892 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
893 if (!ba->ba_1_org)
894 return -ENOMEM;
895 mem_allocated += size;
896 tmp = (unsigned long)ba->ba_1_org;
897 tmp += ALIGN_SIZE;
898 tmp &= ~((unsigned long)ALIGN_SIZE);
899 ba->ba_1 = (void *)tmp;
900 k++;
901 }
902 }
903 }
904 }
905
906 /* Allocation and initialization of Statistics block */
907 size = sizeof(struct stat_block);
908 mac_control->stats_mem =
909 pci_alloc_consistent(nic->pdev, size,
910 &mac_control->stats_mem_phy);
911
912 if (!mac_control->stats_mem) {
913 /*
914 * In case of failure, free_shared_mem() is called, which
915 * should free any memory that was alloced till the
916 * failure happened.
917 */
918 return -ENOMEM;
919 }
920 mem_allocated += size;
921 mac_control->stats_mem_sz = size;
922
923 tmp_v_addr = mac_control->stats_mem;
924 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
925 memset(tmp_v_addr, 0, size);
926 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n", dev->name,
927 (unsigned long long)tmp_p_addr);
928 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
929 return SUCCESS;
930 }
931
932 /**
933 * free_shared_mem - Free the allocated Memory
934 * @nic: Device private variable.
935 * Description: This function is to free all memory locations allocated by
936 * the init_shared_mem() function and return it to the kernel.
937 */
938
939 static void free_shared_mem(struct s2io_nic *nic)
940 {
941 int i, j, blk_cnt, size;
942 void *tmp_v_addr;
943 dma_addr_t tmp_p_addr;
944 int lst_size, lst_per_page;
945 struct net_device *dev;
946 int page_num = 0;
947 struct config_param *config;
948 struct mac_info *mac_control;
949 struct stat_block *stats;
950 struct swStat *swstats;
951
952 if (!nic)
953 return;
954
955 dev = nic->dev;
956
957 config = &nic->config;
958 mac_control = &nic->mac_control;
959 stats = mac_control->stats_info;
960 swstats = &stats->sw_stat;
961
962 lst_size = sizeof(struct TxD) * config->max_txds;
963 lst_per_page = PAGE_SIZE / lst_size;
964
965 for (i = 0; i < config->tx_fifo_num; i++) {
966 struct fifo_info *fifo = &mac_control->fifos[i];
967 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
968
969 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
970 for (j = 0; j < page_num; j++) {
971 int mem_blks = (j * lst_per_page);
972 struct list_info_hold *fli;
973
974 if (!fifo->list_info)
975 return;
976
977 fli = &fifo->list_info[mem_blks];
978 if (!fli->list_virt_addr)
979 break;
980 pci_free_consistent(nic->pdev, PAGE_SIZE,
981 fli->list_virt_addr,
982 fli->list_phy_addr);
983 swstats->mem_freed += PAGE_SIZE;
984 }
985 /* If we got a zero DMA address during allocation,
986 * free the page now
987 */
988 if (mac_control->zerodma_virt_addr) {
989 pci_free_consistent(nic->pdev, PAGE_SIZE,
990 mac_control->zerodma_virt_addr,
991 (dma_addr_t)0);
992 DBG_PRINT(INIT_DBG,
993 "%s: Freeing TxDL with zero DMA address. "
994 "Virtual address %p\n",
995 dev->name, mac_control->zerodma_virt_addr);
996 swstats->mem_freed += PAGE_SIZE;
997 }
998 kfree(fifo->list_info);
999 swstats->mem_freed += tx_cfg->fifo_len *
1000 sizeof(struct list_info_hold);
1001 }
1002
1003 size = SIZE_OF_BLOCK;
1004 for (i = 0; i < config->rx_ring_num; i++) {
1005 struct ring_info *ring = &mac_control->rings[i];
1006
1007 blk_cnt = ring->block_count;
1008 for (j = 0; j < blk_cnt; j++) {
1009 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1010 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1011 if (tmp_v_addr == NULL)
1012 break;
1013 pci_free_consistent(nic->pdev, size,
1014 tmp_v_addr, tmp_p_addr);
1015 swstats->mem_freed += size;
1016 kfree(ring->rx_blocks[j].rxds);
1017 swstats->mem_freed += sizeof(struct rxd_info) *
1018 rxd_count[nic->rxd_mode];
1019 }
1020 }
1021
1022 if (nic->rxd_mode == RXD_MODE_3B) {
1023 /* Freeing buffer storage addresses in 2BUFF mode. */
1024 for (i = 0; i < config->rx_ring_num; i++) {
1025 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1026 struct ring_info *ring = &mac_control->rings[i];
1027
1028 blk_cnt = rx_cfg->num_rxd /
1029 (rxd_count[nic->rxd_mode] + 1);
1030 for (j = 0; j < blk_cnt; j++) {
1031 int k = 0;
1032 if (!ring->ba[j])
1033 continue;
1034 while (k != rxd_count[nic->rxd_mode]) {
1035 struct buffAdd *ba = &ring->ba[j][k];
1036 kfree(ba->ba_0_org);
1037 swstats->mem_freed +=
1038 BUF0_LEN + ALIGN_SIZE;
1039 kfree(ba->ba_1_org);
1040 swstats->mem_freed +=
1041 BUF1_LEN + ALIGN_SIZE;
1042 k++;
1043 }
1044 kfree(ring->ba[j]);
1045 swstats->mem_freed += sizeof(struct buffAdd) *
1046 (rxd_count[nic->rxd_mode] + 1);
1047 }
1048 kfree(ring->ba);
1049 swstats->mem_freed += sizeof(struct buffAdd *) *
1050 blk_cnt;
1051 }
1052 }
1053
1054 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1055 struct fifo_info *fifo = &mac_control->fifos[i];
1056 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1057
1058 if (fifo->ufo_in_band_v) {
1059 swstats->mem_freed += tx_cfg->fifo_len *
1060 sizeof(u64);
1061 kfree(fifo->ufo_in_band_v);
1062 }
1063 }
1064
1065 if (mac_control->stats_mem) {
1066 swstats->mem_freed += mac_control->stats_mem_sz;
1067 pci_free_consistent(nic->pdev,
1068 mac_control->stats_mem_sz,
1069 mac_control->stats_mem,
1070 mac_control->stats_mem_phy);
1071 }
1072 }
1073
1074 /**
1075 * s2io_verify_pci_mode -
1076 */
1077
1078 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1079 {
1080 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1081 register u64 val64 = 0;
1082 int mode;
1083
1084 val64 = readq(&bar0->pci_mode);
1085 mode = (u8)GET_PCI_MODE(val64);
1086
1087 if (val64 & PCI_MODE_UNKNOWN_MODE)
1088 return -1; /* Unknown PCI mode */
1089 return mode;
1090 }
1091
1092 #define NEC_VENID 0x1033
1093 #define NEC_DEVID 0x0125
1094 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1095 {
1096 struct pci_dev *tdev = NULL;
1097 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1098 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1099 if (tdev->bus == s2io_pdev->bus->parent) {
1100 pci_dev_put(tdev);
1101 return 1;
1102 }
1103 }
1104 }
1105 return 0;
1106 }
1107
1108 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1109 /**
1110 * s2io_print_pci_mode -
1111 */
1112 static int s2io_print_pci_mode(struct s2io_nic *nic)
1113 {
1114 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1115 register u64 val64 = 0;
1116 int mode;
1117 struct config_param *config = &nic->config;
1118 const char *pcimode;
1119
1120 val64 = readq(&bar0->pci_mode);
1121 mode = (u8)GET_PCI_MODE(val64);
1122
1123 if (val64 & PCI_MODE_UNKNOWN_MODE)
1124 return -1; /* Unknown PCI mode */
1125
1126 config->bus_speed = bus_speed[mode];
1127
1128 if (s2io_on_nec_bridge(nic->pdev)) {
1129 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1130 nic->dev->name);
1131 return mode;
1132 }
1133
1134 switch (mode) {
1135 case PCI_MODE_PCI_33:
1136 pcimode = "33MHz PCI bus";
1137 break;
1138 case PCI_MODE_PCI_66:
1139 pcimode = "66MHz PCI bus";
1140 break;
1141 case PCI_MODE_PCIX_M1_66:
1142 pcimode = "66MHz PCIX(M1) bus";
1143 break;
1144 case PCI_MODE_PCIX_M1_100:
1145 pcimode = "100MHz PCIX(M1) bus";
1146 break;
1147 case PCI_MODE_PCIX_M1_133:
1148 pcimode = "133MHz PCIX(M1) bus";
1149 break;
1150 case PCI_MODE_PCIX_M2_66:
1151 pcimode = "133MHz PCIX(M2) bus";
1152 break;
1153 case PCI_MODE_PCIX_M2_100:
1154 pcimode = "200MHz PCIX(M2) bus";
1155 break;
1156 case PCI_MODE_PCIX_M2_133:
1157 pcimode = "266MHz PCIX(M2) bus";
1158 break;
1159 default:
1160 pcimode = "unsupported bus!";
1161 mode = -1;
1162 }
1163
1164 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1165 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1166
1167 return mode;
1168 }
1169
1170 /**
1171 * init_tti - Initialization transmit traffic interrupt scheme
1172 * @nic: device private variable
1173 * @link: link status (UP/DOWN) used to enable/disable continuous
1174 * transmit interrupts
1175 * Description: The function configures transmit traffic interrupts
1176 * Return Value: SUCCESS on success and
1177 * '-1' on failure
1178 */
1179
1180 static int init_tti(struct s2io_nic *nic, int link)
1181 {
1182 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1183 register u64 val64 = 0;
1184 int i;
1185 struct config_param *config = &nic->config;
1186
1187 for (i = 0; i < config->tx_fifo_num; i++) {
1188 /*
1189 * TTI Initialization. Default Tx timer gets us about
1190 * 250 interrupts per sec. Continuous interrupts are enabled
1191 * by default.
1192 */
1193 if (nic->device_type == XFRAME_II_DEVICE) {
1194 int count = (nic->config.bus_speed * 125)/2;
1195 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1196 } else
1197 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1198
1199 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1200 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1201 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1202 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1203 if (i == 0)
1204 if (use_continuous_tx_intrs && (link == LINK_UP))
1205 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1206 writeq(val64, &bar0->tti_data1_mem);
1207
1208 if (nic->config.intr_type == MSI_X) {
1209 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1210 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1211 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1212 TTI_DATA2_MEM_TX_UFC_D(0x300);
1213 } else {
1214 if ((nic->config.tx_steering_type ==
1215 TX_DEFAULT_STEERING) &&
1216 (config->tx_fifo_num > 1) &&
1217 (i >= nic->udp_fifo_idx) &&
1218 (i < (nic->udp_fifo_idx +
1219 nic->total_udp_fifos)))
1220 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1221 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1222 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1223 TTI_DATA2_MEM_TX_UFC_D(0x120);
1224 else
1225 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1226 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1227 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1228 TTI_DATA2_MEM_TX_UFC_D(0x80);
1229 }
1230
1231 writeq(val64, &bar0->tti_data2_mem);
1232
1233 val64 = TTI_CMD_MEM_WE |
1234 TTI_CMD_MEM_STROBE_NEW_CMD |
1235 TTI_CMD_MEM_OFFSET(i);
1236 writeq(val64, &bar0->tti_command_mem);
1237
1238 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1239 TTI_CMD_MEM_STROBE_NEW_CMD,
1240 S2IO_BIT_RESET) != SUCCESS)
1241 return FAILURE;
1242 }
1243
1244 return SUCCESS;
1245 }
1246
1247 /**
1248 * init_nic - Initialization of hardware
1249 * @nic: device private variable
1250 * Description: The function sequentially configures every block
1251 * of the H/W from their reset values.
1252 * Return Value: SUCCESS on success and
1253 * '-1' on failure (endian settings incorrect).
1254 */
1255
1256 static int init_nic(struct s2io_nic *nic)
1257 {
1258 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1259 struct net_device *dev = nic->dev;
1260 register u64 val64 = 0;
1261 void __iomem *add;
1262 u32 time;
1263 int i, j;
1264 int dtx_cnt = 0;
1265 unsigned long long mem_share;
1266 int mem_size;
1267 struct config_param *config = &nic->config;
1268 struct mac_info *mac_control = &nic->mac_control;
1269
1270 /* to set the swapper controle on the card */
1271 if (s2io_set_swapper(nic)) {
1272 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1273 return -EIO;
1274 }
1275
1276 /*
1277 * Herc requires EOI to be removed from reset before XGXS, so..
1278 */
1279 if (nic->device_type & XFRAME_II_DEVICE) {
1280 val64 = 0xA500000000ULL;
1281 writeq(val64, &bar0->sw_reset);
1282 msleep(500);
1283 val64 = readq(&bar0->sw_reset);
1284 }
1285
1286 /* Remove XGXS from reset state */
1287 val64 = 0;
1288 writeq(val64, &bar0->sw_reset);
1289 msleep(500);
1290 val64 = readq(&bar0->sw_reset);
1291
1292 /* Ensure that it's safe to access registers by checking
1293 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1294 */
1295 if (nic->device_type == XFRAME_II_DEVICE) {
1296 for (i = 0; i < 50; i++) {
1297 val64 = readq(&bar0->adapter_status);
1298 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1299 break;
1300 msleep(10);
1301 }
1302 if (i == 50)
1303 return -ENODEV;
1304 }
1305
1306 /* Enable Receiving broadcasts */
1307 add = &bar0->mac_cfg;
1308 val64 = readq(&bar0->mac_cfg);
1309 val64 |= MAC_RMAC_BCAST_ENABLE;
1310 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1311 writel((u32)val64, add);
1312 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1313 writel((u32) (val64 >> 32), (add + 4));
1314
1315 /* Read registers in all blocks */
1316 val64 = readq(&bar0->mac_int_mask);
1317 val64 = readq(&bar0->mc_int_mask);
1318 val64 = readq(&bar0->xgxs_int_mask);
1319
1320 /* Set MTU */
1321 val64 = dev->mtu;
1322 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1323
1324 if (nic->device_type & XFRAME_II_DEVICE) {
1325 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1326 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1327 &bar0->dtx_control, UF);
1328 if (dtx_cnt & 0x1)
1329 msleep(1); /* Necessary!! */
1330 dtx_cnt++;
1331 }
1332 } else {
1333 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1334 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1335 &bar0->dtx_control, UF);
1336 val64 = readq(&bar0->dtx_control);
1337 dtx_cnt++;
1338 }
1339 }
1340
1341 /* Tx DMA Initialization */
1342 val64 = 0;
1343 writeq(val64, &bar0->tx_fifo_partition_0);
1344 writeq(val64, &bar0->tx_fifo_partition_1);
1345 writeq(val64, &bar0->tx_fifo_partition_2);
1346 writeq(val64, &bar0->tx_fifo_partition_3);
1347
1348 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1349 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1350
1351 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1352 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1353
1354 if (i == (config->tx_fifo_num - 1)) {
1355 if (i % 2 == 0)
1356 i++;
1357 }
1358
1359 switch (i) {
1360 case 1:
1361 writeq(val64, &bar0->tx_fifo_partition_0);
1362 val64 = 0;
1363 j = 0;
1364 break;
1365 case 3:
1366 writeq(val64, &bar0->tx_fifo_partition_1);
1367 val64 = 0;
1368 j = 0;
1369 break;
1370 case 5:
1371 writeq(val64, &bar0->tx_fifo_partition_2);
1372 val64 = 0;
1373 j = 0;
1374 break;
1375 case 7:
1376 writeq(val64, &bar0->tx_fifo_partition_3);
1377 val64 = 0;
1378 j = 0;
1379 break;
1380 default:
1381 j++;
1382 break;
1383 }
1384 }
1385
1386 /*
1387 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1388 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1389 */
1390 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1391 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1392
1393 val64 = readq(&bar0->tx_fifo_partition_0);
1394 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1395 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1396
1397 /*
1398 * Initialization of Tx_PA_CONFIG register to ignore packet
1399 * integrity checking.
1400 */
1401 val64 = readq(&bar0->tx_pa_cfg);
1402 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1403 TX_PA_CFG_IGNORE_SNAP_OUI |
1404 TX_PA_CFG_IGNORE_LLC_CTRL |
1405 TX_PA_CFG_IGNORE_L2_ERR;
1406 writeq(val64, &bar0->tx_pa_cfg);
1407
1408 /* Rx DMA intialization. */
1409 val64 = 0;
1410 for (i = 0; i < config->rx_ring_num; i++) {
1411 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1412
1413 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1414 }
1415 writeq(val64, &bar0->rx_queue_priority);
1416
1417 /*
1418 * Allocating equal share of memory to all the
1419 * configured Rings.
1420 */
1421 val64 = 0;
1422 if (nic->device_type & XFRAME_II_DEVICE)
1423 mem_size = 32;
1424 else
1425 mem_size = 64;
1426
1427 for (i = 0; i < config->rx_ring_num; i++) {
1428 switch (i) {
1429 case 0:
1430 mem_share = (mem_size / config->rx_ring_num +
1431 mem_size % config->rx_ring_num);
1432 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1433 continue;
1434 case 1:
1435 mem_share = (mem_size / config->rx_ring_num);
1436 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1437 continue;
1438 case 2:
1439 mem_share = (mem_size / config->rx_ring_num);
1440 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1441 continue;
1442 case 3:
1443 mem_share = (mem_size / config->rx_ring_num);
1444 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1445 continue;
1446 case 4:
1447 mem_share = (mem_size / config->rx_ring_num);
1448 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1449 continue;
1450 case 5:
1451 mem_share = (mem_size / config->rx_ring_num);
1452 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1453 continue;
1454 case 6:
1455 mem_share = (mem_size / config->rx_ring_num);
1456 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1457 continue;
1458 case 7:
1459 mem_share = (mem_size / config->rx_ring_num);
1460 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1461 continue;
1462 }
1463 }
1464 writeq(val64, &bar0->rx_queue_cfg);
1465
1466 /*
1467 * Filling Tx round robin registers
1468 * as per the number of FIFOs for equal scheduling priority
1469 */
1470 switch (config->tx_fifo_num) {
1471 case 1:
1472 val64 = 0x0;
1473 writeq(val64, &bar0->tx_w_round_robin_0);
1474 writeq(val64, &bar0->tx_w_round_robin_1);
1475 writeq(val64, &bar0->tx_w_round_robin_2);
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 writeq(val64, &bar0->tx_w_round_robin_4);
1478 break;
1479 case 2:
1480 val64 = 0x0001000100010001ULL;
1481 writeq(val64, &bar0->tx_w_round_robin_0);
1482 writeq(val64, &bar0->tx_w_round_robin_1);
1483 writeq(val64, &bar0->tx_w_round_robin_2);
1484 writeq(val64, &bar0->tx_w_round_robin_3);
1485 val64 = 0x0001000100000000ULL;
1486 writeq(val64, &bar0->tx_w_round_robin_4);
1487 break;
1488 case 3:
1489 val64 = 0x0001020001020001ULL;
1490 writeq(val64, &bar0->tx_w_round_robin_0);
1491 val64 = 0x0200010200010200ULL;
1492 writeq(val64, &bar0->tx_w_round_robin_1);
1493 val64 = 0x0102000102000102ULL;
1494 writeq(val64, &bar0->tx_w_round_robin_2);
1495 val64 = 0x0001020001020001ULL;
1496 writeq(val64, &bar0->tx_w_round_robin_3);
1497 val64 = 0x0200010200000000ULL;
1498 writeq(val64, &bar0->tx_w_round_robin_4);
1499 break;
1500 case 4:
1501 val64 = 0x0001020300010203ULL;
1502 writeq(val64, &bar0->tx_w_round_robin_0);
1503 writeq(val64, &bar0->tx_w_round_robin_1);
1504 writeq(val64, &bar0->tx_w_round_robin_2);
1505 writeq(val64, &bar0->tx_w_round_robin_3);
1506 val64 = 0x0001020300000000ULL;
1507 writeq(val64, &bar0->tx_w_round_robin_4);
1508 break;
1509 case 5:
1510 val64 = 0x0001020304000102ULL;
1511 writeq(val64, &bar0->tx_w_round_robin_0);
1512 val64 = 0x0304000102030400ULL;
1513 writeq(val64, &bar0->tx_w_round_robin_1);
1514 val64 = 0x0102030400010203ULL;
1515 writeq(val64, &bar0->tx_w_round_robin_2);
1516 val64 = 0x0400010203040001ULL;
1517 writeq(val64, &bar0->tx_w_round_robin_3);
1518 val64 = 0x0203040000000000ULL;
1519 writeq(val64, &bar0->tx_w_round_robin_4);
1520 break;
1521 case 6:
1522 val64 = 0x0001020304050001ULL;
1523 writeq(val64, &bar0->tx_w_round_robin_0);
1524 val64 = 0x0203040500010203ULL;
1525 writeq(val64, &bar0->tx_w_round_robin_1);
1526 val64 = 0x0405000102030405ULL;
1527 writeq(val64, &bar0->tx_w_round_robin_2);
1528 val64 = 0x0001020304050001ULL;
1529 writeq(val64, &bar0->tx_w_round_robin_3);
1530 val64 = 0x0203040500000000ULL;
1531 writeq(val64, &bar0->tx_w_round_robin_4);
1532 break;
1533 case 7:
1534 val64 = 0x0001020304050600ULL;
1535 writeq(val64, &bar0->tx_w_round_robin_0);
1536 val64 = 0x0102030405060001ULL;
1537 writeq(val64, &bar0->tx_w_round_robin_1);
1538 val64 = 0x0203040506000102ULL;
1539 writeq(val64, &bar0->tx_w_round_robin_2);
1540 val64 = 0x0304050600010203ULL;
1541 writeq(val64, &bar0->tx_w_round_robin_3);
1542 val64 = 0x0405060000000000ULL;
1543 writeq(val64, &bar0->tx_w_round_robin_4);
1544 break;
1545 case 8:
1546 val64 = 0x0001020304050607ULL;
1547 writeq(val64, &bar0->tx_w_round_robin_0);
1548 writeq(val64, &bar0->tx_w_round_robin_1);
1549 writeq(val64, &bar0->tx_w_round_robin_2);
1550 writeq(val64, &bar0->tx_w_round_robin_3);
1551 val64 = 0x0001020300000000ULL;
1552 writeq(val64, &bar0->tx_w_round_robin_4);
1553 break;
1554 }
1555
1556 /* Enable all configured Tx FIFO partitions */
1557 val64 = readq(&bar0->tx_fifo_partition_0);
1558 val64 |= (TX_FIFO_PARTITION_EN);
1559 writeq(val64, &bar0->tx_fifo_partition_0);
1560
1561 /* Filling the Rx round robin registers as per the
1562 * number of Rings and steering based on QoS with
1563 * equal priority.
1564 */
1565 switch (config->rx_ring_num) {
1566 case 1:
1567 val64 = 0x0;
1568 writeq(val64, &bar0->rx_w_round_robin_0);
1569 writeq(val64, &bar0->rx_w_round_robin_1);
1570 writeq(val64, &bar0->rx_w_round_robin_2);
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 writeq(val64, &bar0->rx_w_round_robin_4);
1573
1574 val64 = 0x8080808080808080ULL;
1575 writeq(val64, &bar0->rts_qos_steering);
1576 break;
1577 case 2:
1578 val64 = 0x0001000100010001ULL;
1579 writeq(val64, &bar0->rx_w_round_robin_0);
1580 writeq(val64, &bar0->rx_w_round_robin_1);
1581 writeq(val64, &bar0->rx_w_round_robin_2);
1582 writeq(val64, &bar0->rx_w_round_robin_3);
1583 val64 = 0x0001000100000000ULL;
1584 writeq(val64, &bar0->rx_w_round_robin_4);
1585
1586 val64 = 0x8080808040404040ULL;
1587 writeq(val64, &bar0->rts_qos_steering);
1588 break;
1589 case 3:
1590 val64 = 0x0001020001020001ULL;
1591 writeq(val64, &bar0->rx_w_round_robin_0);
1592 val64 = 0x0200010200010200ULL;
1593 writeq(val64, &bar0->rx_w_round_robin_1);
1594 val64 = 0x0102000102000102ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_2);
1596 val64 = 0x0001020001020001ULL;
1597 writeq(val64, &bar0->rx_w_round_robin_3);
1598 val64 = 0x0200010200000000ULL;
1599 writeq(val64, &bar0->rx_w_round_robin_4);
1600
1601 val64 = 0x8080804040402020ULL;
1602 writeq(val64, &bar0->rts_qos_steering);
1603 break;
1604 case 4:
1605 val64 = 0x0001020300010203ULL;
1606 writeq(val64, &bar0->rx_w_round_robin_0);
1607 writeq(val64, &bar0->rx_w_round_robin_1);
1608 writeq(val64, &bar0->rx_w_round_robin_2);
1609 writeq(val64, &bar0->rx_w_round_robin_3);
1610 val64 = 0x0001020300000000ULL;
1611 writeq(val64, &bar0->rx_w_round_robin_4);
1612
1613 val64 = 0x8080404020201010ULL;
1614 writeq(val64, &bar0->rts_qos_steering);
1615 break;
1616 case 5:
1617 val64 = 0x0001020304000102ULL;
1618 writeq(val64, &bar0->rx_w_round_robin_0);
1619 val64 = 0x0304000102030400ULL;
1620 writeq(val64, &bar0->rx_w_round_robin_1);
1621 val64 = 0x0102030400010203ULL;
1622 writeq(val64, &bar0->rx_w_round_robin_2);
1623 val64 = 0x0400010203040001ULL;
1624 writeq(val64, &bar0->rx_w_round_robin_3);
1625 val64 = 0x0203040000000000ULL;
1626 writeq(val64, &bar0->rx_w_round_robin_4);
1627
1628 val64 = 0x8080404020201008ULL;
1629 writeq(val64, &bar0->rts_qos_steering);
1630 break;
1631 case 6:
1632 val64 = 0x0001020304050001ULL;
1633 writeq(val64, &bar0->rx_w_round_robin_0);
1634 val64 = 0x0203040500010203ULL;
1635 writeq(val64, &bar0->rx_w_round_robin_1);
1636 val64 = 0x0405000102030405ULL;
1637 writeq(val64, &bar0->rx_w_round_robin_2);
1638 val64 = 0x0001020304050001ULL;
1639 writeq(val64, &bar0->rx_w_round_robin_3);
1640 val64 = 0x0203040500000000ULL;
1641 writeq(val64, &bar0->rx_w_round_robin_4);
1642
1643 val64 = 0x8080404020100804ULL;
1644 writeq(val64, &bar0->rts_qos_steering);
1645 break;
1646 case 7:
1647 val64 = 0x0001020304050600ULL;
1648 writeq(val64, &bar0->rx_w_round_robin_0);
1649 val64 = 0x0102030405060001ULL;
1650 writeq(val64, &bar0->rx_w_round_robin_1);
1651 val64 = 0x0203040506000102ULL;
1652 writeq(val64, &bar0->rx_w_round_robin_2);
1653 val64 = 0x0304050600010203ULL;
1654 writeq(val64, &bar0->rx_w_round_robin_3);
1655 val64 = 0x0405060000000000ULL;
1656 writeq(val64, &bar0->rx_w_round_robin_4);
1657
1658 val64 = 0x8080402010080402ULL;
1659 writeq(val64, &bar0->rts_qos_steering);
1660 break;
1661 case 8:
1662 val64 = 0x0001020304050607ULL;
1663 writeq(val64, &bar0->rx_w_round_robin_0);
1664 writeq(val64, &bar0->rx_w_round_robin_1);
1665 writeq(val64, &bar0->rx_w_round_robin_2);
1666 writeq(val64, &bar0->rx_w_round_robin_3);
1667 val64 = 0x0001020300000000ULL;
1668 writeq(val64, &bar0->rx_w_round_robin_4);
1669
1670 val64 = 0x8040201008040201ULL;
1671 writeq(val64, &bar0->rts_qos_steering);
1672 break;
1673 }
1674
1675 /* UDP Fix */
1676 val64 = 0;
1677 for (i = 0; i < 8; i++)
1678 writeq(val64, &bar0->rts_frm_len_n[i]);
1679
1680 /* Set the default rts frame length for the rings configured */
1681 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1682 for (i = 0 ; i < config->rx_ring_num ; i++)
1683 writeq(val64, &bar0->rts_frm_len_n[i]);
1684
1685 /* Set the frame length for the configured rings
1686 * desired by the user
1687 */
1688 for (i = 0; i < config->rx_ring_num; i++) {
1689 /* If rts_frm_len[i] == 0 then it is assumed that user not
1690 * specified frame length steering.
1691 * If the user provides the frame length then program
1692 * the rts_frm_len register for those values or else
1693 * leave it as it is.
1694 */
1695 if (rts_frm_len[i] != 0) {
1696 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1697 &bar0->rts_frm_len_n[i]);
1698 }
1699 }
1700
1701 /* Disable differentiated services steering logic */
1702 for (i = 0; i < 64; i++) {
1703 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1704 DBG_PRINT(ERR_DBG,
1705 "%s: rts_ds_steer failed on codepoint %d\n",
1706 dev->name, i);
1707 return -ENODEV;
1708 }
1709 }
1710
1711 /* Program statistics memory */
1712 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1713
1714 if (nic->device_type == XFRAME_II_DEVICE) {
1715 val64 = STAT_BC(0x320);
1716 writeq(val64, &bar0->stat_byte_cnt);
1717 }
1718
1719 /*
1720 * Initializing the sampling rate for the device to calculate the
1721 * bandwidth utilization.
1722 */
1723 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1724 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1725 writeq(val64, &bar0->mac_link_util);
1726
1727 /*
1728 * Initializing the Transmit and Receive Traffic Interrupt
1729 * Scheme.
1730 */
1731
1732 /* Initialize TTI */
1733 if (SUCCESS != init_tti(nic, nic->last_link_state))
1734 return -ENODEV;
1735
1736 /* RTI Initialization */
1737 if (nic->device_type == XFRAME_II_DEVICE) {
1738 /*
1739 * Programmed to generate Apprx 500 Intrs per
1740 * second
1741 */
1742 int count = (nic->config.bus_speed * 125)/4;
1743 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1744 } else
1745 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1746 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1747 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1748 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1749 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1750
1751 writeq(val64, &bar0->rti_data1_mem);
1752
1753 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1754 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1755 if (nic->config.intr_type == MSI_X)
1756 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1757 RTI_DATA2_MEM_RX_UFC_D(0x40));
1758 else
1759 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1760 RTI_DATA2_MEM_RX_UFC_D(0x80));
1761 writeq(val64, &bar0->rti_data2_mem);
1762
1763 for (i = 0; i < config->rx_ring_num; i++) {
1764 val64 = RTI_CMD_MEM_WE |
1765 RTI_CMD_MEM_STROBE_NEW_CMD |
1766 RTI_CMD_MEM_OFFSET(i);
1767 writeq(val64, &bar0->rti_command_mem);
1768
1769 /*
1770 * Once the operation completes, the Strobe bit of the
1771 * command register will be reset. We poll for this
1772 * particular condition. We wait for a maximum of 500ms
1773 * for the operation to complete, if it's not complete
1774 * by then we return error.
1775 */
1776 time = 0;
1777 while (true) {
1778 val64 = readq(&bar0->rti_command_mem);
1779 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1780 break;
1781
1782 if (time > 10) {
1783 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1784 dev->name);
1785 return -ENODEV;
1786 }
1787 time++;
1788 msleep(50);
1789 }
1790 }
1791
1792 /*
1793 * Initializing proper values as Pause threshold into all
1794 * the 8 Queues on Rx side.
1795 */
1796 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1798
1799 /* Disable RMAC PAD STRIPPING */
1800 add = &bar0->mac_cfg;
1801 val64 = readq(&bar0->mac_cfg);
1802 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804 writel((u32) (val64), add);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64 >> 32), (add + 4));
1807 val64 = readq(&bar0->mac_cfg);
1808
1809 /* Enable FCS stripping by adapter */
1810 add = &bar0->mac_cfg;
1811 val64 = readq(&bar0->mac_cfg);
1812 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813 if (nic->device_type == XFRAME_II_DEVICE)
1814 writeq(val64, &bar0->mac_cfg);
1815 else {
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64), add);
1818 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819 writel((u32) (val64 >> 32), (add + 4));
1820 }
1821
1822 /*
1823 * Set the time value to be inserted in the pause frame
1824 * generated by xena.
1825 */
1826 val64 = readq(&bar0->rmac_pause_cfg);
1827 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829 writeq(val64, &bar0->rmac_pause_cfg);
1830
1831 /*
1832 * Set the Threshold Limit for Generating the pause frame
1833 * If the amount of data in any Queue exceeds ratio of
1834 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835 * pause frame is generated
1836 */
1837 val64 = 0;
1838 for (i = 0; i < 4; i++) {
1839 val64 |= (((u64)0xFF00 |
1840 nic->mac_control.mc_pause_threshold_q0q3)
1841 << (i * 2 * 8));
1842 }
1843 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1844
1845 val64 = 0;
1846 for (i = 0; i < 4; i++) {
1847 val64 |= (((u64)0xFF00 |
1848 nic->mac_control.mc_pause_threshold_q4q7)
1849 << (i * 2 * 8));
1850 }
1851 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1852
1853 /*
1854 * TxDMA will stop Read request if the number of read split has
1855 * exceeded the limit pointed by shared_splits
1856 */
1857 val64 = readq(&bar0->pic_control);
1858 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1859 writeq(val64, &bar0->pic_control);
1860
1861 if (nic->config.bus_speed == 266) {
1862 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1863 writeq(0x0, &bar0->read_retry_delay);
1864 writeq(0x0, &bar0->write_retry_delay);
1865 }
1866
1867 /*
1868 * Programming the Herc to split every write transaction
1869 * that does not start on an ADB to reduce disconnects.
1870 */
1871 if (nic->device_type == XFRAME_II_DEVICE) {
1872 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1873 MISC_LINK_STABILITY_PRD(3);
1874 writeq(val64, &bar0->misc_control);
1875 val64 = readq(&bar0->pic_control2);
1876 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1877 writeq(val64, &bar0->pic_control2);
1878 }
1879 if (strstr(nic->product_name, "CX4")) {
1880 val64 = TMAC_AVG_IPG(0x17);
1881 writeq(val64, &bar0->tmac_avg_ipg);
1882 }
1883
1884 return SUCCESS;
1885 }
1886 #define LINK_UP_DOWN_INTERRUPT 1
1887 #define MAC_RMAC_ERR_TIMER 2
1888
1889 static int s2io_link_fault_indication(struct s2io_nic *nic)
1890 {
1891 if (nic->device_type == XFRAME_II_DEVICE)
1892 return LINK_UP_DOWN_INTERRUPT;
1893 else
1894 return MAC_RMAC_ERR_TIMER;
1895 }
1896
1897 /**
1898 * do_s2io_write_bits - update alarm bits in alarm register
1899 * @value: alarm bits
1900 * @flag: interrupt status
1901 * @addr: address value
1902 * Description: update alarm bits in alarm register
1903 * Return Value:
1904 * NONE.
1905 */
1906 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1907 {
1908 u64 temp64;
1909
1910 temp64 = readq(addr);
1911
1912 if (flag == ENABLE_INTRS)
1913 temp64 &= ~((u64)value);
1914 else
1915 temp64 |= ((u64)value);
1916 writeq(temp64, addr);
1917 }
1918
1919 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1920 {
1921 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1922 register u64 gen_int_mask = 0;
1923 u64 interruptible;
1924
1925 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1926 if (mask & TX_DMA_INTR) {
1927 gen_int_mask |= TXDMA_INT_M;
1928
1929 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1930 TXDMA_PCC_INT | TXDMA_TTI_INT |
1931 TXDMA_LSO_INT | TXDMA_TPA_INT |
1932 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1933
1934 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1935 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1936 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1937 &bar0->pfc_err_mask);
1938
1939 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1940 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1941 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1942
1943 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1944 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1945 PCC_N_SERR | PCC_6_COF_OV_ERR |
1946 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1947 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1948 PCC_TXB_ECC_SG_ERR,
1949 flag, &bar0->pcc_err_mask);
1950
1951 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1952 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1953
1954 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1955 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1956 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1957 flag, &bar0->lso_err_mask);
1958
1959 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1960 flag, &bar0->tpa_err_mask);
1961
1962 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1963 }
1964
1965 if (mask & TX_MAC_INTR) {
1966 gen_int_mask |= TXMAC_INT_M;
1967 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1968 &bar0->mac_int_mask);
1969 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1970 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1971 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1972 flag, &bar0->mac_tmac_err_mask);
1973 }
1974
1975 if (mask & TX_XGXS_INTR) {
1976 gen_int_mask |= TXXGXS_INT_M;
1977 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1978 &bar0->xgxs_int_mask);
1979 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1980 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1981 flag, &bar0->xgxs_txgxs_err_mask);
1982 }
1983
1984 if (mask & RX_DMA_INTR) {
1985 gen_int_mask |= RXDMA_INT_M;
1986 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1987 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1988 flag, &bar0->rxdma_int_mask);
1989 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1990 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1991 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1992 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1993 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1994 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1995 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1996 &bar0->prc_pcix_err_mask);
1997 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1998 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1999 &bar0->rpa_err_mask);
2000 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2001 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2002 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2003 RDA_FRM_ECC_SG_ERR |
2004 RDA_MISC_ERR|RDA_PCIX_ERR,
2005 flag, &bar0->rda_err_mask);
2006 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2007 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2008 flag, &bar0->rti_err_mask);
2009 }
2010
2011 if (mask & RX_MAC_INTR) {
2012 gen_int_mask |= RXMAC_INT_M;
2013 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2014 &bar0->mac_int_mask);
2015 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2016 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2017 RMAC_DOUBLE_ECC_ERR);
2018 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2019 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2020 do_s2io_write_bits(interruptible,
2021 flag, &bar0->mac_rmac_err_mask);
2022 }
2023
2024 if (mask & RX_XGXS_INTR) {
2025 gen_int_mask |= RXXGXS_INT_M;
2026 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2027 &bar0->xgxs_int_mask);
2028 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2029 &bar0->xgxs_rxgxs_err_mask);
2030 }
2031
2032 if (mask & MC_INTR) {
2033 gen_int_mask |= MC_INT_M;
2034 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2035 flag, &bar0->mc_int_mask);
2036 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2037 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038 &bar0->mc_err_mask);
2039 }
2040 nic->general_int_mask = gen_int_mask;
2041
2042 /* Remove this line when alarm interrupts are enabled */
2043 nic->general_int_mask = 0;
2044 }
2045
2046 /**
2047 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2048 * @nic: device private variable,
2049 * @mask: A mask indicating which Intr block must be modified and,
2050 * @flag: A flag indicating whether to enable or disable the Intrs.
2051 * Description: This function will either disable or enable the interrupts
2052 * depending on the flag argument. The mask argument can be used to
2053 * enable/disable any Intr block.
2054 * Return Value: NONE.
2055 */
2056
2057 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2058 {
2059 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2060 register u64 temp64 = 0, intr_mask = 0;
2061
2062 intr_mask = nic->general_int_mask;
2063
2064 /* Top level interrupt classification */
2065 /* PIC Interrupts */
2066 if (mask & TX_PIC_INTR) {
2067 /* Enable PIC Intrs in the general intr mask register */
2068 intr_mask |= TXPIC_INT_M;
2069 if (flag == ENABLE_INTRS) {
2070 /*
2071 * If Hercules adapter enable GPIO otherwise
2072 * disable all PCIX, Flash, MDIO, IIC and GPIO
2073 * interrupts for now.
2074 * TODO
2075 */
2076 if (s2io_link_fault_indication(nic) ==
2077 LINK_UP_DOWN_INTERRUPT) {
2078 do_s2io_write_bits(PIC_INT_GPIO, flag,
2079 &bar0->pic_int_mask);
2080 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2081 &bar0->gpio_int_mask);
2082 } else
2083 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2084 } else if (flag == DISABLE_INTRS) {
2085 /*
2086 * Disable PIC Intrs in the general
2087 * intr mask register
2088 */
2089 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2090 }
2091 }
2092
2093 /* Tx traffic interrupts */
2094 if (mask & TX_TRAFFIC_INTR) {
2095 intr_mask |= TXTRAFFIC_INT_M;
2096 if (flag == ENABLE_INTRS) {
2097 /*
2098 * Enable all the Tx side interrupts
2099 * writing 0 Enables all 64 TX interrupt levels
2100 */
2101 writeq(0x0, &bar0->tx_traffic_mask);
2102 } else if (flag == DISABLE_INTRS) {
2103 /*
2104 * Disable Tx Traffic Intrs in the general intr mask
2105 * register.
2106 */
2107 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2108 }
2109 }
2110
2111 /* Rx traffic interrupts */
2112 if (mask & RX_TRAFFIC_INTR) {
2113 intr_mask |= RXTRAFFIC_INT_M;
2114 if (flag == ENABLE_INTRS) {
2115 /* writing 0 Enables all 8 RX interrupt levels */
2116 writeq(0x0, &bar0->rx_traffic_mask);
2117 } else if (flag == DISABLE_INTRS) {
2118 /*
2119 * Disable Rx Traffic Intrs in the general intr mask
2120 * register.
2121 */
2122 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2123 }
2124 }
2125
2126 temp64 = readq(&bar0->general_int_mask);
2127 if (flag == ENABLE_INTRS)
2128 temp64 &= ~((u64)intr_mask);
2129 else
2130 temp64 = DISABLE_ALL_INTRS;
2131 writeq(temp64, &bar0->general_int_mask);
2132
2133 nic->general_int_mask = readq(&bar0->general_int_mask);
2134 }
2135
2136 /**
2137 * verify_pcc_quiescent- Checks for PCC quiescent state
2138 * Return: 1 If PCC is quiescence
2139 * 0 If PCC is not quiescence
2140 */
2141 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2142 {
2143 int ret = 0, herc;
2144 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2145 u64 val64 = readq(&bar0->adapter_status);
2146
2147 herc = (sp->device_type == XFRAME_II_DEVICE);
2148
2149 if (flag == false) {
2150 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2151 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2152 ret = 1;
2153 } else {
2154 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2155 ret = 1;
2156 }
2157 } else {
2158 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2159 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2160 ADAPTER_STATUS_RMAC_PCC_IDLE))
2161 ret = 1;
2162 } else {
2163 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2164 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2165 ret = 1;
2166 }
2167 }
2168
2169 return ret;
2170 }
2171 /**
2172 * verify_xena_quiescence - Checks whether the H/W is ready
2173 * Description: Returns whether the H/W is ready to go or not. Depending
2174 * on whether adapter enable bit was written or not the comparison
2175 * differs and the calling function passes the input argument flag to
2176 * indicate this.
2177 * Return: 1 If xena is quiescence
2178 * 0 If Xena is not quiescence
2179 */
2180
2181 static int verify_xena_quiescence(struct s2io_nic *sp)
2182 {
2183 int mode;
2184 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2185 u64 val64 = readq(&bar0->adapter_status);
2186 mode = s2io_verify_pci_mode(sp);
2187
2188 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2189 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2190 return 0;
2191 }
2192 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2193 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2194 return 0;
2195 }
2196 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2197 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2198 return 0;
2199 }
2200 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2201 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2202 return 0;
2203 }
2204 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2205 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2206 return 0;
2207 }
2208 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2209 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2210 return 0;
2211 }
2212 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2213 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2214 return 0;
2215 }
2216 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2217 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2218 return 0;
2219 }
2220
2221 /*
2222 * In PCI 33 mode, the P_PLL is not used, and therefore,
2223 * the the P_PLL_LOCK bit in the adapter_status register will
2224 * not be asserted.
2225 */
2226 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2227 sp->device_type == XFRAME_II_DEVICE &&
2228 mode != PCI_MODE_PCI_33) {
2229 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2230 return 0;
2231 }
2232 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2233 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2234 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2235 return 0;
2236 }
2237 return 1;
2238 }
2239
2240 /**
2241 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2242 * @sp: Pointer to device specifc structure
2243 * Description :
2244 * New procedure to clear mac address reading problems on Alpha platforms
2245 *
2246 */
2247
2248 static void fix_mac_address(struct s2io_nic *sp)
2249 {
2250 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2251 u64 val64;
2252 int i = 0;
2253
2254 while (fix_mac[i] != END_SIGN) {
2255 writeq(fix_mac[i++], &bar0->gpio_control);
2256 udelay(10);
2257 val64 = readq(&bar0->gpio_control);
2258 }
2259 }
2260
2261 /**
2262 * start_nic - Turns the device on
2263 * @nic : device private variable.
2264 * Description:
2265 * This function actually turns the device on. Before this function is
2266 * called,all Registers are configured from their reset states
2267 * and shared memory is allocated but the NIC is still quiescent. On
2268 * calling this function, the device interrupts are cleared and the NIC is
2269 * literally switched on by writing into the adapter control register.
2270 * Return Value:
2271 * SUCCESS on success and -1 on failure.
2272 */
2273
2274 static int start_nic(struct s2io_nic *nic)
2275 {
2276 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2277 struct net_device *dev = nic->dev;
2278 register u64 val64 = 0;
2279 u16 subid, i;
2280 struct config_param *config = &nic->config;
2281 struct mac_info *mac_control = &nic->mac_control;
2282
2283 /* PRC Initialization and configuration */
2284 for (i = 0; i < config->rx_ring_num; i++) {
2285 struct ring_info *ring = &mac_control->rings[i];
2286
2287 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2288 &bar0->prc_rxd0_n[i]);
2289
2290 val64 = readq(&bar0->prc_ctrl_n[i]);
2291 if (nic->rxd_mode == RXD_MODE_1)
2292 val64 |= PRC_CTRL_RC_ENABLED;
2293 else
2294 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2295 if (nic->device_type == XFRAME_II_DEVICE)
2296 val64 |= PRC_CTRL_GROUP_READS;
2297 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2299 writeq(val64, &bar0->prc_ctrl_n[i]);
2300 }
2301
2302 if (nic->rxd_mode == RXD_MODE_3B) {
2303 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304 val64 = readq(&bar0->rx_pa_cfg);
2305 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306 writeq(val64, &bar0->rx_pa_cfg);
2307 }
2308
2309 if (vlan_tag_strip == 0) {
2310 val64 = readq(&bar0->rx_pa_cfg);
2311 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312 writeq(val64, &bar0->rx_pa_cfg);
2313 nic->vlan_strip_flag = 0;
2314 }
2315
2316 /*
2317 * Enabling MC-RLDRAM. After enabling the device, we timeout
2318 * for around 100ms, which is approximately the time required
2319 * for the device to be ready for operation.
2320 */
2321 val64 = readq(&bar0->mc_rldram_mrs);
2322 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324 val64 = readq(&bar0->mc_rldram_mrs);
2325
2326 msleep(100); /* Delay by around 100 ms. */
2327
2328 /* Enabling ECC Protection. */
2329 val64 = readq(&bar0->adapter_control);
2330 val64 &= ~ADAPTER_ECC_EN;
2331 writeq(val64, &bar0->adapter_control);
2332
2333 /*
2334 * Verify if the device is ready to be enabled, if so enable
2335 * it.
2336 */
2337 val64 = readq(&bar0->adapter_status);
2338 if (!verify_xena_quiescence(nic)) {
2339 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2340 "Adapter status reads: 0x%llx\n",
2341 dev->name, (unsigned long long)val64);
2342 return FAILURE;
2343 }
2344
2345 /*
2346 * With some switches, link might be already up at this point.
2347 * Because of this weird behavior, when we enable laser,
2348 * we may not get link. We need to handle this. We cannot
2349 * figure out which switch is misbehaving. So we are forced to
2350 * make a global change.
2351 */
2352
2353 /* Enabling Laser. */
2354 val64 = readq(&bar0->adapter_control);
2355 val64 |= ADAPTER_EOI_TX_ON;
2356 writeq(val64, &bar0->adapter_control);
2357
2358 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2359 /*
2360 * Dont see link state interrupts initally on some switches,
2361 * so directly scheduling the link state task here.
2362 */
2363 schedule_work(&nic->set_link_task);
2364 }
2365 /* SXE-002: Initialize link and activity LED */
2366 subid = nic->pdev->subsystem_device;
2367 if (((subid & 0xFF) >= 0x07) &&
2368 (nic->device_type == XFRAME_I_DEVICE)) {
2369 val64 = readq(&bar0->gpio_control);
2370 val64 |= 0x0000800000000000ULL;
2371 writeq(val64, &bar0->gpio_control);
2372 val64 = 0x0411040400000000ULL;
2373 writeq(val64, (void __iomem *)bar0 + 0x2700);
2374 }
2375
2376 return SUCCESS;
2377 }
2378 /**
2379 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2380 */
2381 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2382 struct TxD *txdlp, int get_off)
2383 {
2384 struct s2io_nic *nic = fifo_data->nic;
2385 struct sk_buff *skb;
2386 struct TxD *txds;
2387 u16 j, frg_cnt;
2388
2389 txds = txdlp;
2390 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2391 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2392 sizeof(u64), PCI_DMA_TODEVICE);
2393 txds++;
2394 }
2395
2396 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2397 if (!skb) {
2398 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2399 return NULL;
2400 }
2401 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2402 skb->len - skb->data_len, PCI_DMA_TODEVICE);
2403 frg_cnt = skb_shinfo(skb)->nr_frags;
2404 if (frg_cnt) {
2405 txds++;
2406 for (j = 0; j < frg_cnt; j++, txds++) {
2407 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2408 if (!txds->Buffer_Pointer)
2409 break;
2410 pci_unmap_page(nic->pdev,
2411 (dma_addr_t)txds->Buffer_Pointer,
2412 frag->size, PCI_DMA_TODEVICE);
2413 }
2414 }
2415 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2416 return skb;
2417 }
2418
2419 /**
2420 * free_tx_buffers - Free all queued Tx buffers
2421 * @nic : device private variable.
2422 * Description:
2423 * Free all queued Tx buffers.
2424 * Return Value: void
2425 */
2426
2427 static void free_tx_buffers(struct s2io_nic *nic)
2428 {
2429 struct net_device *dev = nic->dev;
2430 struct sk_buff *skb;
2431 struct TxD *txdp;
2432 int i, j;
2433 int cnt = 0;
2434 struct config_param *config = &nic->config;
2435 struct mac_info *mac_control = &nic->mac_control;
2436 struct stat_block *stats = mac_control->stats_info;
2437 struct swStat *swstats = &stats->sw_stat;
2438
2439 for (i = 0; i < config->tx_fifo_num; i++) {
2440 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2441 struct fifo_info *fifo = &mac_control->fifos[i];
2442 unsigned long flags;
2443
2444 spin_lock_irqsave(&fifo->tx_lock, flags);
2445 for (j = 0; j < tx_cfg->fifo_len; j++) {
2446 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2447 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2448 if (skb) {
2449 swstats->mem_freed += skb->truesize;
2450 dev_kfree_skb(skb);
2451 cnt++;
2452 }
2453 }
2454 DBG_PRINT(INTR_DBG,
2455 "%s: forcibly freeing %d skbs on FIFO%d\n",
2456 dev->name, cnt, i);
2457 fifo->tx_curr_get_info.offset = 0;
2458 fifo->tx_curr_put_info.offset = 0;
2459 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2460 }
2461 }
2462
2463 /**
2464 * stop_nic - To stop the nic
2465 * @nic ; device private variable.
2466 * Description:
2467 * This function does exactly the opposite of what the start_nic()
2468 * function does. This function is called to stop the device.
2469 * Return Value:
2470 * void.
2471 */
2472
2473 static void stop_nic(struct s2io_nic *nic)
2474 {
2475 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2476 register u64 val64 = 0;
2477 u16 interruptible;
2478
2479 /* Disable all interrupts */
2480 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2481 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2482 interruptible |= TX_PIC_INTR;
2483 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2484
2485 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486 val64 = readq(&bar0->adapter_control);
2487 val64 &= ~(ADAPTER_CNTL_EN);
2488 writeq(val64, &bar0->adapter_control);
2489 }
2490
2491 /**
2492 * fill_rx_buffers - Allocates the Rx side skbs
2493 * @ring_info: per ring structure
2494 * @from_card_up: If this is true, we will map the buffer to get
2495 * the dma address for buf0 and buf1 to give it to the card.
2496 * Else we will sync the already mapped buffer to give it to the card.
2497 * Description:
2498 * The function allocates Rx side skbs and puts the physical
2499 * address of these buffers into the RxD buffer pointers, so that the NIC
2500 * can DMA the received frame into these locations.
2501 * The NIC supports 3 receive modes, viz
2502 * 1. single buffer,
2503 * 2. three buffer and
2504 * 3. Five buffer modes.
2505 * Each mode defines how many fragments the received frame will be split
2506 * up into by the NIC. The frame is split into L3 header, L4 Header,
2507 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508 * is split into 3 fragments. As of now only single buffer mode is
2509 * supported.
2510 * Return Value:
2511 * SUCCESS on success or an appropriate -ve value on failure.
2512 */
2513 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2514 int from_card_up)
2515 {
2516 struct sk_buff *skb;
2517 struct RxD_t *rxdp;
2518 int off, size, block_no, block_no1;
2519 u32 alloc_tab = 0;
2520 u32 alloc_cnt;
2521 u64 tmp;
2522 struct buffAdd *ba;
2523 struct RxD_t *first_rxdp = NULL;
2524 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2525 int rxd_index = 0;
2526 struct RxD1 *rxdp1;
2527 struct RxD3 *rxdp3;
2528 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2529
2530 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2531
2532 block_no1 = ring->rx_curr_get_info.block_index;
2533 while (alloc_tab < alloc_cnt) {
2534 block_no = ring->rx_curr_put_info.block_index;
2535
2536 off = ring->rx_curr_put_info.offset;
2537
2538 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2539
2540 rxd_index = off + 1;
2541 if (block_no)
2542 rxd_index += (block_no * ring->rxd_count);
2543
2544 if ((block_no == block_no1) &&
2545 (off == ring->rx_curr_get_info.offset) &&
2546 (rxdp->Host_Control)) {
2547 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2548 ring->dev->name);
2549 goto end;
2550 }
2551 if (off && (off == ring->rxd_count)) {
2552 ring->rx_curr_put_info.block_index++;
2553 if (ring->rx_curr_put_info.block_index ==
2554 ring->block_count)
2555 ring->rx_curr_put_info.block_index = 0;
2556 block_no = ring->rx_curr_put_info.block_index;
2557 off = 0;
2558 ring->rx_curr_put_info.offset = off;
2559 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2560 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2561 ring->dev->name, rxdp);
2562
2563 }
2564
2565 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2566 ((ring->rxd_mode == RXD_MODE_3B) &&
2567 (rxdp->Control_2 & s2BIT(0)))) {
2568 ring->rx_curr_put_info.offset = off;
2569 goto end;
2570 }
2571 /* calculate size of skb based on ring mode */
2572 size = ring->mtu +
2573 HEADER_ETHERNET_II_802_3_SIZE +
2574 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2575 if (ring->rxd_mode == RXD_MODE_1)
2576 size += NET_IP_ALIGN;
2577 else
2578 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2579
2580 /* allocate skb */
2581 skb = dev_alloc_skb(size);
2582 if (!skb) {
2583 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2584 ring->dev->name);
2585 if (first_rxdp) {
2586 wmb();
2587 first_rxdp->Control_1 |= RXD_OWN_XENA;
2588 }
2589 swstats->mem_alloc_fail_cnt++;
2590
2591 return -ENOMEM ;
2592 }
2593 swstats->mem_allocated += skb->truesize;
2594
2595 if (ring->rxd_mode == RXD_MODE_1) {
2596 /* 1 buffer mode - normal operation mode */
2597 rxdp1 = (struct RxD1 *)rxdp;
2598 memset(rxdp, 0, sizeof(struct RxD1));
2599 skb_reserve(skb, NET_IP_ALIGN);
2600 rxdp1->Buffer0_ptr =
2601 pci_map_single(ring->pdev, skb->data,
2602 size - NET_IP_ALIGN,
2603 PCI_DMA_FROMDEVICE);
2604 if (pci_dma_mapping_error(nic->pdev,
2605 rxdp1->Buffer0_ptr))
2606 goto pci_map_failed;
2607
2608 rxdp->Control_2 =
2609 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2610 rxdp->Host_Control = (unsigned long)skb;
2611 } else if (ring->rxd_mode == RXD_MODE_3B) {
2612 /*
2613 * 2 buffer mode -
2614 * 2 buffer mode provides 128
2615 * byte aligned receive buffers.
2616 */
2617
2618 rxdp3 = (struct RxD3 *)rxdp;
2619 /* save buffer pointers to avoid frequent dma mapping */
2620 Buffer0_ptr = rxdp3->Buffer0_ptr;
2621 Buffer1_ptr = rxdp3->Buffer1_ptr;
2622 memset(rxdp, 0, sizeof(struct RxD3));
2623 /* restore the buffer pointers for dma sync*/
2624 rxdp3->Buffer0_ptr = Buffer0_ptr;
2625 rxdp3->Buffer1_ptr = Buffer1_ptr;
2626
2627 ba = &ring->ba[block_no][off];
2628 skb_reserve(skb, BUF0_LEN);
2629 tmp = (u64)(unsigned long)skb->data;
2630 tmp += ALIGN_SIZE;
2631 tmp &= ~ALIGN_SIZE;
2632 skb->data = (void *) (unsigned long)tmp;
2633 skb_reset_tail_pointer(skb);
2634
2635 if (from_card_up) {
2636 rxdp3->Buffer0_ptr =
2637 pci_map_single(ring->pdev, ba->ba_0,
2638 BUF0_LEN,
2639 PCI_DMA_FROMDEVICE);
2640 if (pci_dma_mapping_error(nic->pdev,
2641 rxdp3->Buffer0_ptr))
2642 goto pci_map_failed;
2643 } else
2644 pci_dma_sync_single_for_device(ring->pdev,
2645 (dma_addr_t)rxdp3->Buffer0_ptr,
2646 BUF0_LEN,
2647 PCI_DMA_FROMDEVICE);
2648
2649 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2650 if (ring->rxd_mode == RXD_MODE_3B) {
2651 /* Two buffer mode */
2652
2653 /*
2654 * Buffer2 will have L3/L4 header plus
2655 * L4 payload
2656 */
2657 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2658 skb->data,
2659 ring->mtu + 4,
2660 PCI_DMA_FROMDEVICE);
2661
2662 if (pci_dma_mapping_error(nic->pdev,
2663 rxdp3->Buffer2_ptr))
2664 goto pci_map_failed;
2665
2666 if (from_card_up) {
2667 rxdp3->Buffer1_ptr =
2668 pci_map_single(ring->pdev,
2669 ba->ba_1,
2670 BUF1_LEN,
2671 PCI_DMA_FROMDEVICE);
2672
2673 if (pci_dma_mapping_error(nic->pdev,
2674 rxdp3->Buffer1_ptr)) {
2675 pci_unmap_single(ring->pdev,
2676 (dma_addr_t)(unsigned long)
2677 skb->data,
2678 ring->mtu + 4,
2679 PCI_DMA_FROMDEVICE);
2680 goto pci_map_failed;
2681 }
2682 }
2683 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2684 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2685 (ring->mtu + 4);
2686 }
2687 rxdp->Control_2 |= s2BIT(0);
2688 rxdp->Host_Control = (unsigned long) (skb);
2689 }
2690 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2691 rxdp->Control_1 |= RXD_OWN_XENA;
2692 off++;
2693 if (off == (ring->rxd_count + 1))
2694 off = 0;
2695 ring->rx_curr_put_info.offset = off;
2696
2697 rxdp->Control_2 |= SET_RXD_MARKER;
2698 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2699 if (first_rxdp) {
2700 wmb();
2701 first_rxdp->Control_1 |= RXD_OWN_XENA;
2702 }
2703 first_rxdp = rxdp;
2704 }
2705 ring->rx_bufs_left += 1;
2706 alloc_tab++;
2707 }
2708
2709 end:
2710 /* Transfer ownership of first descriptor to adapter just before
2711 * exiting. Before that, use memory barrier so that ownership
2712 * and other fields are seen by adapter correctly.
2713 */
2714 if (first_rxdp) {
2715 wmb();
2716 first_rxdp->Control_1 |= RXD_OWN_XENA;
2717 }
2718
2719 return SUCCESS;
2720
2721 pci_map_failed:
2722 swstats->pci_map_fail_cnt++;
2723 swstats->mem_freed += skb->truesize;
2724 dev_kfree_skb_irq(skb);
2725 return -ENOMEM;
2726 }
2727
2728 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2729 {
2730 struct net_device *dev = sp->dev;
2731 int j;
2732 struct sk_buff *skb;
2733 struct RxD_t *rxdp;
2734 struct buffAdd *ba;
2735 struct RxD1 *rxdp1;
2736 struct RxD3 *rxdp3;
2737 struct mac_info *mac_control = &sp->mac_control;
2738 struct stat_block *stats = mac_control->stats_info;
2739 struct swStat *swstats = &stats->sw_stat;
2740
2741 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2742 rxdp = mac_control->rings[ring_no].
2743 rx_blocks[blk].rxds[j].virt_addr;
2744 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2745 if (!skb)
2746 continue;
2747 if (sp->rxd_mode == RXD_MODE_1) {
2748 rxdp1 = (struct RxD1 *)rxdp;
2749 pci_unmap_single(sp->pdev,
2750 (dma_addr_t)rxdp1->Buffer0_ptr,
2751 dev->mtu +
2752 HEADER_ETHERNET_II_802_3_SIZE +
2753 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2754 PCI_DMA_FROMDEVICE);
2755 memset(rxdp, 0, sizeof(struct RxD1));
2756 } else if (sp->rxd_mode == RXD_MODE_3B) {
2757 rxdp3 = (struct RxD3 *)rxdp;
2758 ba = &mac_control->rings[ring_no].ba[blk][j];
2759 pci_unmap_single(sp->pdev,
2760 (dma_addr_t)rxdp3->Buffer0_ptr,
2761 BUF0_LEN,
2762 PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(sp->pdev,
2764 (dma_addr_t)rxdp3->Buffer1_ptr,
2765 BUF1_LEN,
2766 PCI_DMA_FROMDEVICE);
2767 pci_unmap_single(sp->pdev,
2768 (dma_addr_t)rxdp3->Buffer2_ptr,
2769 dev->mtu + 4,
2770 PCI_DMA_FROMDEVICE);
2771 memset(rxdp, 0, sizeof(struct RxD3));
2772 }
2773 swstats->mem_freed += skb->truesize;
2774 dev_kfree_skb(skb);
2775 mac_control->rings[ring_no].rx_bufs_left -= 1;
2776 }
2777 }
2778
2779 /**
2780 * free_rx_buffers - Frees all Rx buffers
2781 * @sp: device private variable.
2782 * Description:
2783 * This function will free all Rx buffers allocated by host.
2784 * Return Value:
2785 * NONE.
2786 */
2787
2788 static void free_rx_buffers(struct s2io_nic *sp)
2789 {
2790 struct net_device *dev = sp->dev;
2791 int i, blk = 0, buf_cnt = 0;
2792 struct config_param *config = &sp->config;
2793 struct mac_info *mac_control = &sp->mac_control;
2794
2795 for (i = 0; i < config->rx_ring_num; i++) {
2796 struct ring_info *ring = &mac_control->rings[i];
2797
2798 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2799 free_rxd_blk(sp, i, blk);
2800
2801 ring->rx_curr_put_info.block_index = 0;
2802 ring->rx_curr_get_info.block_index = 0;
2803 ring->rx_curr_put_info.offset = 0;
2804 ring->rx_curr_get_info.offset = 0;
2805 ring->rx_bufs_left = 0;
2806 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2807 dev->name, buf_cnt, i);
2808 }
2809 }
2810
2811 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2812 {
2813 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2814 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2815 ring->dev->name);
2816 }
2817 return 0;
2818 }
2819
2820 /**
2821 * s2io_poll - Rx interrupt handler for NAPI support
2822 * @napi : pointer to the napi structure.
2823 * @budget : The number of packets that were budgeted to be processed
2824 * during one pass through the 'Poll" function.
2825 * Description:
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2829 * Return value:
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2831 */
2832
2833 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2834 {
2835 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836 struct net_device *dev = ring->dev;
2837 int pkts_processed = 0;
2838 u8 __iomem *addr = NULL;
2839 u8 val8 = 0;
2840 struct s2io_nic *nic = netdev_priv(dev);
2841 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2842 int budget_org = budget;
2843
2844 if (unlikely(!is_s2io_card_up(nic)))
2845 return 0;
2846
2847 pkts_processed = rx_intr_handler(ring, budget);
2848 s2io_chk_rx_buffers(nic, ring);
2849
2850 if (pkts_processed < budget_org) {
2851 napi_complete(napi);
2852 /*Re Enable MSI-Rx Vector*/
2853 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2854 addr += 7 - ring->ring_no;
2855 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2856 writeb(val8, addr);
2857 val8 = readb(addr);
2858 }
2859 return pkts_processed;
2860 }
2861
2862 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2863 {
2864 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2865 int pkts_processed = 0;
2866 int ring_pkts_processed, i;
2867 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2868 int budget_org = budget;
2869 struct config_param *config = &nic->config;
2870 struct mac_info *mac_control = &nic->mac_control;
2871
2872 if (unlikely(!is_s2io_card_up(nic)))
2873 return 0;
2874
2875 for (i = 0; i < config->rx_ring_num; i++) {
2876 struct ring_info *ring = &mac_control->rings[i];
2877 ring_pkts_processed = rx_intr_handler(ring, budget);
2878 s2io_chk_rx_buffers(nic, ring);
2879 pkts_processed += ring_pkts_processed;
2880 budget -= ring_pkts_processed;
2881 if (budget <= 0)
2882 break;
2883 }
2884 if (pkts_processed < budget_org) {
2885 napi_complete(napi);
2886 /* Re enable the Rx interrupts for the ring */
2887 writeq(0, &bar0->rx_traffic_mask);
2888 readl(&bar0->rx_traffic_mask);
2889 }
2890 return pkts_processed;
2891 }
2892
2893 #ifdef CONFIG_NET_POLL_CONTROLLER
2894 /**
2895 * s2io_netpoll - netpoll event handler entry point
2896 * @dev : pointer to the device structure.
2897 * Description:
2898 * This function will be called by upper layer to check for events on the
2899 * interface in situations where interrupts are disabled. It is used for
2900 * specific in-kernel networking tasks, such as remote consoles and kernel
2901 * debugging over the network (example netdump in RedHat).
2902 */
2903 static void s2io_netpoll(struct net_device *dev)
2904 {
2905 struct s2io_nic *nic = netdev_priv(dev);
2906 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2907 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2908 int i;
2909 struct config_param *config = &nic->config;
2910 struct mac_info *mac_control = &nic->mac_control;
2911
2912 if (pci_channel_offline(nic->pdev))
2913 return;
2914
2915 disable_irq(dev->irq);
2916
2917 writeq(val64, &bar0->rx_traffic_int);
2918 writeq(val64, &bar0->tx_traffic_int);
2919
2920 /* we need to free up the transmitted skbufs or else netpoll will
2921 * run out of skbs and will fail and eventually netpoll application such
2922 * as netdump will fail.
2923 */
2924 for (i = 0; i < config->tx_fifo_num; i++)
2925 tx_intr_handler(&mac_control->fifos[i]);
2926
2927 /* check for received packet and indicate up to network */
2928 for (i = 0; i < config->rx_ring_num; i++) {
2929 struct ring_info *ring = &mac_control->rings[i];
2930
2931 rx_intr_handler(ring, 0);
2932 }
2933
2934 for (i = 0; i < config->rx_ring_num; i++) {
2935 struct ring_info *ring = &mac_control->rings[i];
2936
2937 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2938 DBG_PRINT(INFO_DBG,
2939 "%s: Out of memory in Rx Netpoll!!\n",
2940 dev->name);
2941 break;
2942 }
2943 }
2944 enable_irq(dev->irq);
2945 return;
2946 }
2947 #endif
2948
2949 /**
2950 * rx_intr_handler - Rx interrupt handler
2951 * @ring_info: per ring structure.
2952 * @budget: budget for napi processing.
2953 * Description:
2954 * If the interrupt is because of a received frame or if the
2955 * receive ring contains fresh as yet un-processed frames,this function is
2956 * called. It picks out the RxD at which place the last Rx processing had
2957 * stopped and sends the skb to the OSM's Rx handler and then increments
2958 * the offset.
2959 * Return Value:
2960 * No. of napi packets processed.
2961 */
2962 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2963 {
2964 int get_block, put_block;
2965 struct rx_curr_get_info get_info, put_info;
2966 struct RxD_t *rxdp;
2967 struct sk_buff *skb;
2968 int pkt_cnt = 0, napi_pkts = 0;
2969 int i;
2970 struct RxD1 *rxdp1;
2971 struct RxD3 *rxdp3;
2972
2973 get_info = ring_data->rx_curr_get_info;
2974 get_block = get_info.block_index;
2975 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2976 put_block = put_info.block_index;
2977 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2978
2979 while (RXD_IS_UP2DT(rxdp)) {
2980 /*
2981 * If your are next to put index then it's
2982 * FIFO full condition
2983 */
2984 if ((get_block == put_block) &&
2985 (get_info.offset + 1) == put_info.offset) {
2986 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2987 ring_data->dev->name);
2988 break;
2989 }
2990 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2991 if (skb == NULL) {
2992 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2993 ring_data->dev->name);
2994 return 0;
2995 }
2996 if (ring_data->rxd_mode == RXD_MODE_1) {
2997 rxdp1 = (struct RxD1 *)rxdp;
2998 pci_unmap_single(ring_data->pdev, (dma_addr_t)
2999 rxdp1->Buffer0_ptr,
3000 ring_data->mtu +
3001 HEADER_ETHERNET_II_802_3_SIZE +
3002 HEADER_802_2_SIZE +
3003 HEADER_SNAP_SIZE,
3004 PCI_DMA_FROMDEVICE);
3005 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3006 rxdp3 = (struct RxD3 *)rxdp;
3007 pci_dma_sync_single_for_cpu(ring_data->pdev,
3008 (dma_addr_t)rxdp3->Buffer0_ptr,
3009 BUF0_LEN,
3010 PCI_DMA_FROMDEVICE);
3011 pci_unmap_single(ring_data->pdev,
3012 (dma_addr_t)rxdp3->Buffer2_ptr,
3013 ring_data->mtu + 4,
3014 PCI_DMA_FROMDEVICE);
3015 }
3016 prefetch(skb->data);
3017 rx_osm_handler(ring_data, rxdp);
3018 get_info.offset++;
3019 ring_data->rx_curr_get_info.offset = get_info.offset;
3020 rxdp = ring_data->rx_blocks[get_block].
3021 rxds[get_info.offset].virt_addr;
3022 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3023 get_info.offset = 0;
3024 ring_data->rx_curr_get_info.offset = get_info.offset;
3025 get_block++;
3026 if (get_block == ring_data->block_count)
3027 get_block = 0;
3028 ring_data->rx_curr_get_info.block_index = get_block;
3029 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3030 }
3031
3032 if (ring_data->nic->config.napi) {
3033 budget--;
3034 napi_pkts++;
3035 if (!budget)
3036 break;
3037 }
3038 pkt_cnt++;
3039 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3040 break;
3041 }
3042 if (ring_data->lro) {
3043 /* Clear all LRO sessions before exiting */
3044 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3045 struct lro *lro = &ring_data->lro0_n[i];
3046 if (lro->in_use) {
3047 update_L3L4_header(ring_data->nic, lro);
3048 queue_rx_frame(lro->parent, lro->vlan_tag);
3049 clear_lro_session(lro);
3050 }
3051 }
3052 }
3053 return napi_pkts;
3054 }
3055
3056 /**
3057 * tx_intr_handler - Transmit interrupt handler
3058 * @nic : device private variable
3059 * Description:
3060 * If an interrupt was raised to indicate DMA complete of the
3061 * Tx packet, this function is called. It identifies the last TxD
3062 * whose buffer was freed and frees all skbs whose data have already
3063 * DMA'ed into the NICs internal memory.
3064 * Return Value:
3065 * NONE
3066 */
3067
3068 static void tx_intr_handler(struct fifo_info *fifo_data)
3069 {
3070 struct s2io_nic *nic = fifo_data->nic;
3071 struct tx_curr_get_info get_info, put_info;
3072 struct sk_buff *skb = NULL;
3073 struct TxD *txdlp;
3074 int pkt_cnt = 0;
3075 unsigned long flags = 0;
3076 u8 err_mask;
3077 struct stat_block *stats = nic->mac_control.stats_info;
3078 struct swStat *swstats = &stats->sw_stat;
3079
3080 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3081 return;
3082
3083 get_info = fifo_data->tx_curr_get_info;
3084 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3085 txdlp = (struct TxD *)
3086 fifo_data->list_info[get_info.offset].list_virt_addr;
3087 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3088 (get_info.offset != put_info.offset) &&
3089 (txdlp->Host_Control)) {
3090 /* Check for TxD errors */
3091 if (txdlp->Control_1 & TXD_T_CODE) {
3092 unsigned long long err;
3093 err = txdlp->Control_1 & TXD_T_CODE;
3094 if (err & 0x1) {
3095 swstats->parity_err_cnt++;
3096 }
3097
3098 /* update t_code statistics */
3099 err_mask = err >> 48;
3100 switch (err_mask) {
3101 case 2:
3102 swstats->tx_buf_abort_cnt++;
3103 break;
3104
3105 case 3:
3106 swstats->tx_desc_abort_cnt++;
3107 break;
3108
3109 case 7:
3110 swstats->tx_parity_err_cnt++;
3111 break;
3112
3113 case 10:
3114 swstats->tx_link_loss_cnt++;
3115 break;
3116
3117 case 15:
3118 swstats->tx_list_proc_err_cnt++;
3119 break;
3120 }
3121 }
3122
3123 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3124 if (skb == NULL) {
3125 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3126 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3127 __func__);
3128 return;
3129 }
3130 pkt_cnt++;
3131
3132 /* Updating the statistics block */
3133 nic->dev->stats.tx_bytes += skb->len;
3134 swstats->mem_freed += skb->truesize;
3135 dev_kfree_skb_irq(skb);
3136
3137 get_info.offset++;
3138 if (get_info.offset == get_info.fifo_len + 1)
3139 get_info.offset = 0;
3140 txdlp = (struct TxD *)
3141 fifo_data->list_info[get_info.offset].list_virt_addr;
3142 fifo_data->tx_curr_get_info.offset = get_info.offset;
3143 }
3144
3145 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3146
3147 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3148 }
3149
3150 /**
3151 * s2io_mdio_write - Function to write in to MDIO registers
3152 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3153 * @addr : address value
3154 * @value : data value
3155 * @dev : pointer to net_device structure
3156 * Description:
3157 * This function is used to write values to the MDIO registers
3158 * NONE
3159 */
3160 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3161 struct net_device *dev)
3162 {
3163 u64 val64;
3164 struct s2io_nic *sp = netdev_priv(dev);
3165 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3166
3167 /* address transaction */
3168 val64 = MDIO_MMD_INDX_ADDR(addr) |
3169 MDIO_MMD_DEV_ADDR(mmd_type) |
3170 MDIO_MMS_PRT_ADDR(0x0);
3171 writeq(val64, &bar0->mdio_control);
3172 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3173 writeq(val64, &bar0->mdio_control);
3174 udelay(100);
3175
3176 /* Data transaction */
3177 val64 = MDIO_MMD_INDX_ADDR(addr) |
3178 MDIO_MMD_DEV_ADDR(mmd_type) |
3179 MDIO_MMS_PRT_ADDR(0x0) |
3180 MDIO_MDIO_DATA(value) |
3181 MDIO_OP(MDIO_OP_WRITE_TRANS);
3182 writeq(val64, &bar0->mdio_control);
3183 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3184 writeq(val64, &bar0->mdio_control);
3185 udelay(100);
3186
3187 val64 = MDIO_MMD_INDX_ADDR(addr) |
3188 MDIO_MMD_DEV_ADDR(mmd_type) |
3189 MDIO_MMS_PRT_ADDR(0x0) |
3190 MDIO_OP(MDIO_OP_READ_TRANS);
3191 writeq(val64, &bar0->mdio_control);
3192 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3193 writeq(val64, &bar0->mdio_control);
3194 udelay(100);
3195 }
3196
3197 /**
3198 * s2io_mdio_read - Function to write in to MDIO registers
3199 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3200 * @addr : address value
3201 * @dev : pointer to net_device structure
3202 * Description:
3203 * This function is used to read values to the MDIO registers
3204 * NONE
3205 */
3206 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3207 {
3208 u64 val64 = 0x0;
3209 u64 rval64 = 0x0;
3210 struct s2io_nic *sp = netdev_priv(dev);
3211 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3212
3213 /* address transaction */
3214 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3215 | MDIO_MMD_DEV_ADDR(mmd_type)
3216 | MDIO_MMS_PRT_ADDR(0x0));
3217 writeq(val64, &bar0->mdio_control);
3218 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3219 writeq(val64, &bar0->mdio_control);
3220 udelay(100);
3221
3222 /* Data transaction */
3223 val64 = MDIO_MMD_INDX_ADDR(addr) |
3224 MDIO_MMD_DEV_ADDR(mmd_type) |
3225 MDIO_MMS_PRT_ADDR(0x0) |
3226 MDIO_OP(MDIO_OP_READ_TRANS);
3227 writeq(val64, &bar0->mdio_control);
3228 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3229 writeq(val64, &bar0->mdio_control);
3230 udelay(100);
3231
3232 /* Read the value from regs */
3233 rval64 = readq(&bar0->mdio_control);
3234 rval64 = rval64 & 0xFFFF0000;
3235 rval64 = rval64 >> 16;
3236 return rval64;
3237 }
3238
3239 /**
3240 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3241 * @counter : couter value to be updated
3242 * @flag : flag to indicate the status
3243 * @type : counter type
3244 * Description:
3245 * This function is to check the status of the xpak counters value
3246 * NONE
3247 */
3248
3249 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3250 u16 flag, u16 type)
3251 {
3252 u64 mask = 0x3;
3253 u64 val64;
3254 int i;
3255 for (i = 0; i < index; i++)
3256 mask = mask << 0x2;
3257
3258 if (flag > 0) {
3259 *counter = *counter + 1;
3260 val64 = *regs_stat & mask;
3261 val64 = val64 >> (index * 0x2);
3262 val64 = val64 + 1;
3263 if (val64 == 3) {
3264 switch (type) {
3265 case 1:
3266 DBG_PRINT(ERR_DBG,
3267 "Take Xframe NIC out of service.\n");
3268 DBG_PRINT(ERR_DBG,
3269 "Excessive temperatures may result in premature transceiver failure.\n");
3270 break;
3271 case 2:
3272 DBG_PRINT(ERR_DBG,
3273 "Take Xframe NIC out of service.\n");
3274 DBG_PRINT(ERR_DBG,
3275 "Excessive bias currents may indicate imminent laser diode failure.\n");
3276 break;
3277 case 3:
3278 DBG_PRINT(ERR_DBG,
3279 "Take Xframe NIC out of service.\n");
3280 DBG_PRINT(ERR_DBG,
3281 "Excessive laser output power may saturate far-end receiver.\n");
3282 break;
3283 default:
3284 DBG_PRINT(ERR_DBG,
3285 "Incorrect XPAK Alarm type\n");
3286 }
3287 val64 = 0x0;
3288 }
3289 val64 = val64 << (index * 0x2);
3290 *regs_stat = (*regs_stat & (~mask)) | (val64);
3291
3292 } else {
3293 *regs_stat = *regs_stat & (~mask);
3294 }
3295 }
3296
3297 /**
3298 * s2io_updt_xpak_counter - Function to update the xpak counters
3299 * @dev : pointer to net_device struct
3300 * Description:
3301 * This function is to upate the status of the xpak counters value
3302 * NONE
3303 */
3304 static void s2io_updt_xpak_counter(struct net_device *dev)
3305 {
3306 u16 flag = 0x0;
3307 u16 type = 0x0;
3308 u16 val16 = 0x0;
3309 u64 val64 = 0x0;
3310 u64 addr = 0x0;
3311
3312 struct s2io_nic *sp = netdev_priv(dev);
3313 struct stat_block *stats = sp->mac_control.stats_info;
3314 struct xpakStat *xstats = &stats->xpak_stat;
3315
3316 /* Check the communication with the MDIO slave */
3317 addr = MDIO_CTRL1;
3318 val64 = 0x0;
3319 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3320 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3321 DBG_PRINT(ERR_DBG,
3322 "ERR: MDIO slave access failed - Returned %llx\n",
3323 (unsigned long long)val64);
3324 return;
3325 }
3326
3327 /* Check for the expected value of control reg 1 */
3328 if (val64 != MDIO_CTRL1_SPEED10G) {
3329 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3330 "Returned: %llx- Expected: 0x%x\n",
3331 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3332 return;
3333 }
3334
3335 /* Loading the DOM register to MDIO register */
3336 addr = 0xA100;
3337 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3338 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3339
3340 /* Reading the Alarm flags */
3341 addr = 0xA070;
3342 val64 = 0x0;
3343 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3344
3345 flag = CHECKBIT(val64, 0x7);
3346 type = 1;
3347 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3348 &xstats->xpak_regs_stat,
3349 0x0, flag, type);
3350
3351 if (CHECKBIT(val64, 0x6))
3352 xstats->alarm_transceiver_temp_low++;
3353
3354 flag = CHECKBIT(val64, 0x3);
3355 type = 2;
3356 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3357 &xstats->xpak_regs_stat,
3358 0x2, flag, type);
3359
3360 if (CHECKBIT(val64, 0x2))
3361 xstats->alarm_laser_bias_current_low++;
3362
3363 flag = CHECKBIT(val64, 0x1);
3364 type = 3;
3365 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3366 &xstats->xpak_regs_stat,
3367 0x4, flag, type);
3368
3369 if (CHECKBIT(val64, 0x0))
3370 xstats->alarm_laser_output_power_low++;
3371
3372 /* Reading the Warning flags */
3373 addr = 0xA074;
3374 val64 = 0x0;
3375 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3376
3377 if (CHECKBIT(val64, 0x7))
3378 xstats->warn_transceiver_temp_high++;
3379
3380 if (CHECKBIT(val64, 0x6))
3381 xstats->warn_transceiver_temp_low++;
3382
3383 if (CHECKBIT(val64, 0x3))
3384 xstats->warn_laser_bias_current_high++;
3385
3386 if (CHECKBIT(val64, 0x2))
3387 xstats->warn_laser_bias_current_low++;
3388
3389 if (CHECKBIT(val64, 0x1))
3390 xstats->warn_laser_output_power_high++;
3391
3392 if (CHECKBIT(val64, 0x0))
3393 xstats->warn_laser_output_power_low++;
3394 }
3395
3396 /**
3397 * wait_for_cmd_complete - waits for a command to complete.
3398 * @sp : private member of the device structure, which is a pointer to the
3399 * s2io_nic structure.
3400 * Description: Function that waits for a command to Write into RMAC
3401 * ADDR DATA registers to be completed and returns either success or
3402 * error depending on whether the command was complete or not.
3403 * Return value:
3404 * SUCCESS on success and FAILURE on failure.
3405 */
3406
3407 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3408 int bit_state)
3409 {
3410 int ret = FAILURE, cnt = 0, delay = 1;
3411 u64 val64;
3412
3413 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3414 return FAILURE;
3415
3416 do {
3417 val64 = readq(addr);
3418 if (bit_state == S2IO_BIT_RESET) {
3419 if (!(val64 & busy_bit)) {
3420 ret = SUCCESS;
3421 break;
3422 }
3423 } else {
3424 if (!(val64 & busy_bit)) {
3425 ret = SUCCESS;
3426 break;
3427 }
3428 }
3429
3430 if (in_interrupt())
3431 mdelay(delay);
3432 else
3433 msleep(delay);
3434
3435 if (++cnt >= 10)
3436 delay = 50;
3437 } while (cnt < 20);
3438 return ret;
3439 }
3440 /*
3441 * check_pci_device_id - Checks if the device id is supported
3442 * @id : device id
3443 * Description: Function to check if the pci device id is supported by driver.
3444 * Return value: Actual device id if supported else PCI_ANY_ID
3445 */
3446 static u16 check_pci_device_id(u16 id)
3447 {
3448 switch (id) {
3449 case PCI_DEVICE_ID_HERC_WIN:
3450 case PCI_DEVICE_ID_HERC_UNI:
3451 return XFRAME_II_DEVICE;
3452 case PCI_DEVICE_ID_S2IO_UNI:
3453 case PCI_DEVICE_ID_S2IO_WIN:
3454 return XFRAME_I_DEVICE;
3455 default:
3456 return PCI_ANY_ID;
3457 }
3458 }
3459
3460 /**
3461 * s2io_reset - Resets the card.
3462 * @sp : private member of the device structure.
3463 * Description: Function to Reset the card. This function then also
3464 * restores the previously saved PCI configuration space registers as
3465 * the card reset also resets the configuration space.
3466 * Return value:
3467 * void.
3468 */
3469
3470 static void s2io_reset(struct s2io_nic *sp)
3471 {
3472 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3473 u64 val64;
3474 u16 subid, pci_cmd;
3475 int i;
3476 u16 val16;
3477 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3478 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3479 struct stat_block *stats;
3480 struct swStat *swstats;
3481
3482 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3483 __func__, sp->dev->name);
3484
3485 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3486 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3487
3488 val64 = SW_RESET_ALL;
3489 writeq(val64, &bar0->sw_reset);
3490 if (strstr(sp->product_name, "CX4"))
3491 msleep(750);
3492 msleep(250);
3493 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3494
3495 /* Restore the PCI state saved during initialization. */
3496 pci_restore_state(sp->pdev);
3497 pci_read_config_word(sp->pdev, 0x2, &val16);
3498 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3499 break;
3500 msleep(200);
3501 }
3502
3503 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3504 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3505
3506 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3507
3508 s2io_init_pci(sp);
3509
3510 /* Set swapper to enable I/O register access */
3511 s2io_set_swapper(sp);
3512
3513 /* restore mac_addr entries */
3514 do_s2io_restore_unicast_mc(sp);
3515
3516 /* Restore the MSIX table entries from local variables */
3517 restore_xmsi_data(sp);
3518
3519 /* Clear certain PCI/PCI-X fields after reset */
3520 if (sp->device_type == XFRAME_II_DEVICE) {
3521 /* Clear "detected parity error" bit */
3522 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3523
3524 /* Clearing PCIX Ecc status register */
3525 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3526
3527 /* Clearing PCI_STATUS error reflected here */
3528 writeq(s2BIT(62), &bar0->txpic_int_reg);
3529 }
3530
3531 /* Reset device statistics maintained by OS */
3532 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3533
3534 stats = sp->mac_control.stats_info;
3535 swstats = &stats->sw_stat;
3536
3537 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3538 up_cnt = swstats->link_up_cnt;
3539 down_cnt = swstats->link_down_cnt;
3540 up_time = swstats->link_up_time;
3541 down_time = swstats->link_down_time;
3542 reset_cnt = swstats->soft_reset_cnt;
3543 mem_alloc_cnt = swstats->mem_allocated;
3544 mem_free_cnt = swstats->mem_freed;
3545 watchdog_cnt = swstats->watchdog_timer_cnt;
3546
3547 memset(stats, 0, sizeof(struct stat_block));
3548
3549 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3550 swstats->link_up_cnt = up_cnt;
3551 swstats->link_down_cnt = down_cnt;
3552 swstats->link_up_time = up_time;
3553 swstats->link_down_time = down_time;
3554 swstats->soft_reset_cnt = reset_cnt;
3555 swstats->mem_allocated = mem_alloc_cnt;
3556 swstats->mem_freed = mem_free_cnt;
3557 swstats->watchdog_timer_cnt = watchdog_cnt;
3558
3559 /* SXE-002: Configure link and activity LED to turn it off */
3560 subid = sp->pdev->subsystem_device;
3561 if (((subid & 0xFF) >= 0x07) &&
3562 (sp->device_type == XFRAME_I_DEVICE)) {
3563 val64 = readq(&bar0->gpio_control);
3564 val64 |= 0x0000800000000000ULL;
3565 writeq(val64, &bar0->gpio_control);
3566 val64 = 0x0411040400000000ULL;
3567 writeq(val64, (void __iomem *)bar0 + 0x2700);
3568 }
3569
3570 /*
3571 * Clear spurious ECC interrupts that would have occured on
3572 * XFRAME II cards after reset.
3573 */
3574 if (sp->device_type == XFRAME_II_DEVICE) {
3575 val64 = readq(&bar0->pcc_err_reg);
3576 writeq(val64, &bar0->pcc_err_reg);
3577 }
3578
3579 sp->device_enabled_once = false;
3580 }
3581
3582 /**
3583 * s2io_set_swapper - to set the swapper controle on the card
3584 * @sp : private member of the device structure,
3585 * pointer to the s2io_nic structure.
3586 * Description: Function to set the swapper control on the card
3587 * correctly depending on the 'endianness' of the system.
3588 * Return value:
3589 * SUCCESS on success and FAILURE on failure.
3590 */
3591
3592 static int s2io_set_swapper(struct s2io_nic *sp)
3593 {
3594 struct net_device *dev = sp->dev;
3595 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3596 u64 val64, valt, valr;
3597
3598 /*
3599 * Set proper endian settings and verify the same by reading
3600 * the PIF Feed-back register.
3601 */
3602
3603 val64 = readq(&bar0->pif_rd_swapper_fb);
3604 if (val64 != 0x0123456789ABCDEFULL) {
3605 int i = 0;
3606 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3607 0x8100008181000081ULL, /* FE=1, SE=0 */
3608 0x4200004242000042ULL, /* FE=0, SE=1 */
3609 0}; /* FE=0, SE=0 */
3610
3611 while (i < 4) {
3612 writeq(value[i], &bar0->swapper_ctrl);
3613 val64 = readq(&bar0->pif_rd_swapper_fb);
3614 if (val64 == 0x0123456789ABCDEFULL)
3615 break;
3616 i++;
3617 }
3618 if (i == 4) {
3619 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3620 "feedback read %llx\n",
3621 dev->name, (unsigned long long)val64);
3622 return FAILURE;
3623 }
3624 valr = value[i];
3625 } else {
3626 valr = readq(&bar0->swapper_ctrl);
3627 }
3628
3629 valt = 0x0123456789ABCDEFULL;
3630 writeq(valt, &bar0->xmsi_address);
3631 val64 = readq(&bar0->xmsi_address);
3632
3633 if (val64 != valt) {
3634 int i = 0;
3635 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3636 0x0081810000818100ULL, /* FE=1, SE=0 */
3637 0x0042420000424200ULL, /* FE=0, SE=1 */
3638 0}; /* FE=0, SE=0 */
3639
3640 while (i < 4) {
3641 writeq((value[i] | valr), &bar0->swapper_ctrl);
3642 writeq(valt, &bar0->xmsi_address);
3643 val64 = readq(&bar0->xmsi_address);
3644 if (val64 == valt)
3645 break;
3646 i++;
3647 }
3648 if (i == 4) {
3649 unsigned long long x = val64;
3650 DBG_PRINT(ERR_DBG,
3651 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3652 return FAILURE;
3653 }
3654 }
3655 val64 = readq(&bar0->swapper_ctrl);
3656 val64 &= 0xFFFF000000000000ULL;
3657
3658 #ifdef __BIG_ENDIAN
3659 /*
3660 * The device by default set to a big endian format, so a
3661 * big endian driver need not set anything.
3662 */
3663 val64 |= (SWAPPER_CTRL_TXP_FE |
3664 SWAPPER_CTRL_TXP_SE |
3665 SWAPPER_CTRL_TXD_R_FE |
3666 SWAPPER_CTRL_TXD_W_FE |
3667 SWAPPER_CTRL_TXF_R_FE |
3668 SWAPPER_CTRL_RXD_R_FE |
3669 SWAPPER_CTRL_RXD_W_FE |
3670 SWAPPER_CTRL_RXF_W_FE |
3671 SWAPPER_CTRL_XMSI_FE |
3672 SWAPPER_CTRL_STATS_FE |
3673 SWAPPER_CTRL_STATS_SE);
3674 if (sp->config.intr_type == INTA)
3675 val64 |= SWAPPER_CTRL_XMSI_SE;
3676 writeq(val64, &bar0->swapper_ctrl);
3677 #else
3678 /*
3679 * Initially we enable all bits to make it accessible by the
3680 * driver, then we selectively enable only those bits that
3681 * we want to set.
3682 */
3683 val64 |= (SWAPPER_CTRL_TXP_FE |
3684 SWAPPER_CTRL_TXP_SE |
3685 SWAPPER_CTRL_TXD_R_FE |
3686 SWAPPER_CTRL_TXD_R_SE |
3687 SWAPPER_CTRL_TXD_W_FE |
3688 SWAPPER_CTRL_TXD_W_SE |
3689 SWAPPER_CTRL_TXF_R_FE |
3690 SWAPPER_CTRL_RXD_R_FE |
3691 SWAPPER_CTRL_RXD_R_SE |
3692 SWAPPER_CTRL_RXD_W_FE |
3693 SWAPPER_CTRL_RXD_W_SE |
3694 SWAPPER_CTRL_RXF_W_FE |
3695 SWAPPER_CTRL_XMSI_FE |
3696 SWAPPER_CTRL_STATS_FE |
3697 SWAPPER_CTRL_STATS_SE);
3698 if (sp->config.intr_type == INTA)
3699 val64 |= SWAPPER_CTRL_XMSI_SE;
3700 writeq(val64, &bar0->swapper_ctrl);
3701 #endif
3702 val64 = readq(&bar0->swapper_ctrl);
3703
3704 /*
3705 * Verifying if endian settings are accurate by reading a
3706 * feedback register.
3707 */
3708 val64 = readq(&bar0->pif_rd_swapper_fb);
3709 if (val64 != 0x0123456789ABCDEFULL) {
3710 /* Endian settings are incorrect, calls for another dekko. */
3711 DBG_PRINT(ERR_DBG,
3712 "%s: Endian settings are wrong, feedback read %llx\n",
3713 dev->name, (unsigned long long)val64);
3714 return FAILURE;
3715 }
3716
3717 return SUCCESS;
3718 }
3719
3720 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3721 {
3722 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3723 u64 val64;
3724 int ret = 0, cnt = 0;
3725
3726 do {
3727 val64 = readq(&bar0->xmsi_access);
3728 if (!(val64 & s2BIT(15)))
3729 break;
3730 mdelay(1);
3731 cnt++;
3732 } while (cnt < 5);
3733 if (cnt == 5) {
3734 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3735 ret = 1;
3736 }
3737
3738 return ret;
3739 }
3740
3741 static void restore_xmsi_data(struct s2io_nic *nic)
3742 {
3743 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3744 u64 val64;
3745 int i, msix_index;
3746
3747 if (nic->device_type == XFRAME_I_DEVICE)
3748 return;
3749
3750 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3751 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3752 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3753 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3754 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3755 writeq(val64, &bar0->xmsi_access);
3756 if (wait_for_msix_trans(nic, msix_index)) {
3757 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3758 __func__, msix_index);
3759 continue;
3760 }
3761 }
3762 }
3763
3764 static void store_xmsi_data(struct s2io_nic *nic)
3765 {
3766 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3767 u64 val64, addr, data;
3768 int i, msix_index;
3769
3770 if (nic->device_type == XFRAME_I_DEVICE)
3771 return;
3772
3773 /* Store and display */
3774 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3775 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3776 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3777 writeq(val64, &bar0->xmsi_access);
3778 if (wait_for_msix_trans(nic, msix_index)) {
3779 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3780 __func__, msix_index);
3781 continue;
3782 }
3783 addr = readq(&bar0->xmsi_address);
3784 data = readq(&bar0->xmsi_data);
3785 if (addr && data) {
3786 nic->msix_info[i].addr = addr;
3787 nic->msix_info[i].data = data;
3788 }
3789 }
3790 }
3791
3792 static int s2io_enable_msi_x(struct s2io_nic *nic)
3793 {
3794 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3795 u64 rx_mat;
3796 u16 msi_control; /* Temp variable */
3797 int ret, i, j, msix_indx = 1;
3798 int size;
3799 struct stat_block *stats = nic->mac_control.stats_info;
3800 struct swStat *swstats = &stats->sw_stat;
3801
3802 size = nic->num_entries * sizeof(struct msix_entry);
3803 nic->entries = kzalloc(size, GFP_KERNEL);
3804 if (!nic->entries) {
3805 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3806 __func__);
3807 swstats->mem_alloc_fail_cnt++;
3808 return -ENOMEM;
3809 }
3810 swstats->mem_allocated += size;
3811
3812 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3813 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3814 if (!nic->s2io_entries) {
3815 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3816 __func__);
3817 swstats->mem_alloc_fail_cnt++;
3818 kfree(nic->entries);
3819 swstats->mem_freed
3820 += (nic->num_entries * sizeof(struct msix_entry));
3821 return -ENOMEM;
3822 }
3823 swstats->mem_allocated += size;
3824
3825 nic->entries[0].entry = 0;
3826 nic->s2io_entries[0].entry = 0;
3827 nic->s2io_entries[0].in_use = MSIX_FLG;
3828 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3829 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3830
3831 for (i = 1; i < nic->num_entries; i++) {
3832 nic->entries[i].entry = ((i - 1) * 8) + 1;
3833 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3834 nic->s2io_entries[i].arg = NULL;
3835 nic->s2io_entries[i].in_use = 0;
3836 }
3837
3838 rx_mat = readq(&bar0->rx_mat);
3839 for (j = 0; j < nic->config.rx_ring_num; j++) {
3840 rx_mat |= RX_MAT_SET(j, msix_indx);
3841 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3842 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3843 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3844 msix_indx += 8;
3845 }
3846 writeq(rx_mat, &bar0->rx_mat);
3847 readq(&bar0->rx_mat);
3848
3849 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3850 /* We fail init if error or we get less vectors than min required */
3851 if (ret) {
3852 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3853 kfree(nic->entries);
3854 swstats->mem_freed += nic->num_entries *
3855 sizeof(struct msix_entry);
3856 kfree(nic->s2io_entries);
3857 swstats->mem_freed += nic->num_entries *
3858 sizeof(struct s2io_msix_entry);
3859 nic->entries = NULL;
3860 nic->s2io_entries = NULL;
3861 return -ENOMEM;
3862 }
3863
3864 /*
3865 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3866 * in the herc NIC. (Temp change, needs to be removed later)
3867 */
3868 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3869 msi_control |= 0x1; /* Enable MSI */
3870 pci_write_config_word(nic->pdev, 0x42, msi_control);
3871
3872 return 0;
3873 }
3874
3875 /* Handle software interrupt used during MSI(X) test */
3876 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3877 {
3878 struct s2io_nic *sp = dev_id;
3879
3880 sp->msi_detected = 1;
3881 wake_up(&sp->msi_wait);
3882
3883 return IRQ_HANDLED;
3884 }
3885
3886 /* Test interrupt path by forcing a a software IRQ */
3887 static int s2io_test_msi(struct s2io_nic *sp)
3888 {
3889 struct pci_dev *pdev = sp->pdev;
3890 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3891 int err;
3892 u64 val64, saved64;
3893
3894 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3895 sp->name, sp);
3896 if (err) {
3897 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3898 sp->dev->name, pci_name(pdev), pdev->irq);
3899 return err;
3900 }
3901
3902 init_waitqueue_head(&sp->msi_wait);
3903 sp->msi_detected = 0;
3904
3905 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3906 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3907 val64 |= SCHED_INT_CTRL_TIMER_EN;
3908 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3909 writeq(val64, &bar0->scheduled_int_ctrl);
3910
3911 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3912
3913 if (!sp->msi_detected) {
3914 /* MSI(X) test failed, go back to INTx mode */
3915 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3916 "using MSI(X) during test\n",
3917 sp->dev->name, pci_name(pdev));
3918
3919 err = -EOPNOTSUPP;
3920 }
3921
3922 free_irq(sp->entries[1].vector, sp);
3923
3924 writeq(saved64, &bar0->scheduled_int_ctrl);
3925
3926 return err;
3927 }
3928
3929 static void remove_msix_isr(struct s2io_nic *sp)
3930 {
3931 int i;
3932 u16 msi_control;
3933
3934 for (i = 0; i < sp->num_entries; i++) {
3935 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3936 int vector = sp->entries[i].vector;
3937 void *arg = sp->s2io_entries[i].arg;
3938 free_irq(vector, arg);
3939 }
3940 }
3941
3942 kfree(sp->entries);
3943 kfree(sp->s2io_entries);
3944 sp->entries = NULL;
3945 sp->s2io_entries = NULL;
3946
3947 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3948 msi_control &= 0xFFFE; /* Disable MSI */
3949 pci_write_config_word(sp->pdev, 0x42, msi_control);
3950
3951 pci_disable_msix(sp->pdev);
3952 }
3953
3954 static void remove_inta_isr(struct s2io_nic *sp)
3955 {
3956 struct net_device *dev = sp->dev;
3957
3958 free_irq(sp->pdev->irq, dev);
3959 }
3960
3961 /* ********************************************************* *
3962 * Functions defined below concern the OS part of the driver *
3963 * ********************************************************* */
3964
3965 /**
3966 * s2io_open - open entry point of the driver
3967 * @dev : pointer to the device structure.
3968 * Description:
3969 * This function is the open entry point of the driver. It mainly calls a
3970 * function to allocate Rx buffers and inserts them into the buffer
3971 * descriptors and then enables the Rx part of the NIC.
3972 * Return value:
3973 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3974 * file on failure.
3975 */
3976
3977 static int s2io_open(struct net_device *dev)
3978 {
3979 struct s2io_nic *sp = netdev_priv(dev);
3980 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3981 int err = 0;
3982
3983 /*
3984 * Make sure you have link off by default every time
3985 * Nic is initialized
3986 */
3987 netif_carrier_off(dev);
3988 sp->last_link_state = 0;
3989
3990 /* Initialize H/W and enable interrupts */
3991 err = s2io_card_up(sp);
3992 if (err) {
3993 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3994 dev->name);
3995 goto hw_init_failed;
3996 }
3997
3998 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3999 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4000 s2io_card_down(sp);
4001 err = -ENODEV;
4002 goto hw_init_failed;
4003 }
4004 s2io_start_all_tx_queue(sp);
4005 return 0;
4006
4007 hw_init_failed:
4008 if (sp->config.intr_type == MSI_X) {
4009 if (sp->entries) {
4010 kfree(sp->entries);
4011 swstats->mem_freed += sp->num_entries *
4012 sizeof(struct msix_entry);
4013 }
4014 if (sp->s2io_entries) {
4015 kfree(sp->s2io_entries);
4016 swstats->mem_freed += sp->num_entries *
4017 sizeof(struct s2io_msix_entry);
4018 }
4019 }
4020 return err;
4021 }
4022
4023 /**
4024 * s2io_close -close entry point of the driver
4025 * @dev : device pointer.
4026 * Description:
4027 * This is the stop entry point of the driver. It needs to undo exactly
4028 * whatever was done by the open entry point,thus it's usually referred to
4029 * as the close function.Among other things this function mainly stops the
4030 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4031 * Return value:
4032 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4033 * file on failure.
4034 */
4035
4036 static int s2io_close(struct net_device *dev)
4037 {
4038 struct s2io_nic *sp = netdev_priv(dev);
4039 struct config_param *config = &sp->config;
4040 u64 tmp64;
4041 int offset;
4042
4043 /* Return if the device is already closed *
4044 * Can happen when s2io_card_up failed in change_mtu *
4045 */
4046 if (!is_s2io_card_up(sp))
4047 return 0;
4048
4049 s2io_stop_all_tx_queue(sp);
4050 /* delete all populated mac entries */
4051 for (offset = 1; offset < config->max_mc_addr; offset++) {
4052 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4053 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4054 do_s2io_delete_unicast_mc(sp, tmp64);
4055 }
4056
4057 s2io_card_down(sp);
4058
4059 return 0;
4060 }
4061
4062 /**
4063 * s2io_xmit - Tx entry point of te driver
4064 * @skb : the socket buffer containing the Tx data.
4065 * @dev : device pointer.
4066 * Description :
4067 * This function is the Tx entry point of the driver. S2IO NIC supports
4068 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4069 * NOTE: when device cant queue the pkt,just the trans_start variable will
4070 * not be upadted.
4071 * Return value:
4072 * 0 on success & 1 on failure.
4073 */
4074
4075 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4076 {
4077 struct s2io_nic *sp = netdev_priv(dev);
4078 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4079 register u64 val64;
4080 struct TxD *txdp;
4081 struct TxFIFO_element __iomem *tx_fifo;
4082 unsigned long flags = 0;
4083 u16 vlan_tag = 0;
4084 struct fifo_info *fifo = NULL;
4085 int do_spin_lock = 1;
4086 int offload_type;
4087 int enable_per_list_interrupt = 0;
4088 struct config_param *config = &sp->config;
4089 struct mac_info *mac_control = &sp->mac_control;
4090 struct stat_block *stats = mac_control->stats_info;
4091 struct swStat *swstats = &stats->sw_stat;
4092
4093 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4094
4095 if (unlikely(skb->len <= 0)) {
4096 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4097 dev_kfree_skb_any(skb);
4098 return NETDEV_TX_OK;
4099 }
4100
4101 if (!is_s2io_card_up(sp)) {
4102 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4103 dev->name);
4104 dev_kfree_skb(skb);
4105 return NETDEV_TX_OK;
4106 }
4107
4108 queue = 0;
4109 if (sp->vlgrp && vlan_tx_tag_present(skb))
4110 vlan_tag = vlan_tx_tag_get(skb);
4111 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4112 if (skb->protocol == htons(ETH_P_IP)) {
4113 struct iphdr *ip;
4114 struct tcphdr *th;
4115 ip = ip_hdr(skb);
4116
4117 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4118 th = (struct tcphdr *)(((unsigned char *)ip) +
4119 ip->ihl*4);
4120
4121 if (ip->protocol == IPPROTO_TCP) {
4122 queue_len = sp->total_tcp_fifos;
4123 queue = (ntohs(th->source) +
4124 ntohs(th->dest)) &
4125 sp->fifo_selector[queue_len - 1];
4126 if (queue >= queue_len)
4127 queue = queue_len - 1;
4128 } else if (ip->protocol == IPPROTO_UDP) {
4129 queue_len = sp->total_udp_fifos;
4130 queue = (ntohs(th->source) +
4131 ntohs(th->dest)) &
4132 sp->fifo_selector[queue_len - 1];
4133 if (queue >= queue_len)
4134 queue = queue_len - 1;
4135 queue += sp->udp_fifo_idx;
4136 if (skb->len > 1024)
4137 enable_per_list_interrupt = 1;
4138 do_spin_lock = 0;
4139 }
4140 }
4141 }
4142 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4143 /* get fifo number based on skb->priority value */
4144 queue = config->fifo_mapping
4145 [skb->priority & (MAX_TX_FIFOS - 1)];
4146 fifo = &mac_control->fifos[queue];
4147
4148 if (do_spin_lock)
4149 spin_lock_irqsave(&fifo->tx_lock, flags);
4150 else {
4151 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4152 return NETDEV_TX_LOCKED;
4153 }
4154
4155 if (sp->config.multiq) {
4156 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4157 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4158 return NETDEV_TX_BUSY;
4159 }
4160 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4161 if (netif_queue_stopped(dev)) {
4162 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4163 return NETDEV_TX_BUSY;
4164 }
4165 }
4166
4167 put_off = (u16)fifo->tx_curr_put_info.offset;
4168 get_off = (u16)fifo->tx_curr_get_info.offset;
4169 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4170
4171 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4172 /* Avoid "put" pointer going beyond "get" pointer */
4173 if (txdp->Host_Control ||
4174 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4175 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4176 s2io_stop_tx_queue(sp, fifo->fifo_no);
4177 dev_kfree_skb(skb);
4178 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4179 return NETDEV_TX_OK;
4180 }
4181
4182 offload_type = s2io_offload_type(skb);
4183 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4184 txdp->Control_1 |= TXD_TCP_LSO_EN;
4185 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4186 }
4187 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4188 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4189 TXD_TX_CKO_TCP_EN |
4190 TXD_TX_CKO_UDP_EN);
4191 }
4192 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4193 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4194 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4195 if (enable_per_list_interrupt)
4196 if (put_off & (queue_len >> 5))
4197 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4198 if (vlan_tag) {
4199 txdp->Control_2 |= TXD_VLAN_ENABLE;
4200 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4201 }
4202
4203 frg_len = skb->len - skb->data_len;
4204 if (offload_type == SKB_GSO_UDP) {
4205 int ufo_size;
4206
4207 ufo_size = s2io_udp_mss(skb);
4208 ufo_size &= ~7;
4209 txdp->Control_1 |= TXD_UFO_EN;
4210 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4211 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4212 #ifdef __BIG_ENDIAN
4213 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4214 fifo->ufo_in_band_v[put_off] =
4215 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4216 #else
4217 fifo->ufo_in_band_v[put_off] =
4218 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4219 #endif
4220 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4221 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4222 fifo->ufo_in_band_v,
4223 sizeof(u64),
4224 PCI_DMA_TODEVICE);
4225 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4226 goto pci_map_failed;
4227 txdp++;
4228 }
4229
4230 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4231 frg_len, PCI_DMA_TODEVICE);
4232 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4233 goto pci_map_failed;
4234
4235 txdp->Host_Control = (unsigned long)skb;
4236 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4237 if (offload_type == SKB_GSO_UDP)
4238 txdp->Control_1 |= TXD_UFO_EN;
4239
4240 frg_cnt = skb_shinfo(skb)->nr_frags;
4241 /* For fragmented SKB. */
4242 for (i = 0; i < frg_cnt; i++) {
4243 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4244 /* A '0' length fragment will be ignored */
4245 if (!frag->size)
4246 continue;
4247 txdp++;
4248 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4249 frag->page_offset,
4250 frag->size,
4251 PCI_DMA_TODEVICE);
4252 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4253 if (offload_type == SKB_GSO_UDP)
4254 txdp->Control_1 |= TXD_UFO_EN;
4255 }
4256 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4257
4258 if (offload_type == SKB_GSO_UDP)
4259 frg_cnt++; /* as Txd0 was used for inband header */
4260
4261 tx_fifo = mac_control->tx_FIFO_start[queue];
4262 val64 = fifo->list_info[put_off].list_phy_addr;
4263 writeq(val64, &tx_fifo->TxDL_Pointer);
4264
4265 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4266 TX_FIFO_LAST_LIST);
4267 if (offload_type)
4268 val64 |= TX_FIFO_SPECIAL_FUNC;
4269
4270 writeq(val64, &tx_fifo->List_Control);
4271
4272 mmiowb();
4273
4274 put_off++;
4275 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4276 put_off = 0;
4277 fifo->tx_curr_put_info.offset = put_off;
4278
4279 /* Avoid "put" pointer going beyond "get" pointer */
4280 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4281 swstats->fifo_full_cnt++;
4282 DBG_PRINT(TX_DBG,
4283 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4284 put_off, get_off);
4285 s2io_stop_tx_queue(sp, fifo->fifo_no);
4286 }
4287 swstats->mem_allocated += skb->truesize;
4288 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4289
4290 if (sp->config.intr_type == MSI_X)
4291 tx_intr_handler(fifo);
4292
4293 return NETDEV_TX_OK;
4294
4295 pci_map_failed:
4296 swstats->pci_map_fail_cnt++;
4297 s2io_stop_tx_queue(sp, fifo->fifo_no);
4298 swstats->mem_freed += skb->truesize;
4299 dev_kfree_skb(skb);
4300 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4301 return NETDEV_TX_OK;
4302 }
4303
4304 static void
4305 s2io_alarm_handle(unsigned long data)
4306 {
4307 struct s2io_nic *sp = (struct s2io_nic *)data;
4308 struct net_device *dev = sp->dev;
4309
4310 s2io_handle_errors(dev);
4311 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4312 }
4313
4314 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4315 {
4316 struct ring_info *ring = (struct ring_info *)dev_id;
4317 struct s2io_nic *sp = ring->nic;
4318 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4319
4320 if (unlikely(!is_s2io_card_up(sp)))
4321 return IRQ_HANDLED;
4322
4323 if (sp->config.napi) {
4324 u8 __iomem *addr = NULL;
4325 u8 val8 = 0;
4326
4327 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4328 addr += (7 - ring->ring_no);
4329 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4330 writeb(val8, addr);
4331 val8 = readb(addr);
4332 napi_schedule(&ring->napi);
4333 } else {
4334 rx_intr_handler(ring, 0);
4335 s2io_chk_rx_buffers(sp, ring);
4336 }
4337
4338 return IRQ_HANDLED;
4339 }
4340
4341 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4342 {
4343 int i;
4344 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4345 struct s2io_nic *sp = fifos->nic;
4346 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4347 struct config_param *config = &sp->config;
4348 u64 reason;
4349
4350 if (unlikely(!is_s2io_card_up(sp)))
4351 return IRQ_NONE;
4352
4353 reason = readq(&bar0->general_int_status);
4354 if (unlikely(reason == S2IO_MINUS_ONE))
4355 /* Nothing much can be done. Get out */
4356 return IRQ_HANDLED;
4357
4358 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4359 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4360
4361 if (reason & GEN_INTR_TXPIC)
4362 s2io_txpic_intr_handle(sp);
4363
4364 if (reason & GEN_INTR_TXTRAFFIC)
4365 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4366
4367 for (i = 0; i < config->tx_fifo_num; i++)
4368 tx_intr_handler(&fifos[i]);
4369
4370 writeq(sp->general_int_mask, &bar0->general_int_mask);
4371 readl(&bar0->general_int_status);
4372 return IRQ_HANDLED;
4373 }
4374 /* The interrupt was not raised by us */
4375 return IRQ_NONE;
4376 }
4377
4378 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4379 {
4380 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4381 u64 val64;
4382
4383 val64 = readq(&bar0->pic_int_status);
4384 if (val64 & PIC_INT_GPIO) {
4385 val64 = readq(&bar0->gpio_int_reg);
4386 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4387 (val64 & GPIO_INT_REG_LINK_UP)) {
4388 /*
4389 * This is unstable state so clear both up/down
4390 * interrupt and adapter to re-evaluate the link state.
4391 */
4392 val64 |= GPIO_INT_REG_LINK_DOWN;
4393 val64 |= GPIO_INT_REG_LINK_UP;
4394 writeq(val64, &bar0->gpio_int_reg);
4395 val64 = readq(&bar0->gpio_int_mask);
4396 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4397 GPIO_INT_MASK_LINK_DOWN);
4398 writeq(val64, &bar0->gpio_int_mask);
4399 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4400 val64 = readq(&bar0->adapter_status);
4401 /* Enable Adapter */
4402 val64 = readq(&bar0->adapter_control);
4403 val64 |= ADAPTER_CNTL_EN;
4404 writeq(val64, &bar0->adapter_control);
4405 val64 |= ADAPTER_LED_ON;
4406 writeq(val64, &bar0->adapter_control);
4407 if (!sp->device_enabled_once)
4408 sp->device_enabled_once = 1;
4409
4410 s2io_link(sp, LINK_UP);
4411 /*
4412 * unmask link down interrupt and mask link-up
4413 * intr
4414 */
4415 val64 = readq(&bar0->gpio_int_mask);
4416 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4417 val64 |= GPIO_INT_MASK_LINK_UP;
4418 writeq(val64, &bar0->gpio_int_mask);
4419
4420 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4421 val64 = readq(&bar0->adapter_status);
4422 s2io_link(sp, LINK_DOWN);
4423 /* Link is down so unmaks link up interrupt */
4424 val64 = readq(&bar0->gpio_int_mask);
4425 val64 &= ~GPIO_INT_MASK_LINK_UP;
4426 val64 |= GPIO_INT_MASK_LINK_DOWN;
4427 writeq(val64, &bar0->gpio_int_mask);
4428
4429 /* turn off LED */
4430 val64 = readq(&bar0->adapter_control);
4431 val64 = val64 & (~ADAPTER_LED_ON);
4432 writeq(val64, &bar0->adapter_control);
4433 }
4434 }
4435 val64 = readq(&bar0->gpio_int_mask);
4436 }
4437
4438 /**
4439 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4440 * @value: alarm bits
4441 * @addr: address value
4442 * @cnt: counter variable
4443 * Description: Check for alarm and increment the counter
4444 * Return Value:
4445 * 1 - if alarm bit set
4446 * 0 - if alarm bit is not set
4447 */
4448 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4449 unsigned long long *cnt)
4450 {
4451 u64 val64;
4452 val64 = readq(addr);
4453 if (val64 & value) {
4454 writeq(val64, addr);
4455 (*cnt)++;
4456 return 1;
4457 }
4458 return 0;
4459
4460 }
4461
4462 /**
4463 * s2io_handle_errors - Xframe error indication handler
4464 * @nic: device private variable
4465 * Description: Handle alarms such as loss of link, single or
4466 * double ECC errors, critical and serious errors.
4467 * Return Value:
4468 * NONE
4469 */
4470 static void s2io_handle_errors(void *dev_id)
4471 {
4472 struct net_device *dev = (struct net_device *)dev_id;
4473 struct s2io_nic *sp = netdev_priv(dev);
4474 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4475 u64 temp64 = 0, val64 = 0;
4476 int i = 0;
4477
4478 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4479 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4480
4481 if (!is_s2io_card_up(sp))
4482 return;
4483
4484 if (pci_channel_offline(sp->pdev))
4485 return;
4486
4487 memset(&sw_stat->ring_full_cnt, 0,
4488 sizeof(sw_stat->ring_full_cnt));
4489
4490 /* Handling the XPAK counters update */
4491 if (stats->xpak_timer_count < 72000) {
4492 /* waiting for an hour */
4493 stats->xpak_timer_count++;
4494 } else {
4495 s2io_updt_xpak_counter(dev);
4496 /* reset the count to zero */
4497 stats->xpak_timer_count = 0;
4498 }
4499
4500 /* Handling link status change error Intr */
4501 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4502 val64 = readq(&bar0->mac_rmac_err_reg);
4503 writeq(val64, &bar0->mac_rmac_err_reg);
4504 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4505 schedule_work(&sp->set_link_task);
4506 }
4507
4508 /* In case of a serious error, the device will be Reset. */
4509 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4510 &sw_stat->serious_err_cnt))
4511 goto reset;
4512
4513 /* Check for data parity error */
4514 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4515 &sw_stat->parity_err_cnt))
4516 goto reset;
4517
4518 /* Check for ring full counter */
4519 if (sp->device_type == XFRAME_II_DEVICE) {
4520 val64 = readq(&bar0->ring_bump_counter1);
4521 for (i = 0; i < 4; i++) {
4522 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4523 temp64 >>= 64 - ((i+1)*16);
4524 sw_stat->ring_full_cnt[i] += temp64;
4525 }
4526
4527 val64 = readq(&bar0->ring_bump_counter2);
4528 for (i = 0; i < 4; i++) {
4529 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4530 temp64 >>= 64 - ((i+1)*16);
4531 sw_stat->ring_full_cnt[i+4] += temp64;
4532 }
4533 }
4534
4535 val64 = readq(&bar0->txdma_int_status);
4536 /*check for pfc_err*/
4537 if (val64 & TXDMA_PFC_INT) {
4538 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4539 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4540 PFC_PCIX_ERR,
4541 &bar0->pfc_err_reg,
4542 &sw_stat->pfc_err_cnt))
4543 goto reset;
4544 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4545 &bar0->pfc_err_reg,
4546 &sw_stat->pfc_err_cnt);
4547 }
4548
4549 /*check for tda_err*/
4550 if (val64 & TXDMA_TDA_INT) {
4551 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4552 TDA_SM0_ERR_ALARM |
4553 TDA_SM1_ERR_ALARM,
4554 &bar0->tda_err_reg,
4555 &sw_stat->tda_err_cnt))
4556 goto reset;
4557 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4558 &bar0->tda_err_reg,
4559 &sw_stat->tda_err_cnt);
4560 }
4561 /*check for pcc_err*/
4562 if (val64 & TXDMA_PCC_INT) {
4563 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4564 PCC_N_SERR | PCC_6_COF_OV_ERR |
4565 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4566 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4567 PCC_TXB_ECC_DB_ERR,
4568 &bar0->pcc_err_reg,
4569 &sw_stat->pcc_err_cnt))
4570 goto reset;
4571 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4572 &bar0->pcc_err_reg,
4573 &sw_stat->pcc_err_cnt);
4574 }
4575
4576 /*check for tti_err*/
4577 if (val64 & TXDMA_TTI_INT) {
4578 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4579 &bar0->tti_err_reg,
4580 &sw_stat->tti_err_cnt))
4581 goto reset;
4582 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4583 &bar0->tti_err_reg,
4584 &sw_stat->tti_err_cnt);
4585 }
4586
4587 /*check for lso_err*/
4588 if (val64 & TXDMA_LSO_INT) {
4589 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4590 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4591 &bar0->lso_err_reg,
4592 &sw_stat->lso_err_cnt))
4593 goto reset;
4594 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4595 &bar0->lso_err_reg,
4596 &sw_stat->lso_err_cnt);
4597 }
4598
4599 /*check for tpa_err*/
4600 if (val64 & TXDMA_TPA_INT) {
4601 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4602 &bar0->tpa_err_reg,
4603 &sw_stat->tpa_err_cnt))
4604 goto reset;
4605 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4606 &bar0->tpa_err_reg,
4607 &sw_stat->tpa_err_cnt);
4608 }
4609
4610 /*check for sm_err*/
4611 if (val64 & TXDMA_SM_INT) {
4612 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4613 &bar0->sm_err_reg,
4614 &sw_stat->sm_err_cnt))
4615 goto reset;
4616 }
4617
4618 val64 = readq(&bar0->mac_int_status);
4619 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4620 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4621 &bar0->mac_tmac_err_reg,
4622 &sw_stat->mac_tmac_err_cnt))
4623 goto reset;
4624 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4625 TMAC_DESC_ECC_SG_ERR |
4626 TMAC_DESC_ECC_DB_ERR,
4627 &bar0->mac_tmac_err_reg,
4628 &sw_stat->mac_tmac_err_cnt);
4629 }
4630
4631 val64 = readq(&bar0->xgxs_int_status);
4632 if (val64 & XGXS_INT_STATUS_TXGXS) {
4633 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4634 &bar0->xgxs_txgxs_err_reg,
4635 &sw_stat->xgxs_txgxs_err_cnt))
4636 goto reset;
4637 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4638 &bar0->xgxs_txgxs_err_reg,
4639 &sw_stat->xgxs_txgxs_err_cnt);
4640 }
4641
4642 val64 = readq(&bar0->rxdma_int_status);
4643 if (val64 & RXDMA_INT_RC_INT_M) {
4644 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4645 RC_FTC_ECC_DB_ERR |
4646 RC_PRCn_SM_ERR_ALARM |
4647 RC_FTC_SM_ERR_ALARM,
4648 &bar0->rc_err_reg,
4649 &sw_stat->rc_err_cnt))
4650 goto reset;
4651 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4652 RC_FTC_ECC_SG_ERR |
4653 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4654 &sw_stat->rc_err_cnt);
4655 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4656 PRC_PCI_AB_WR_Rn |
4657 PRC_PCI_AB_F_WR_Rn,
4658 &bar0->prc_pcix_err_reg,
4659 &sw_stat->prc_pcix_err_cnt))
4660 goto reset;
4661 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4662 PRC_PCI_DP_WR_Rn |
4663 PRC_PCI_DP_F_WR_Rn,
4664 &bar0->prc_pcix_err_reg,
4665 &sw_stat->prc_pcix_err_cnt);
4666 }
4667
4668 if (val64 & RXDMA_INT_RPA_INT_M) {
4669 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4670 &bar0->rpa_err_reg,
4671 &sw_stat->rpa_err_cnt))
4672 goto reset;
4673 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4674 &bar0->rpa_err_reg,
4675 &sw_stat->rpa_err_cnt);
4676 }
4677
4678 if (val64 & RXDMA_INT_RDA_INT_M) {
4679 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4680 RDA_FRM_ECC_DB_N_AERR |
4681 RDA_SM1_ERR_ALARM |
4682 RDA_SM0_ERR_ALARM |
4683 RDA_RXD_ECC_DB_SERR,
4684 &bar0->rda_err_reg,
4685 &sw_stat->rda_err_cnt))
4686 goto reset;
4687 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4688 RDA_FRM_ECC_SG_ERR |
4689 RDA_MISC_ERR |
4690 RDA_PCIX_ERR,
4691 &bar0->rda_err_reg,
4692 &sw_stat->rda_err_cnt);
4693 }
4694
4695 if (val64 & RXDMA_INT_RTI_INT_M) {
4696 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4697 &bar0->rti_err_reg,
4698 &sw_stat->rti_err_cnt))
4699 goto reset;
4700 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4701 &bar0->rti_err_reg,
4702 &sw_stat->rti_err_cnt);
4703 }
4704
4705 val64 = readq(&bar0->mac_int_status);
4706 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4707 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4708 &bar0->mac_rmac_err_reg,
4709 &sw_stat->mac_rmac_err_cnt))
4710 goto reset;
4711 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4712 RMAC_SINGLE_ECC_ERR |
4713 RMAC_DOUBLE_ECC_ERR,
4714 &bar0->mac_rmac_err_reg,
4715 &sw_stat->mac_rmac_err_cnt);
4716 }
4717
4718 val64 = readq(&bar0->xgxs_int_status);
4719 if (val64 & XGXS_INT_STATUS_RXGXS) {
4720 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4721 &bar0->xgxs_rxgxs_err_reg,
4722 &sw_stat->xgxs_rxgxs_err_cnt))
4723 goto reset;
4724 }
4725
4726 val64 = readq(&bar0->mc_int_status);
4727 if (val64 & MC_INT_STATUS_MC_INT) {
4728 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4729 &bar0->mc_err_reg,
4730 &sw_stat->mc_err_cnt))
4731 goto reset;
4732
4733 /* Handling Ecc errors */
4734 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4735 writeq(val64, &bar0->mc_err_reg);
4736 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4737 sw_stat->double_ecc_errs++;
4738 if (sp->device_type != XFRAME_II_DEVICE) {
4739 /*
4740 * Reset XframeI only if critical error
4741 */
4742 if (val64 &
4743 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4744 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4745 goto reset;
4746 }
4747 } else
4748 sw_stat->single_ecc_errs++;
4749 }
4750 }
4751 return;
4752
4753 reset:
4754 s2io_stop_all_tx_queue(sp);
4755 schedule_work(&sp->rst_timer_task);
4756 sw_stat->soft_reset_cnt++;
4757 return;
4758 }
4759
4760 /**
4761 * s2io_isr - ISR handler of the device .
4762 * @irq: the irq of the device.
4763 * @dev_id: a void pointer to the dev structure of the NIC.
4764 * Description: This function is the ISR handler of the device. It
4765 * identifies the reason for the interrupt and calls the relevant
4766 * service routines. As a contongency measure, this ISR allocates the
4767 * recv buffers, if their numbers are below the panic value which is
4768 * presently set to 25% of the original number of rcv buffers allocated.
4769 * Return value:
4770 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4771 * IRQ_NONE: will be returned if interrupt is not from our device
4772 */
4773 static irqreturn_t s2io_isr(int irq, void *dev_id)
4774 {
4775 struct net_device *dev = (struct net_device *)dev_id;
4776 struct s2io_nic *sp = netdev_priv(dev);
4777 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4778 int i;
4779 u64 reason = 0;
4780 struct mac_info *mac_control;
4781 struct config_param *config;
4782
4783 /* Pretend we handled any irq's from a disconnected card */
4784 if (pci_channel_offline(sp->pdev))
4785 return IRQ_NONE;
4786
4787 if (!is_s2io_card_up(sp))
4788 return IRQ_NONE;
4789
4790 config = &sp->config;
4791 mac_control = &sp->mac_control;
4792
4793 /*
4794 * Identify the cause for interrupt and call the appropriate
4795 * interrupt handler. Causes for the interrupt could be;
4796 * 1. Rx of packet.
4797 * 2. Tx complete.
4798 * 3. Link down.
4799 */
4800 reason = readq(&bar0->general_int_status);
4801
4802 if (unlikely(reason == S2IO_MINUS_ONE))
4803 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4804
4805 if (reason &
4806 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4807 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4808
4809 if (config->napi) {
4810 if (reason & GEN_INTR_RXTRAFFIC) {
4811 napi_schedule(&sp->napi);
4812 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4813 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4814 readl(&bar0->rx_traffic_int);
4815 }
4816 } else {
4817 /*
4818 * rx_traffic_int reg is an R1 register, writing all 1's
4819 * will ensure that the actual interrupt causing bit
4820 * get's cleared and hence a read can be avoided.
4821 */
4822 if (reason & GEN_INTR_RXTRAFFIC)
4823 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4824
4825 for (i = 0; i < config->rx_ring_num; i++) {
4826 struct ring_info *ring = &mac_control->rings[i];
4827
4828 rx_intr_handler(ring, 0);
4829 }
4830 }
4831
4832 /*
4833 * tx_traffic_int reg is an R1 register, writing all 1's
4834 * will ensure that the actual interrupt causing bit get's
4835 * cleared and hence a read can be avoided.
4836 */
4837 if (reason & GEN_INTR_TXTRAFFIC)
4838 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4839
4840 for (i = 0; i < config->tx_fifo_num; i++)
4841 tx_intr_handler(&mac_control->fifos[i]);
4842
4843 if (reason & GEN_INTR_TXPIC)
4844 s2io_txpic_intr_handle(sp);
4845
4846 /*
4847 * Reallocate the buffers from the interrupt handler itself.
4848 */
4849 if (!config->napi) {
4850 for (i = 0; i < config->rx_ring_num; i++) {
4851 struct ring_info *ring = &mac_control->rings[i];
4852
4853 s2io_chk_rx_buffers(sp, ring);
4854 }
4855 }
4856 writeq(sp->general_int_mask, &bar0->general_int_mask);
4857 readl(&bar0->general_int_status);
4858
4859 return IRQ_HANDLED;
4860
4861 } else if (!reason) {
4862 /* The interrupt was not raised by us */
4863 return IRQ_NONE;
4864 }
4865
4866 return IRQ_HANDLED;
4867 }
4868
4869 /**
4870 * s2io_updt_stats -
4871 */
4872 static void s2io_updt_stats(struct s2io_nic *sp)
4873 {
4874 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4875 u64 val64;
4876 int cnt = 0;
4877
4878 if (is_s2io_card_up(sp)) {
4879 /* Apprx 30us on a 133 MHz bus */
4880 val64 = SET_UPDT_CLICKS(10) |
4881 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4882 writeq(val64, &bar0->stat_cfg);
4883 do {
4884 udelay(100);
4885 val64 = readq(&bar0->stat_cfg);
4886 if (!(val64 & s2BIT(0)))
4887 break;
4888 cnt++;
4889 if (cnt == 5)
4890 break; /* Updt failed */
4891 } while (1);
4892 }
4893 }
4894
4895 /**
4896 * s2io_get_stats - Updates the device statistics structure.
4897 * @dev : pointer to the device structure.
4898 * Description:
4899 * This function updates the device statistics structure in the s2io_nic
4900 * structure and returns a pointer to the same.
4901 * Return value:
4902 * pointer to the updated net_device_stats structure.
4903 */
4904
4905 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4906 {
4907 struct s2io_nic *sp = netdev_priv(dev);
4908 struct config_param *config = &sp->config;
4909 struct mac_info *mac_control = &sp->mac_control;
4910 struct stat_block *stats = mac_control->stats_info;
4911 int i;
4912
4913 /* Configure Stats for immediate updt */
4914 s2io_updt_stats(sp);
4915
4916 /* Using sp->stats as a staging area, because reset (due to mtu
4917 change, for example) will clear some hardware counters */
4918 dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
4919 sp->stats.tx_packets;
4920 sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4921
4922 dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
4923 sp->stats.tx_errors;
4924 sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4925
4926 dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
4927 sp->stats.rx_errors;
4928 sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4929
4930 dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
4931 sp->stats.multicast;
4932 sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4933
4934 dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
4935 sp->stats.rx_length_errors;
4936 sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
4937
4938 /* collect per-ring rx_packets and rx_bytes */
4939 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4940 for (i = 0; i < config->rx_ring_num; i++) {
4941 struct ring_info *ring = &mac_control->rings[i];
4942
4943 dev->stats.rx_packets += ring->rx_packets;
4944 dev->stats.rx_bytes += ring->rx_bytes;
4945 }
4946
4947 return &dev->stats;
4948 }
4949
4950 /**
4951 * s2io_set_multicast - entry point for multicast address enable/disable.
4952 * @dev : pointer to the device structure
4953 * Description:
4954 * This function is a driver entry point which gets called by the kernel
4955 * whenever multicast addresses must be enabled/disabled. This also gets
4956 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4957 * determine, if multicast address must be enabled or if promiscuous mode
4958 * is to be disabled etc.
4959 * Return value:
4960 * void.
4961 */
4962
4963 static void s2io_set_multicast(struct net_device *dev)
4964 {
4965 int i, j, prev_cnt;
4966 struct dev_mc_list *mclist;
4967 struct s2io_nic *sp = netdev_priv(dev);
4968 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4969 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4970 0xfeffffffffffULL;
4971 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4972 void __iomem *add;
4973 struct config_param *config = &sp->config;
4974
4975 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4976 /* Enable all Multicast addresses */
4977 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4978 &bar0->rmac_addr_data0_mem);
4979 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4980 &bar0->rmac_addr_data1_mem);
4981 val64 = RMAC_ADDR_CMD_MEM_WE |
4982 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4983 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4984 writeq(val64, &bar0->rmac_addr_cmd_mem);
4985 /* Wait till command completes */
4986 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4987 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4988 S2IO_BIT_RESET);
4989
4990 sp->m_cast_flg = 1;
4991 sp->all_multi_pos = config->max_mc_addr - 1;
4992 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4993 /* Disable all Multicast addresses */
4994 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4995 &bar0->rmac_addr_data0_mem);
4996 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4997 &bar0->rmac_addr_data1_mem);
4998 val64 = RMAC_ADDR_CMD_MEM_WE |
4999 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5000 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5001 writeq(val64, &bar0->rmac_addr_cmd_mem);
5002 /* Wait till command completes */
5003 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5004 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5005 S2IO_BIT_RESET);
5006
5007 sp->m_cast_flg = 0;
5008 sp->all_multi_pos = 0;
5009 }
5010
5011 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5012 /* Put the NIC into promiscuous mode */
5013 add = &bar0->mac_cfg;
5014 val64 = readq(&bar0->mac_cfg);
5015 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5016
5017 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5018 writel((u32)val64, add);
5019 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5020 writel((u32) (val64 >> 32), (add + 4));
5021
5022 if (vlan_tag_strip != 1) {
5023 val64 = readq(&bar0->rx_pa_cfg);
5024 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5025 writeq(val64, &bar0->rx_pa_cfg);
5026 sp->vlan_strip_flag = 0;
5027 }
5028
5029 val64 = readq(&bar0->mac_cfg);
5030 sp->promisc_flg = 1;
5031 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5032 dev->name);
5033 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5034 /* Remove the NIC from promiscuous mode */
5035 add = &bar0->mac_cfg;
5036 val64 = readq(&bar0->mac_cfg);
5037 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5038
5039 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5040 writel((u32)val64, add);
5041 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5042 writel((u32) (val64 >> 32), (add + 4));
5043
5044 if (vlan_tag_strip != 0) {
5045 val64 = readq(&bar0->rx_pa_cfg);
5046 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5047 writeq(val64, &bar0->rx_pa_cfg);
5048 sp->vlan_strip_flag = 1;
5049 }
5050
5051 val64 = readq(&bar0->mac_cfg);
5052 sp->promisc_flg = 0;
5053 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5054 }
5055
5056 /* Update individual M_CAST address list */
5057 if ((!sp->m_cast_flg) && dev->mc_count) {
5058 if (dev->mc_count >
5059 (config->max_mc_addr - config->max_mac_addr)) {
5060 DBG_PRINT(ERR_DBG,
5061 "%s: No more Rx filters can be added - "
5062 "please enable ALL_MULTI instead\n",
5063 dev->name);
5064 return;
5065 }
5066
5067 prev_cnt = sp->mc_addr_count;
5068 sp->mc_addr_count = dev->mc_count;
5069
5070 /* Clear out the previous list of Mc in the H/W. */
5071 for (i = 0; i < prev_cnt; i++) {
5072 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5073 &bar0->rmac_addr_data0_mem);
5074 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5075 &bar0->rmac_addr_data1_mem);
5076 val64 = RMAC_ADDR_CMD_MEM_WE |
5077 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5078 RMAC_ADDR_CMD_MEM_OFFSET
5079 (config->mc_start_offset + i);
5080 writeq(val64, &bar0->rmac_addr_cmd_mem);
5081
5082 /* Wait for command completes */
5083 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5084 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5085 S2IO_BIT_RESET)) {
5086 DBG_PRINT(ERR_DBG,
5087 "%s: Adding Multicasts failed\n",
5088 dev->name);
5089 return;
5090 }
5091 }
5092
5093 /* Create the new Rx filter list and update the same in H/W. */
5094 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5095 i++, mclist = mclist->next) {
5096 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5097 ETH_ALEN);
5098 mac_addr = 0;
5099 for (j = 0; j < ETH_ALEN; j++) {
5100 mac_addr |= mclist->dmi_addr[j];
5101 mac_addr <<= 8;
5102 }
5103 mac_addr >>= 8;
5104 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5105 &bar0->rmac_addr_data0_mem);
5106 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5107 &bar0->rmac_addr_data1_mem);
5108 val64 = RMAC_ADDR_CMD_MEM_WE |
5109 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5110 RMAC_ADDR_CMD_MEM_OFFSET
5111 (i + config->mc_start_offset);
5112 writeq(val64, &bar0->rmac_addr_cmd_mem);
5113
5114 /* Wait for command completes */
5115 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5116 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5117 S2IO_BIT_RESET)) {
5118 DBG_PRINT(ERR_DBG,
5119 "%s: Adding Multicasts failed\n",
5120 dev->name);
5121 return;
5122 }
5123 }
5124 }
5125 }
5126
5127 /* read from CAM unicast & multicast addresses and store it in
5128 * def_mac_addr structure
5129 */
5130 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5131 {
5132 int offset;
5133 u64 mac_addr = 0x0;
5134 struct config_param *config = &sp->config;
5135
5136 /* store unicast & multicast mac addresses */
5137 for (offset = 0; offset < config->max_mc_addr; offset++) {
5138 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5139 /* if read fails disable the entry */
5140 if (mac_addr == FAILURE)
5141 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5142 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5143 }
5144 }
5145
5146 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5147 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5148 {
5149 int offset;
5150 struct config_param *config = &sp->config;
5151 /* restore unicast mac address */
5152 for (offset = 0; offset < config->max_mac_addr; offset++)
5153 do_s2io_prog_unicast(sp->dev,
5154 sp->def_mac_addr[offset].mac_addr);
5155
5156 /* restore multicast mac address */
5157 for (offset = config->mc_start_offset;
5158 offset < config->max_mc_addr; offset++)
5159 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5160 }
5161
5162 /* add a multicast MAC address to CAM */
5163 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5164 {
5165 int i;
5166 u64 mac_addr = 0;
5167 struct config_param *config = &sp->config;
5168
5169 for (i = 0; i < ETH_ALEN; i++) {
5170 mac_addr <<= 8;
5171 mac_addr |= addr[i];
5172 }
5173 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5174 return SUCCESS;
5175
5176 /* check if the multicast mac already preset in CAM */
5177 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5178 u64 tmp64;
5179 tmp64 = do_s2io_read_unicast_mc(sp, i);
5180 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5181 break;
5182
5183 if (tmp64 == mac_addr)
5184 return SUCCESS;
5185 }
5186 if (i == config->max_mc_addr) {
5187 DBG_PRINT(ERR_DBG,
5188 "CAM full no space left for multicast MAC\n");
5189 return FAILURE;
5190 }
5191 /* Update the internal structure with this new mac address */
5192 do_s2io_copy_mac_addr(sp, i, mac_addr);
5193
5194 return do_s2io_add_mac(sp, mac_addr, i);
5195 }
5196
5197 /* add MAC address to CAM */
5198 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5199 {
5200 u64 val64;
5201 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5202
5203 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5204 &bar0->rmac_addr_data0_mem);
5205
5206 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5207 RMAC_ADDR_CMD_MEM_OFFSET(off);
5208 writeq(val64, &bar0->rmac_addr_cmd_mem);
5209
5210 /* Wait till command completes */
5211 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5212 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5213 S2IO_BIT_RESET)) {
5214 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5215 return FAILURE;
5216 }
5217 return SUCCESS;
5218 }
5219 /* deletes a specified unicast/multicast mac entry from CAM */
5220 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5221 {
5222 int offset;
5223 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5224 struct config_param *config = &sp->config;
5225
5226 for (offset = 1;
5227 offset < config->max_mc_addr; offset++) {
5228 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5229 if (tmp64 == addr) {
5230 /* disable the entry by writing 0xffffffffffffULL */
5231 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5232 return FAILURE;
5233 /* store the new mac list from CAM */
5234 do_s2io_store_unicast_mc(sp);
5235 return SUCCESS;
5236 }
5237 }
5238 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5239 (unsigned long long)addr);
5240 return FAILURE;
5241 }
5242
5243 /* read mac entries from CAM */
5244 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5245 {
5246 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5247 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5248
5249 /* read mac addr */
5250 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5251 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5252 writeq(val64, &bar0->rmac_addr_cmd_mem);
5253
5254 /* Wait till command completes */
5255 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5256 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5257 S2IO_BIT_RESET)) {
5258 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5259 return FAILURE;
5260 }
5261 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5262
5263 return tmp64 >> 16;
5264 }
5265
5266 /**
5267 * s2io_set_mac_addr driver entry point
5268 */
5269
5270 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5271 {
5272 struct sockaddr *addr = p;
5273
5274 if (!is_valid_ether_addr(addr->sa_data))
5275 return -EINVAL;
5276
5277 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5278
5279 /* store the MAC address in CAM */
5280 return do_s2io_prog_unicast(dev, dev->dev_addr);
5281 }
5282 /**
5283 * do_s2io_prog_unicast - Programs the Xframe mac address
5284 * @dev : pointer to the device structure.
5285 * @addr: a uchar pointer to the new mac address which is to be set.
5286 * Description : This procedure will program the Xframe to receive
5287 * frames with new Mac Address
5288 * Return value: SUCCESS on success and an appropriate (-)ve integer
5289 * as defined in errno.h file on failure.
5290 */
5291
5292 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5293 {
5294 struct s2io_nic *sp = netdev_priv(dev);
5295 register u64 mac_addr = 0, perm_addr = 0;
5296 int i;
5297 u64 tmp64;
5298 struct config_param *config = &sp->config;
5299
5300 /*
5301 * Set the new MAC address as the new unicast filter and reflect this
5302 * change on the device address registered with the OS. It will be
5303 * at offset 0.
5304 */
5305 for (i = 0; i < ETH_ALEN; i++) {
5306 mac_addr <<= 8;
5307 mac_addr |= addr[i];
5308 perm_addr <<= 8;
5309 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5310 }
5311
5312 /* check if the dev_addr is different than perm_addr */
5313 if (mac_addr == perm_addr)
5314 return SUCCESS;
5315
5316 /* check if the mac already preset in CAM */
5317 for (i = 1; i < config->max_mac_addr; i++) {
5318 tmp64 = do_s2io_read_unicast_mc(sp, i);
5319 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5320 break;
5321
5322 if (tmp64 == mac_addr) {
5323 DBG_PRINT(INFO_DBG,
5324 "MAC addr:0x%llx already present in CAM\n",
5325 (unsigned long long)mac_addr);
5326 return SUCCESS;
5327 }
5328 }
5329 if (i == config->max_mac_addr) {
5330 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5331 return FAILURE;
5332 }
5333 /* Update the internal structure with this new mac address */
5334 do_s2io_copy_mac_addr(sp, i, mac_addr);
5335
5336 return do_s2io_add_mac(sp, mac_addr, i);
5337 }
5338
5339 /**
5340 * s2io_ethtool_sset - Sets different link parameters.
5341 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5342 * @info: pointer to the structure with parameters given by ethtool to set
5343 * link information.
5344 * Description:
5345 * The function sets different link parameters provided by the user onto
5346 * the NIC.
5347 * Return value:
5348 * 0 on success.
5349 */
5350
5351 static int s2io_ethtool_sset(struct net_device *dev,
5352 struct ethtool_cmd *info)
5353 {
5354 struct s2io_nic *sp = netdev_priv(dev);
5355 if ((info->autoneg == AUTONEG_ENABLE) ||
5356 (info->speed != SPEED_10000) ||
5357 (info->duplex != DUPLEX_FULL))
5358 return -EINVAL;
5359 else {
5360 s2io_close(sp->dev);
5361 s2io_open(sp->dev);
5362 }
5363
5364 return 0;
5365 }
5366
5367 /**
5368 * s2io_ethtol_gset - Return link specific information.
5369 * @sp : private member of the device structure, pointer to the
5370 * s2io_nic structure.
5371 * @info : pointer to the structure with parameters given by ethtool
5372 * to return link information.
5373 * Description:
5374 * Returns link specific information like speed, duplex etc.. to ethtool.
5375 * Return value :
5376 * return 0 on success.
5377 */
5378
5379 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5380 {
5381 struct s2io_nic *sp = netdev_priv(dev);
5382 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5383 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5384 info->port = PORT_FIBRE;
5385
5386 /* info->transceiver */
5387 info->transceiver = XCVR_EXTERNAL;
5388
5389 if (netif_carrier_ok(sp->dev)) {
5390 info->speed = 10000;
5391 info->duplex = DUPLEX_FULL;
5392 } else {
5393 info->speed = -1;
5394 info->duplex = -1;
5395 }
5396
5397 info->autoneg = AUTONEG_DISABLE;
5398 return 0;
5399 }
5400
5401 /**
5402 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5403 * @sp : private member of the device structure, which is a pointer to the
5404 * s2io_nic structure.
5405 * @info : pointer to the structure with parameters given by ethtool to
5406 * return driver information.
5407 * Description:
5408 * Returns driver specefic information like name, version etc.. to ethtool.
5409 * Return value:
5410 * void
5411 */
5412
5413 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5414 struct ethtool_drvinfo *info)
5415 {
5416 struct s2io_nic *sp = netdev_priv(dev);
5417
5418 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5419 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5420 strncpy(info->fw_version, "", sizeof(info->fw_version));
5421 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5422 info->regdump_len = XENA_REG_SPACE;
5423 info->eedump_len = XENA_EEPROM_SPACE;
5424 }
5425
5426 /**
5427 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5428 * @sp: private member of the device structure, which is a pointer to the
5429 * s2io_nic structure.
5430 * @regs : pointer to the structure with parameters given by ethtool for
5431 * dumping the registers.
5432 * @reg_space: The input argumnet into which all the registers are dumped.
5433 * Description:
5434 * Dumps the entire register space of xFrame NIC into the user given
5435 * buffer area.
5436 * Return value :
5437 * void .
5438 */
5439
5440 static void s2io_ethtool_gregs(struct net_device *dev,
5441 struct ethtool_regs *regs, void *space)
5442 {
5443 int i;
5444 u64 reg;
5445 u8 *reg_space = (u8 *)space;
5446 struct s2io_nic *sp = netdev_priv(dev);
5447
5448 regs->len = XENA_REG_SPACE;
5449 regs->version = sp->pdev->subsystem_device;
5450
5451 for (i = 0; i < regs->len; i += 8) {
5452 reg = readq(sp->bar0 + i);
5453 memcpy((reg_space + i), &reg, 8);
5454 }
5455 }
5456
5457 /**
5458 * s2io_phy_id - timer function that alternates adapter LED.
5459 * @data : address of the private member of the device structure, which
5460 * is a pointer to the s2io_nic structure, provided as an u32.
5461 * Description: This is actually the timer function that alternates the
5462 * adapter LED bit of the adapter control bit to set/reset every time on
5463 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5464 * once every second.
5465 */
5466 static void s2io_phy_id(unsigned long data)
5467 {
5468 struct s2io_nic *sp = (struct s2io_nic *)data;
5469 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5470 u64 val64 = 0;
5471 u16 subid;
5472
5473 subid = sp->pdev->subsystem_device;
5474 if ((sp->device_type == XFRAME_II_DEVICE) ||
5475 ((subid & 0xFF) >= 0x07)) {
5476 val64 = readq(&bar0->gpio_control);
5477 val64 ^= GPIO_CTRL_GPIO_0;
5478 writeq(val64, &bar0->gpio_control);
5479 } else {
5480 val64 = readq(&bar0->adapter_control);
5481 val64 ^= ADAPTER_LED_ON;
5482 writeq(val64, &bar0->adapter_control);
5483 }
5484
5485 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5486 }
5487
5488 /**
5489 * s2io_ethtool_idnic - To physically identify the nic on the system.
5490 * @sp : private member of the device structure, which is a pointer to the
5491 * s2io_nic structure.
5492 * @id : pointer to the structure with identification parameters given by
5493 * ethtool.
5494 * Description: Used to physically identify the NIC on the system.
5495 * The Link LED will blink for a time specified by the user for
5496 * identification.
5497 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5498 * identification is possible only if it's link is up.
5499 * Return value:
5500 * int , returns 0 on success
5501 */
5502
5503 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5504 {
5505 u64 val64 = 0, last_gpio_ctrl_val;
5506 struct s2io_nic *sp = netdev_priv(dev);
5507 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5508 u16 subid;
5509
5510 subid = sp->pdev->subsystem_device;
5511 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5512 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5513 val64 = readq(&bar0->adapter_control);
5514 if (!(val64 & ADAPTER_CNTL_EN)) {
5515 pr_err("Adapter Link down, cannot blink LED\n");
5516 return -EFAULT;
5517 }
5518 }
5519 if (sp->id_timer.function == NULL) {
5520 init_timer(&sp->id_timer);
5521 sp->id_timer.function = s2io_phy_id;
5522 sp->id_timer.data = (unsigned long)sp;
5523 }
5524 mod_timer(&sp->id_timer, jiffies);
5525 if (data)
5526 msleep_interruptible(data * HZ);
5527 else
5528 msleep_interruptible(MAX_FLICKER_TIME);
5529 del_timer_sync(&sp->id_timer);
5530
5531 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5532 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5533 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5534 }
5535
5536 return 0;
5537 }
5538
5539 static void s2io_ethtool_gringparam(struct net_device *dev,
5540 struct ethtool_ringparam *ering)
5541 {
5542 struct s2io_nic *sp = netdev_priv(dev);
5543 int i, tx_desc_count = 0, rx_desc_count = 0;
5544
5545 if (sp->rxd_mode == RXD_MODE_1)
5546 ering->rx_max_pending = MAX_RX_DESC_1;
5547 else if (sp->rxd_mode == RXD_MODE_3B)
5548 ering->rx_max_pending = MAX_RX_DESC_2;
5549
5550 ering->tx_max_pending = MAX_TX_DESC;
5551 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5552 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5553
5554 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5555 ering->tx_pending = tx_desc_count;
5556 rx_desc_count = 0;
5557 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5558 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5559
5560 ering->rx_pending = rx_desc_count;
5561
5562 ering->rx_mini_max_pending = 0;
5563 ering->rx_mini_pending = 0;
5564 if (sp->rxd_mode == RXD_MODE_1)
5565 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5566 else if (sp->rxd_mode == RXD_MODE_3B)
5567 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5568 ering->rx_jumbo_pending = rx_desc_count;
5569 }
5570
5571 /**
5572 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5573 * @sp : private member of the device structure, which is a pointer to the
5574 * s2io_nic structure.
5575 * @ep : pointer to the structure with pause parameters given by ethtool.
5576 * Description:
5577 * Returns the Pause frame generation and reception capability of the NIC.
5578 * Return value:
5579 * void
5580 */
5581 static void s2io_ethtool_getpause_data(struct net_device *dev,
5582 struct ethtool_pauseparam *ep)
5583 {
5584 u64 val64;
5585 struct s2io_nic *sp = netdev_priv(dev);
5586 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5587
5588 val64 = readq(&bar0->rmac_pause_cfg);
5589 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5590 ep->tx_pause = true;
5591 if (val64 & RMAC_PAUSE_RX_ENABLE)
5592 ep->rx_pause = true;
5593 ep->autoneg = false;
5594 }
5595
5596 /**
5597 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5598 * @sp : private member of the device structure, which is a pointer to the
5599 * s2io_nic structure.
5600 * @ep : pointer to the structure with pause parameters given by ethtool.
5601 * Description:
5602 * It can be used to set or reset Pause frame generation or reception
5603 * support of the NIC.
5604 * Return value:
5605 * int, returns 0 on Success
5606 */
5607
5608 static int s2io_ethtool_setpause_data(struct net_device *dev,
5609 struct ethtool_pauseparam *ep)
5610 {
5611 u64 val64;
5612 struct s2io_nic *sp = netdev_priv(dev);
5613 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5614
5615 val64 = readq(&bar0->rmac_pause_cfg);
5616 if (ep->tx_pause)
5617 val64 |= RMAC_PAUSE_GEN_ENABLE;
5618 else
5619 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5620 if (ep->rx_pause)
5621 val64 |= RMAC_PAUSE_RX_ENABLE;
5622 else
5623 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5624 writeq(val64, &bar0->rmac_pause_cfg);
5625 return 0;
5626 }
5627
5628 /**
5629 * read_eeprom - reads 4 bytes of data from user given offset.
5630 * @sp : private member of the device structure, which is a pointer to the
5631 * s2io_nic structure.
5632 * @off : offset at which the data must be written
5633 * @data : Its an output parameter where the data read at the given
5634 * offset is stored.
5635 * Description:
5636 * Will read 4 bytes of data from the user given offset and return the
5637 * read data.
5638 * NOTE: Will allow to read only part of the EEPROM visible through the
5639 * I2C bus.
5640 * Return value:
5641 * -1 on failure and 0 on success.
5642 */
5643
5644 #define S2IO_DEV_ID 5
5645 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5646 {
5647 int ret = -1;
5648 u32 exit_cnt = 0;
5649 u64 val64;
5650 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5651
5652 if (sp->device_type == XFRAME_I_DEVICE) {
5653 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5654 I2C_CONTROL_ADDR(off) |
5655 I2C_CONTROL_BYTE_CNT(0x3) |
5656 I2C_CONTROL_READ |
5657 I2C_CONTROL_CNTL_START;
5658 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5659
5660 while (exit_cnt < 5) {
5661 val64 = readq(&bar0->i2c_control);
5662 if (I2C_CONTROL_CNTL_END(val64)) {
5663 *data = I2C_CONTROL_GET_DATA(val64);
5664 ret = 0;
5665 break;
5666 }
5667 msleep(50);
5668 exit_cnt++;
5669 }
5670 }
5671
5672 if (sp->device_type == XFRAME_II_DEVICE) {
5673 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5674 SPI_CONTROL_BYTECNT(0x3) |
5675 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5676 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5677 val64 |= SPI_CONTROL_REQ;
5678 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5679 while (exit_cnt < 5) {
5680 val64 = readq(&bar0->spi_control);
5681 if (val64 & SPI_CONTROL_NACK) {
5682 ret = 1;
5683 break;
5684 } else if (val64 & SPI_CONTROL_DONE) {
5685 *data = readq(&bar0->spi_data);
5686 *data &= 0xffffff;
5687 ret = 0;
5688 break;
5689 }
5690 msleep(50);
5691 exit_cnt++;
5692 }
5693 }
5694 return ret;
5695 }
5696
5697 /**
5698 * write_eeprom - actually writes the relevant part of the data value.
5699 * @sp : private member of the device structure, which is a pointer to the
5700 * s2io_nic structure.
5701 * @off : offset at which the data must be written
5702 * @data : The data that is to be written
5703 * @cnt : Number of bytes of the data that are actually to be written into
5704 * the Eeprom. (max of 3)
5705 * Description:
5706 * Actually writes the relevant part of the data value into the Eeprom
5707 * through the I2C bus.
5708 * Return value:
5709 * 0 on success, -1 on failure.
5710 */
5711
5712 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5713 {
5714 int exit_cnt = 0, ret = -1;
5715 u64 val64;
5716 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5717
5718 if (sp->device_type == XFRAME_I_DEVICE) {
5719 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5720 I2C_CONTROL_ADDR(off) |
5721 I2C_CONTROL_BYTE_CNT(cnt) |
5722 I2C_CONTROL_SET_DATA((u32)data) |
5723 I2C_CONTROL_CNTL_START;
5724 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5725
5726 while (exit_cnt < 5) {
5727 val64 = readq(&bar0->i2c_control);
5728 if (I2C_CONTROL_CNTL_END(val64)) {
5729 if (!(val64 & I2C_CONTROL_NACK))
5730 ret = 0;
5731 break;
5732 }
5733 msleep(50);
5734 exit_cnt++;
5735 }
5736 }
5737
5738 if (sp->device_type == XFRAME_II_DEVICE) {
5739 int write_cnt = (cnt == 8) ? 0 : cnt;
5740 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5741
5742 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5743 SPI_CONTROL_BYTECNT(write_cnt) |
5744 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5745 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5746 val64 |= SPI_CONTROL_REQ;
5747 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5748 while (exit_cnt < 5) {
5749 val64 = readq(&bar0->spi_control);
5750 if (val64 & SPI_CONTROL_NACK) {
5751 ret = 1;
5752 break;
5753 } else if (val64 & SPI_CONTROL_DONE) {
5754 ret = 0;
5755 break;
5756 }
5757 msleep(50);
5758 exit_cnt++;
5759 }
5760 }
5761 return ret;
5762 }
5763 static void s2io_vpd_read(struct s2io_nic *nic)
5764 {
5765 u8 *vpd_data;
5766 u8 data;
5767 int i = 0, cnt, fail = 0;
5768 int vpd_addr = 0x80;
5769 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5770
5771 if (nic->device_type == XFRAME_II_DEVICE) {
5772 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5773 vpd_addr = 0x80;
5774 } else {
5775 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5776 vpd_addr = 0x50;
5777 }
5778 strcpy(nic->serial_num, "NOT AVAILABLE");
5779
5780 vpd_data = kmalloc(256, GFP_KERNEL);
5781 if (!vpd_data) {
5782 swstats->mem_alloc_fail_cnt++;
5783 return;
5784 }
5785 swstats->mem_allocated += 256;
5786
5787 for (i = 0; i < 256; i += 4) {
5788 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5789 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5790 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5791 for (cnt = 0; cnt < 5; cnt++) {
5792 msleep(2);
5793 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5794 if (data == 0x80)
5795 break;
5796 }
5797 if (cnt >= 5) {
5798 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5799 fail = 1;
5800 break;
5801 }
5802 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5803 (u32 *)&vpd_data[i]);
5804 }
5805
5806 if (!fail) {
5807 /* read serial number of adapter */
5808 for (cnt = 0; cnt < 256; cnt++) {
5809 if ((vpd_data[cnt] == 'S') &&
5810 (vpd_data[cnt+1] == 'N') &&
5811 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5812 memset(nic->serial_num, 0, VPD_STRING_LEN);
5813 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5814 vpd_data[cnt+2]);
5815 break;
5816 }
5817 }
5818 }
5819
5820 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5821 memset(nic->product_name, 0, vpd_data[1]);
5822 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5823 }
5824 kfree(vpd_data);
5825 swstats->mem_freed += 256;
5826 }
5827
5828 /**
5829 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5830 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5831 * @eeprom : pointer to the user level structure provided by ethtool,
5832 * containing all relevant information.
5833 * @data_buf : user defined value to be written into Eeprom.
5834 * Description: Reads the values stored in the Eeprom at given offset
5835 * for a given length. Stores these values int the input argument data
5836 * buffer 'data_buf' and returns these to the caller (ethtool.)
5837 * Return value:
5838 * int 0 on success
5839 */
5840
5841 static int s2io_ethtool_geeprom(struct net_device *dev,
5842 struct ethtool_eeprom *eeprom, u8 * data_buf)
5843 {
5844 u32 i, valid;
5845 u64 data;
5846 struct s2io_nic *sp = netdev_priv(dev);
5847
5848 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5849
5850 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5851 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5852
5853 for (i = 0; i < eeprom->len; i += 4) {
5854 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5855 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5856 return -EFAULT;
5857 }
5858 valid = INV(data);
5859 memcpy((data_buf + i), &valid, 4);
5860 }
5861 return 0;
5862 }
5863
5864 /**
5865 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5866 * @sp : private member of the device structure, which is a pointer to the
5867 * s2io_nic structure.
5868 * @eeprom : pointer to the user level structure provided by ethtool,
5869 * containing all relevant information.
5870 * @data_buf ; user defined value to be written into Eeprom.
5871 * Description:
5872 * Tries to write the user provided value in the Eeprom, at the offset
5873 * given by the user.
5874 * Return value:
5875 * 0 on success, -EFAULT on failure.
5876 */
5877
5878 static int s2io_ethtool_seeprom(struct net_device *dev,
5879 struct ethtool_eeprom *eeprom,
5880 u8 *data_buf)
5881 {
5882 int len = eeprom->len, cnt = 0;
5883 u64 valid = 0, data;
5884 struct s2io_nic *sp = netdev_priv(dev);
5885
5886 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5887 DBG_PRINT(ERR_DBG,
5888 "ETHTOOL_WRITE_EEPROM Err: "
5889 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5890 (sp->pdev->vendor | (sp->pdev->device << 16)),
5891 eeprom->magic);
5892 return -EFAULT;
5893 }
5894
5895 while (len) {
5896 data = (u32)data_buf[cnt] & 0x000000FF;
5897 if (data)
5898 valid = (u32)(data << 24);
5899 else
5900 valid = data;
5901
5902 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5903 DBG_PRINT(ERR_DBG,
5904 "ETHTOOL_WRITE_EEPROM Err: "
5905 "Cannot write into the specified offset\n");
5906 return -EFAULT;
5907 }
5908 cnt++;
5909 len--;
5910 }
5911
5912 return 0;
5913 }
5914
5915 /**
5916 * s2io_register_test - reads and writes into all clock domains.
5917 * @sp : private member of the device structure, which is a pointer to the
5918 * s2io_nic structure.
5919 * @data : variable that returns the result of each of the test conducted b
5920 * by the driver.
5921 * Description:
5922 * Read and write into all clock domains. The NIC has 3 clock domains,
5923 * see that registers in all the three regions are accessible.
5924 * Return value:
5925 * 0 on success.
5926 */
5927
5928 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5929 {
5930 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5931 u64 val64 = 0, exp_val;
5932 int fail = 0;
5933
5934 val64 = readq(&bar0->pif_rd_swapper_fb);
5935 if (val64 != 0x123456789abcdefULL) {
5936 fail = 1;
5937 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5938 }
5939
5940 val64 = readq(&bar0->rmac_pause_cfg);
5941 if (val64 != 0xc000ffff00000000ULL) {
5942 fail = 1;
5943 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5944 }
5945
5946 val64 = readq(&bar0->rx_queue_cfg);
5947 if (sp->device_type == XFRAME_II_DEVICE)
5948 exp_val = 0x0404040404040404ULL;
5949 else
5950 exp_val = 0x0808080808080808ULL;
5951 if (val64 != exp_val) {
5952 fail = 1;
5953 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5954 }
5955
5956 val64 = readq(&bar0->xgxs_efifo_cfg);
5957 if (val64 != 0x000000001923141EULL) {
5958 fail = 1;
5959 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5960 }
5961
5962 val64 = 0x5A5A5A5A5A5A5A5AULL;
5963 writeq(val64, &bar0->xmsi_data);
5964 val64 = readq(&bar0->xmsi_data);
5965 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5966 fail = 1;
5967 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5968 }
5969
5970 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5971 writeq(val64, &bar0->xmsi_data);
5972 val64 = readq(&bar0->xmsi_data);
5973 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5974 fail = 1;
5975 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5976 }
5977
5978 *data = fail;
5979 return fail;
5980 }
5981
5982 /**
5983 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5984 * @sp : private member of the device structure, which is a pointer to the
5985 * s2io_nic structure.
5986 * @data:variable that returns the result of each of the test conducted by
5987 * the driver.
5988 * Description:
5989 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5990 * register.
5991 * Return value:
5992 * 0 on success.
5993 */
5994
5995 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5996 {
5997 int fail = 0;
5998 u64 ret_data, org_4F0, org_7F0;
5999 u8 saved_4F0 = 0, saved_7F0 = 0;
6000 struct net_device *dev = sp->dev;
6001
6002 /* Test Write Error at offset 0 */
6003 /* Note that SPI interface allows write access to all areas
6004 * of EEPROM. Hence doing all negative testing only for Xframe I.
6005 */
6006 if (sp->device_type == XFRAME_I_DEVICE)
6007 if (!write_eeprom(sp, 0, 0, 3))
6008 fail = 1;
6009
6010 /* Save current values at offsets 0x4F0 and 0x7F0 */
6011 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6012 saved_4F0 = 1;
6013 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6014 saved_7F0 = 1;
6015
6016 /* Test Write at offset 4f0 */
6017 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6018 fail = 1;
6019 if (read_eeprom(sp, 0x4F0, &ret_data))
6020 fail = 1;
6021
6022 if (ret_data != 0x012345) {
6023 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6024 "Data written %llx Data read %llx\n",
6025 dev->name, (unsigned long long)0x12345,
6026 (unsigned long long)ret_data);
6027 fail = 1;
6028 }
6029
6030 /* Reset the EEPROM data go FFFF */
6031 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6032
6033 /* Test Write Request Error at offset 0x7c */
6034 if (sp->device_type == XFRAME_I_DEVICE)
6035 if (!write_eeprom(sp, 0x07C, 0, 3))
6036 fail = 1;
6037
6038 /* Test Write Request at offset 0x7f0 */
6039 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6040 fail = 1;
6041 if (read_eeprom(sp, 0x7F0, &ret_data))
6042 fail = 1;
6043
6044 if (ret_data != 0x012345) {
6045 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6046 "Data written %llx Data read %llx\n",
6047 dev->name, (unsigned long long)0x12345,
6048 (unsigned long long)ret_data);
6049 fail = 1;
6050 }
6051
6052 /* Reset the EEPROM data go FFFF */
6053 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6054
6055 if (sp->device_type == XFRAME_I_DEVICE) {
6056 /* Test Write Error at offset 0x80 */
6057 if (!write_eeprom(sp, 0x080, 0, 3))
6058 fail = 1;
6059
6060 /* Test Write Error at offset 0xfc */
6061 if (!write_eeprom(sp, 0x0FC, 0, 3))
6062 fail = 1;
6063
6064 /* Test Write Error at offset 0x100 */
6065 if (!write_eeprom(sp, 0x100, 0, 3))
6066 fail = 1;
6067
6068 /* Test Write Error at offset 4ec */
6069 if (!write_eeprom(sp, 0x4EC, 0, 3))
6070 fail = 1;
6071 }
6072
6073 /* Restore values at offsets 0x4F0 and 0x7F0 */
6074 if (saved_4F0)
6075 write_eeprom(sp, 0x4F0, org_4F0, 3);
6076 if (saved_7F0)
6077 write_eeprom(sp, 0x7F0, org_7F0, 3);
6078
6079 *data = fail;
6080 return fail;
6081 }
6082
6083 /**
6084 * s2io_bist_test - invokes the MemBist test of the card .
6085 * @sp : private member of the device structure, which is a pointer to the
6086 * s2io_nic structure.
6087 * @data:variable that returns the result of each of the test conducted by
6088 * the driver.
6089 * Description:
6090 * This invokes the MemBist test of the card. We give around
6091 * 2 secs time for the Test to complete. If it's still not complete
6092 * within this peiod, we consider that the test failed.
6093 * Return value:
6094 * 0 on success and -1 on failure.
6095 */
6096
6097 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6098 {
6099 u8 bist = 0;
6100 int cnt = 0, ret = -1;
6101
6102 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6103 bist |= PCI_BIST_START;
6104 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6105
6106 while (cnt < 20) {
6107 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6108 if (!(bist & PCI_BIST_START)) {
6109 *data = (bist & PCI_BIST_CODE_MASK);
6110 ret = 0;
6111 break;
6112 }
6113 msleep(100);
6114 cnt++;
6115 }
6116
6117 return ret;
6118 }
6119
6120 /**
6121 * s2io-link_test - verifies the link state of the nic
6122 * @sp ; private member of the device structure, which is a pointer to the
6123 * s2io_nic structure.
6124 * @data: variable that returns the result of each of the test conducted by
6125 * the driver.
6126 * Description:
6127 * The function verifies the link state of the NIC and updates the input
6128 * argument 'data' appropriately.
6129 * Return value:
6130 * 0 on success.
6131 */
6132
6133 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6134 {
6135 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6136 u64 val64;
6137
6138 val64 = readq(&bar0->adapter_status);
6139 if (!(LINK_IS_UP(val64)))
6140 *data = 1;
6141 else
6142 *data = 0;
6143
6144 return *data;
6145 }
6146
6147 /**
6148 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6149 * @sp - private member of the device structure, which is a pointer to the
6150 * s2io_nic structure.
6151 * @data - variable that returns the result of each of the test
6152 * conducted by the driver.
6153 * Description:
6154 * This is one of the offline test that tests the read and write
6155 * access to the RldRam chip on the NIC.
6156 * Return value:
6157 * 0 on success.
6158 */
6159
6160 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6161 {
6162 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6163 u64 val64;
6164 int cnt, iteration = 0, test_fail = 0;
6165
6166 val64 = readq(&bar0->adapter_control);
6167 val64 &= ~ADAPTER_ECC_EN;
6168 writeq(val64, &bar0->adapter_control);
6169
6170 val64 = readq(&bar0->mc_rldram_test_ctrl);
6171 val64 |= MC_RLDRAM_TEST_MODE;
6172 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6173
6174 val64 = readq(&bar0->mc_rldram_mrs);
6175 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6176 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6177
6178 val64 |= MC_RLDRAM_MRS_ENABLE;
6179 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6180
6181 while (iteration < 2) {
6182 val64 = 0x55555555aaaa0000ULL;
6183 if (iteration == 1)
6184 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6185 writeq(val64, &bar0->mc_rldram_test_d0);
6186
6187 val64 = 0xaaaa5a5555550000ULL;
6188 if (iteration == 1)
6189 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6190 writeq(val64, &bar0->mc_rldram_test_d1);
6191
6192 val64 = 0x55aaaaaaaa5a0000ULL;
6193 if (iteration == 1)
6194 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6195 writeq(val64, &bar0->mc_rldram_test_d2);
6196
6197 val64 = (u64) (0x0000003ffffe0100ULL);
6198 writeq(val64, &bar0->mc_rldram_test_add);
6199
6200 val64 = MC_RLDRAM_TEST_MODE |
6201 MC_RLDRAM_TEST_WRITE |
6202 MC_RLDRAM_TEST_GO;
6203 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6204
6205 for (cnt = 0; cnt < 5; cnt++) {
6206 val64 = readq(&bar0->mc_rldram_test_ctrl);
6207 if (val64 & MC_RLDRAM_TEST_DONE)
6208 break;
6209 msleep(200);
6210 }
6211
6212 if (cnt == 5)
6213 break;
6214
6215 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6216 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6217
6218 for (cnt = 0; cnt < 5; cnt++) {
6219 val64 = readq(&bar0->mc_rldram_test_ctrl);
6220 if (val64 & MC_RLDRAM_TEST_DONE)
6221 break;
6222 msleep(500);
6223 }
6224
6225 if (cnt == 5)
6226 break;
6227
6228 val64 = readq(&bar0->mc_rldram_test_ctrl);
6229 if (!(val64 & MC_RLDRAM_TEST_PASS))
6230 test_fail = 1;
6231
6232 iteration++;
6233 }
6234
6235 *data = test_fail;
6236
6237 /* Bring the adapter out of test mode */
6238 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6239
6240 return test_fail;
6241 }
6242
6243 /**
6244 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6245 * @sp : private member of the device structure, which is a pointer to the
6246 * s2io_nic structure.
6247 * @ethtest : pointer to a ethtool command specific structure that will be
6248 * returned to the user.
6249 * @data : variable that returns the result of each of the test
6250 * conducted by the driver.
6251 * Description:
6252 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6253 * the health of the card.
6254 * Return value:
6255 * void
6256 */
6257
6258 static void s2io_ethtool_test(struct net_device *dev,
6259 struct ethtool_test *ethtest,
6260 uint64_t *data)
6261 {
6262 struct s2io_nic *sp = netdev_priv(dev);
6263 int orig_state = netif_running(sp->dev);
6264
6265 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6266 /* Offline Tests. */
6267 if (orig_state)
6268 s2io_close(sp->dev);
6269
6270 if (s2io_register_test(sp, &data[0]))
6271 ethtest->flags |= ETH_TEST_FL_FAILED;
6272
6273 s2io_reset(sp);
6274
6275 if (s2io_rldram_test(sp, &data[3]))
6276 ethtest->flags |= ETH_TEST_FL_FAILED;
6277
6278 s2io_reset(sp);
6279
6280 if (s2io_eeprom_test(sp, &data[1]))
6281 ethtest->flags |= ETH_TEST_FL_FAILED;
6282
6283 if (s2io_bist_test(sp, &data[4]))
6284 ethtest->flags |= ETH_TEST_FL_FAILED;
6285
6286 if (orig_state)
6287 s2io_open(sp->dev);
6288
6289 data[2] = 0;
6290 } else {
6291 /* Online Tests. */
6292 if (!orig_state) {
6293 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6294 dev->name);
6295 data[0] = -1;
6296 data[1] = -1;
6297 data[2] = -1;
6298 data[3] = -1;
6299 data[4] = -1;
6300 }
6301
6302 if (s2io_link_test(sp, &data[2]))
6303 ethtest->flags |= ETH_TEST_FL_FAILED;
6304
6305 data[0] = 0;
6306 data[1] = 0;
6307 data[3] = 0;
6308 data[4] = 0;
6309 }
6310 }
6311
6312 static void s2io_get_ethtool_stats(struct net_device *dev,
6313 struct ethtool_stats *estats,
6314 u64 *tmp_stats)
6315 {
6316 int i = 0, k;
6317 struct s2io_nic *sp = netdev_priv(dev);
6318 struct stat_block *stats = sp->mac_control.stats_info;
6319 struct swStat *swstats = &stats->sw_stat;
6320 struct xpakStat *xstats = &stats->xpak_stat;
6321
6322 s2io_updt_stats(sp);
6323 tmp_stats[i++] =
6324 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6325 le32_to_cpu(stats->tmac_frms);
6326 tmp_stats[i++] =
6327 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6328 le32_to_cpu(stats->tmac_data_octets);
6329 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6330 tmp_stats[i++] =
6331 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6332 le32_to_cpu(stats->tmac_mcst_frms);
6333 tmp_stats[i++] =
6334 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6335 le32_to_cpu(stats->tmac_bcst_frms);
6336 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6337 tmp_stats[i++] =
6338 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6339 le32_to_cpu(stats->tmac_ttl_octets);
6340 tmp_stats[i++] =
6341 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6342 le32_to_cpu(stats->tmac_ucst_frms);
6343 tmp_stats[i++] =
6344 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6345 le32_to_cpu(stats->tmac_nucst_frms);
6346 tmp_stats[i++] =
6347 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6348 le32_to_cpu(stats->tmac_any_err_frms);
6349 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6350 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6351 tmp_stats[i++] =
6352 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6353 le32_to_cpu(stats->tmac_vld_ip);
6354 tmp_stats[i++] =
6355 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6356 le32_to_cpu(stats->tmac_drop_ip);
6357 tmp_stats[i++] =
6358 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6359 le32_to_cpu(stats->tmac_icmp);
6360 tmp_stats[i++] =
6361 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6362 le32_to_cpu(stats->tmac_rst_tcp);
6363 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6364 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6365 le32_to_cpu(stats->tmac_udp);
6366 tmp_stats[i++] =
6367 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6368 le32_to_cpu(stats->rmac_vld_frms);
6369 tmp_stats[i++] =
6370 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6371 le32_to_cpu(stats->rmac_data_octets);
6372 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6373 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6374 tmp_stats[i++] =
6375 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6376 le32_to_cpu(stats->rmac_vld_mcst_frms);
6377 tmp_stats[i++] =
6378 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6379 le32_to_cpu(stats->rmac_vld_bcst_frms);
6380 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6381 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6382 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6383 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6384 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6385 tmp_stats[i++] =
6386 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6387 le32_to_cpu(stats->rmac_ttl_octets);
6388 tmp_stats[i++] =
6389 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6390 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6391 tmp_stats[i++] =
6392 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6393 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6394 tmp_stats[i++] =
6395 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6396 le32_to_cpu(stats->rmac_discarded_frms);
6397 tmp_stats[i++] =
6398 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6399 << 32 | le32_to_cpu(stats->rmac_drop_events);
6400 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6401 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6402 tmp_stats[i++] =
6403 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6404 le32_to_cpu(stats->rmac_usized_frms);
6405 tmp_stats[i++] =
6406 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6407 le32_to_cpu(stats->rmac_osized_frms);
6408 tmp_stats[i++] =
6409 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6410 le32_to_cpu(stats->rmac_frag_frms);
6411 tmp_stats[i++] =
6412 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6413 le32_to_cpu(stats->rmac_jabber_frms);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6418 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6419 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6420 tmp_stats[i++] =
6421 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6422 le32_to_cpu(stats->rmac_ip);
6423 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6424 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6425 tmp_stats[i++] =
6426 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6427 le32_to_cpu(stats->rmac_drop_ip);
6428 tmp_stats[i++] =
6429 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6430 le32_to_cpu(stats->rmac_icmp);
6431 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6432 tmp_stats[i++] =
6433 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6434 le32_to_cpu(stats->rmac_udp);
6435 tmp_stats[i++] =
6436 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6437 le32_to_cpu(stats->rmac_err_drp_udp);
6438 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6439 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6440 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6446 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6447 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6448 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6449 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6450 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6451 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6452 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6453 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6454 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6455 tmp_stats[i++] =
6456 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6457 le32_to_cpu(stats->rmac_pause_cnt);
6458 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6459 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6460 tmp_stats[i++] =
6461 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6462 le32_to_cpu(stats->rmac_accepted_ip);
6463 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6464 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6465 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6467 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6468 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6469 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6470 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6471 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6472 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6473 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6474 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6477 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6480 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6481 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6482
6483 /* Enhanced statistics exist only for Hercules */
6484 if (sp->device_type == XFRAME_II_DEVICE) {
6485 tmp_stats[i++] =
6486 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6487 tmp_stats[i++] =
6488 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6489 tmp_stats[i++] =
6490 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6491 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6492 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6493 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6494 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6495 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6496 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6497 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6498 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6499 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6500 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6501 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6502 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6503 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6504 }
6505
6506 tmp_stats[i++] = 0;
6507 tmp_stats[i++] = swstats->single_ecc_errs;
6508 tmp_stats[i++] = swstats->double_ecc_errs;
6509 tmp_stats[i++] = swstats->parity_err_cnt;
6510 tmp_stats[i++] = swstats->serious_err_cnt;
6511 tmp_stats[i++] = swstats->soft_reset_cnt;
6512 tmp_stats[i++] = swstats->fifo_full_cnt;
6513 for (k = 0; k < MAX_RX_RINGS; k++)
6514 tmp_stats[i++] = swstats->ring_full_cnt[k];
6515 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6516 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6517 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6518 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6519 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6520 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6521 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6522 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6523 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6524 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6525 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6526 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6527 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6528 tmp_stats[i++] = swstats->sending_both;
6529 tmp_stats[i++] = swstats->outof_sequence_pkts;
6530 tmp_stats[i++] = swstats->flush_max_pkts;
6531 if (swstats->num_aggregations) {
6532 u64 tmp = swstats->sum_avg_pkts_aggregated;
6533 int count = 0;
6534 /*
6535 * Since 64-bit divide does not work on all platforms,
6536 * do repeated subtraction.
6537 */
6538 while (tmp >= swstats->num_aggregations) {
6539 tmp -= swstats->num_aggregations;
6540 count++;
6541 }
6542 tmp_stats[i++] = count;
6543 } else
6544 tmp_stats[i++] = 0;
6545 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6546 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6547 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6548 tmp_stats[i++] = swstats->mem_allocated;
6549 tmp_stats[i++] = swstats->mem_freed;
6550 tmp_stats[i++] = swstats->link_up_cnt;
6551 tmp_stats[i++] = swstats->link_down_cnt;
6552 tmp_stats[i++] = swstats->link_up_time;
6553 tmp_stats[i++] = swstats->link_down_time;
6554
6555 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6556 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6557 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6558 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6559 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6560
6561 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6562 tmp_stats[i++] = swstats->rx_abort_cnt;
6563 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6564 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6565 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6566 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6567 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6568 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6569 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6570 tmp_stats[i++] = swstats->tda_err_cnt;
6571 tmp_stats[i++] = swstats->pfc_err_cnt;
6572 tmp_stats[i++] = swstats->pcc_err_cnt;
6573 tmp_stats[i++] = swstats->tti_err_cnt;
6574 tmp_stats[i++] = swstats->tpa_err_cnt;
6575 tmp_stats[i++] = swstats->sm_err_cnt;
6576 tmp_stats[i++] = swstats->lso_err_cnt;
6577 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6578 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6579 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6580 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6581 tmp_stats[i++] = swstats->rc_err_cnt;
6582 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6583 tmp_stats[i++] = swstats->rpa_err_cnt;
6584 tmp_stats[i++] = swstats->rda_err_cnt;
6585 tmp_stats[i++] = swstats->rti_err_cnt;
6586 tmp_stats[i++] = swstats->mc_err_cnt;
6587 }
6588
6589 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6590 {
6591 return XENA_REG_SPACE;
6592 }
6593
6594
6595 static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
6596 {
6597 struct s2io_nic *sp = netdev_priv(dev);
6598
6599 return sp->rx_csum;
6600 }
6601
6602 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6603 {
6604 struct s2io_nic *sp = netdev_priv(dev);
6605
6606 if (data)
6607 sp->rx_csum = 1;
6608 else
6609 sp->rx_csum = 0;
6610
6611 return 0;
6612 }
6613
6614 static int s2io_get_eeprom_len(struct net_device *dev)
6615 {
6616 return XENA_EEPROM_SPACE;
6617 }
6618
6619 static int s2io_get_sset_count(struct net_device *dev, int sset)
6620 {
6621 struct s2io_nic *sp = netdev_priv(dev);
6622
6623 switch (sset) {
6624 case ETH_SS_TEST:
6625 return S2IO_TEST_LEN;
6626 case ETH_SS_STATS:
6627 switch (sp->device_type) {
6628 case XFRAME_I_DEVICE:
6629 return XFRAME_I_STAT_LEN;
6630 case XFRAME_II_DEVICE:
6631 return XFRAME_II_STAT_LEN;
6632 default:
6633 return 0;
6634 }
6635 default:
6636 return -EOPNOTSUPP;
6637 }
6638 }
6639
6640 static void s2io_ethtool_get_strings(struct net_device *dev,
6641 u32 stringset, u8 *data)
6642 {
6643 int stat_size = 0;
6644 struct s2io_nic *sp = netdev_priv(dev);
6645
6646 switch (stringset) {
6647 case ETH_SS_TEST:
6648 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6649 break;
6650 case ETH_SS_STATS:
6651 stat_size = sizeof(ethtool_xena_stats_keys);
6652 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6653 if (sp->device_type == XFRAME_II_DEVICE) {
6654 memcpy(data + stat_size,
6655 &ethtool_enhanced_stats_keys,
6656 sizeof(ethtool_enhanced_stats_keys));
6657 stat_size += sizeof(ethtool_enhanced_stats_keys);
6658 }
6659
6660 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6661 sizeof(ethtool_driver_stats_keys));
6662 }
6663 }
6664
6665 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6666 {
6667 if (data)
6668 dev->features |= NETIF_F_IP_CSUM;
6669 else
6670 dev->features &= ~NETIF_F_IP_CSUM;
6671
6672 return 0;
6673 }
6674
6675 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6676 {
6677 return (dev->features & NETIF_F_TSO) != 0;
6678 }
6679 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6680 {
6681 if (data)
6682 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6683 else
6684 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6685
6686 return 0;
6687 }
6688
6689 static const struct ethtool_ops netdev_ethtool_ops = {
6690 .get_settings = s2io_ethtool_gset,
6691 .set_settings = s2io_ethtool_sset,
6692 .get_drvinfo = s2io_ethtool_gdrvinfo,
6693 .get_regs_len = s2io_ethtool_get_regs_len,
6694 .get_regs = s2io_ethtool_gregs,
6695 .get_link = ethtool_op_get_link,
6696 .get_eeprom_len = s2io_get_eeprom_len,
6697 .get_eeprom = s2io_ethtool_geeprom,
6698 .set_eeprom = s2io_ethtool_seeprom,
6699 .get_ringparam = s2io_ethtool_gringparam,
6700 .get_pauseparam = s2io_ethtool_getpause_data,
6701 .set_pauseparam = s2io_ethtool_setpause_data,
6702 .get_rx_csum = s2io_ethtool_get_rx_csum,
6703 .set_rx_csum = s2io_ethtool_set_rx_csum,
6704 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6705 .set_sg = ethtool_op_set_sg,
6706 .get_tso = s2io_ethtool_op_get_tso,
6707 .set_tso = s2io_ethtool_op_set_tso,
6708 .set_ufo = ethtool_op_set_ufo,
6709 .self_test = s2io_ethtool_test,
6710 .get_strings = s2io_ethtool_get_strings,
6711 .phys_id = s2io_ethtool_idnic,
6712 .get_ethtool_stats = s2io_get_ethtool_stats,
6713 .get_sset_count = s2io_get_sset_count,
6714 };
6715
6716 /**
6717 * s2io_ioctl - Entry point for the Ioctl
6718 * @dev : Device pointer.
6719 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6720 * a proprietary structure used to pass information to the driver.
6721 * @cmd : This is used to distinguish between the different commands that
6722 * can be passed to the IOCTL functions.
6723 * Description:
6724 * Currently there are no special functionality supported in IOCTL, hence
6725 * function always return EOPNOTSUPPORTED
6726 */
6727
6728 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6729 {
6730 return -EOPNOTSUPP;
6731 }
6732
6733 /**
6734 * s2io_change_mtu - entry point to change MTU size for the device.
6735 * @dev : device pointer.
6736 * @new_mtu : the new MTU size for the device.
6737 * Description: A driver entry point to change MTU size for the device.
6738 * Before changing the MTU the device must be stopped.
6739 * Return value:
6740 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6741 * file on failure.
6742 */
6743
6744 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6745 {
6746 struct s2io_nic *sp = netdev_priv(dev);
6747 int ret = 0;
6748
6749 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6750 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6751 return -EPERM;
6752 }
6753
6754 dev->mtu = new_mtu;
6755 if (netif_running(dev)) {
6756 s2io_stop_all_tx_queue(sp);
6757 s2io_card_down(sp);
6758 ret = s2io_card_up(sp);
6759 if (ret) {
6760 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6761 __func__);
6762 return ret;
6763 }
6764 s2io_wake_all_tx_queue(sp);
6765 } else { /* Device is down */
6766 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6767 u64 val64 = new_mtu;
6768
6769 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6770 }
6771
6772 return ret;
6773 }
6774
6775 /**
6776 * s2io_set_link - Set the LInk status
6777 * @data: long pointer to device private structue
6778 * Description: Sets the link status for the adapter
6779 */
6780
6781 static void s2io_set_link(struct work_struct *work)
6782 {
6783 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6784 set_link_task);
6785 struct net_device *dev = nic->dev;
6786 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6787 register u64 val64;
6788 u16 subid;
6789
6790 rtnl_lock();
6791
6792 if (!netif_running(dev))
6793 goto out_unlock;
6794
6795 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6796 /* The card is being reset, no point doing anything */
6797 goto out_unlock;
6798 }
6799
6800 subid = nic->pdev->subsystem_device;
6801 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6802 /*
6803 * Allow a small delay for the NICs self initiated
6804 * cleanup to complete.
6805 */
6806 msleep(100);
6807 }
6808
6809 val64 = readq(&bar0->adapter_status);
6810 if (LINK_IS_UP(val64)) {
6811 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6812 if (verify_xena_quiescence(nic)) {
6813 val64 = readq(&bar0->adapter_control);
6814 val64 |= ADAPTER_CNTL_EN;
6815 writeq(val64, &bar0->adapter_control);
6816 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6817 nic->device_type, subid)) {
6818 val64 = readq(&bar0->gpio_control);
6819 val64 |= GPIO_CTRL_GPIO_0;
6820 writeq(val64, &bar0->gpio_control);
6821 val64 = readq(&bar0->gpio_control);
6822 } else {
6823 val64 |= ADAPTER_LED_ON;
6824 writeq(val64, &bar0->adapter_control);
6825 }
6826 nic->device_enabled_once = true;
6827 } else {
6828 DBG_PRINT(ERR_DBG,
6829 "%s: Error: device is not Quiescent\n",
6830 dev->name);
6831 s2io_stop_all_tx_queue(nic);
6832 }
6833 }
6834 val64 = readq(&bar0->adapter_control);
6835 val64 |= ADAPTER_LED_ON;
6836 writeq(val64, &bar0->adapter_control);
6837 s2io_link(nic, LINK_UP);
6838 } else {
6839 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6840 subid)) {
6841 val64 = readq(&bar0->gpio_control);
6842 val64 &= ~GPIO_CTRL_GPIO_0;
6843 writeq(val64, &bar0->gpio_control);
6844 val64 = readq(&bar0->gpio_control);
6845 }
6846 /* turn off LED */
6847 val64 = readq(&bar0->adapter_control);
6848 val64 = val64 & (~ADAPTER_LED_ON);
6849 writeq(val64, &bar0->adapter_control);
6850 s2io_link(nic, LINK_DOWN);
6851 }
6852 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6853
6854 out_unlock:
6855 rtnl_unlock();
6856 }
6857
6858 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6859 struct buffAdd *ba,
6860 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6861 u64 *temp2, int size)
6862 {
6863 struct net_device *dev = sp->dev;
6864 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6865
6866 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6867 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6868 /* allocate skb */
6869 if (*skb) {
6870 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6871 /*
6872 * As Rx frame are not going to be processed,
6873 * using same mapped address for the Rxd
6874 * buffer pointer
6875 */
6876 rxdp1->Buffer0_ptr = *temp0;
6877 } else {
6878 *skb = dev_alloc_skb(size);
6879 if (!(*skb)) {
6880 DBG_PRINT(INFO_DBG,
6881 "%s: Out of memory to allocate %s\n",
6882 dev->name, "1 buf mode SKBs");
6883 stats->mem_alloc_fail_cnt++;
6884 return -ENOMEM ;
6885 }
6886 stats->mem_allocated += (*skb)->truesize;
6887 /* storing the mapped addr in a temp variable
6888 * such it will be used for next rxd whose
6889 * Host Control is NULL
6890 */
6891 rxdp1->Buffer0_ptr = *temp0 =
6892 pci_map_single(sp->pdev, (*skb)->data,
6893 size - NET_IP_ALIGN,
6894 PCI_DMA_FROMDEVICE);
6895 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6896 goto memalloc_failed;
6897 rxdp->Host_Control = (unsigned long) (*skb);
6898 }
6899 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6900 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6901 /* Two buffer Mode */
6902 if (*skb) {
6903 rxdp3->Buffer2_ptr = *temp2;
6904 rxdp3->Buffer0_ptr = *temp0;
6905 rxdp3->Buffer1_ptr = *temp1;
6906 } else {
6907 *skb = dev_alloc_skb(size);
6908 if (!(*skb)) {
6909 DBG_PRINT(INFO_DBG,
6910 "%s: Out of memory to allocate %s\n",
6911 dev->name,
6912 "2 buf mode SKBs");
6913 stats->mem_alloc_fail_cnt++;
6914 return -ENOMEM;
6915 }
6916 stats->mem_allocated += (*skb)->truesize;
6917 rxdp3->Buffer2_ptr = *temp2 =
6918 pci_map_single(sp->pdev, (*skb)->data,
6919 dev->mtu + 4,
6920 PCI_DMA_FROMDEVICE);
6921 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6922 goto memalloc_failed;
6923 rxdp3->Buffer0_ptr = *temp0 =
6924 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6925 PCI_DMA_FROMDEVICE);
6926 if (pci_dma_mapping_error(sp->pdev,
6927 rxdp3->Buffer0_ptr)) {
6928 pci_unmap_single(sp->pdev,
6929 (dma_addr_t)rxdp3->Buffer2_ptr,
6930 dev->mtu + 4,
6931 PCI_DMA_FROMDEVICE);
6932 goto memalloc_failed;
6933 }
6934 rxdp->Host_Control = (unsigned long) (*skb);
6935
6936 /* Buffer-1 will be dummy buffer not used */
6937 rxdp3->Buffer1_ptr = *temp1 =
6938 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6939 PCI_DMA_FROMDEVICE);
6940 if (pci_dma_mapping_error(sp->pdev,
6941 rxdp3->Buffer1_ptr)) {
6942 pci_unmap_single(sp->pdev,
6943 (dma_addr_t)rxdp3->Buffer0_ptr,
6944 BUF0_LEN, PCI_DMA_FROMDEVICE);
6945 pci_unmap_single(sp->pdev,
6946 (dma_addr_t)rxdp3->Buffer2_ptr,
6947 dev->mtu + 4,
6948 PCI_DMA_FROMDEVICE);
6949 goto memalloc_failed;
6950 }
6951 }
6952 }
6953 return 0;
6954
6955 memalloc_failed:
6956 stats->pci_map_fail_cnt++;
6957 stats->mem_freed += (*skb)->truesize;
6958 dev_kfree_skb(*skb);
6959 return -ENOMEM;
6960 }
6961
6962 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6963 int size)
6964 {
6965 struct net_device *dev = sp->dev;
6966 if (sp->rxd_mode == RXD_MODE_1) {
6967 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6968 } else if (sp->rxd_mode == RXD_MODE_3B) {
6969 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6970 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6971 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6972 }
6973 }
6974
6975 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6976 {
6977 int i, j, k, blk_cnt = 0, size;
6978 struct config_param *config = &sp->config;
6979 struct mac_info *mac_control = &sp->mac_control;
6980 struct net_device *dev = sp->dev;
6981 struct RxD_t *rxdp = NULL;
6982 struct sk_buff *skb = NULL;
6983 struct buffAdd *ba = NULL;
6984 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6985
6986 /* Calculate the size based on ring mode */
6987 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6988 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6989 if (sp->rxd_mode == RXD_MODE_1)
6990 size += NET_IP_ALIGN;
6991 else if (sp->rxd_mode == RXD_MODE_3B)
6992 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6993
6994 for (i = 0; i < config->rx_ring_num; i++) {
6995 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6996 struct ring_info *ring = &mac_control->rings[i];
6997
6998 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6999
7000 for (j = 0; j < blk_cnt; j++) {
7001 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7002 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7003 if (sp->rxd_mode == RXD_MODE_3B)
7004 ba = &ring->ba[j][k];
7005 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7006 (u64 *)&temp0_64,
7007 (u64 *)&temp1_64,
7008 (u64 *)&temp2_64,
7009 size) == -ENOMEM) {
7010 return 0;
7011 }
7012
7013 set_rxd_buffer_size(sp, rxdp, size);
7014 wmb();
7015 /* flip the Ownership bit to Hardware */
7016 rxdp->Control_1 |= RXD_OWN_XENA;
7017 }
7018 }
7019 }
7020 return 0;
7021
7022 }
7023
7024 static int s2io_add_isr(struct s2io_nic *sp)
7025 {
7026 int ret = 0;
7027 struct net_device *dev = sp->dev;
7028 int err = 0;
7029
7030 if (sp->config.intr_type == MSI_X)
7031 ret = s2io_enable_msi_x(sp);
7032 if (ret) {
7033 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7034 sp->config.intr_type = INTA;
7035 }
7036
7037 /*
7038 * Store the values of the MSIX table in
7039 * the struct s2io_nic structure
7040 */
7041 store_xmsi_data(sp);
7042
7043 /* After proper initialization of H/W, register ISR */
7044 if (sp->config.intr_type == MSI_X) {
7045 int i, msix_rx_cnt = 0;
7046
7047 for (i = 0; i < sp->num_entries; i++) {
7048 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7049 if (sp->s2io_entries[i].type ==
7050 MSIX_RING_TYPE) {
7051 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7052 dev->name, i);
7053 err = request_irq(sp->entries[i].vector,
7054 s2io_msix_ring_handle,
7055 0,
7056 sp->desc[i],
7057 sp->s2io_entries[i].arg);
7058 } else if (sp->s2io_entries[i].type ==
7059 MSIX_ALARM_TYPE) {
7060 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7061 dev->name, i);
7062 err = request_irq(sp->entries[i].vector,
7063 s2io_msix_fifo_handle,
7064 0,
7065 sp->desc[i],
7066 sp->s2io_entries[i].arg);
7067
7068 }
7069 /* if either data or addr is zero print it. */
7070 if (!(sp->msix_info[i].addr &&
7071 sp->msix_info[i].data)) {
7072 DBG_PRINT(ERR_DBG,
7073 "%s @Addr:0x%llx Data:0x%llx\n",
7074 sp->desc[i],
7075 (unsigned long long)
7076 sp->msix_info[i].addr,
7077 (unsigned long long)
7078 ntohl(sp->msix_info[i].data));
7079 } else
7080 msix_rx_cnt++;
7081 if (err) {
7082 remove_msix_isr(sp);
7083
7084 DBG_PRINT(ERR_DBG,
7085 "%s:MSI-X-%d registration "
7086 "failed\n", dev->name, i);
7087
7088 DBG_PRINT(ERR_DBG,
7089 "%s: Defaulting to INTA\n",
7090 dev->name);
7091 sp->config.intr_type = INTA;
7092 break;
7093 }
7094 sp->s2io_entries[i].in_use =
7095 MSIX_REGISTERED_SUCCESS;
7096 }
7097 }
7098 if (!err) {
7099 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7100 DBG_PRINT(INFO_DBG,
7101 "MSI-X-TX entries enabled through alarm vector\n");
7102 }
7103 }
7104 if (sp->config.intr_type == INTA) {
7105 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7106 sp->name, dev);
7107 if (err) {
7108 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7109 dev->name);
7110 return -1;
7111 }
7112 }
7113 return 0;
7114 }
7115
7116 static void s2io_rem_isr(struct s2io_nic *sp)
7117 {
7118 if (sp->config.intr_type == MSI_X)
7119 remove_msix_isr(sp);
7120 else
7121 remove_inta_isr(sp);
7122 }
7123
7124 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7125 {
7126 int cnt = 0;
7127 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7128 register u64 val64 = 0;
7129 struct config_param *config;
7130 config = &sp->config;
7131
7132 if (!is_s2io_card_up(sp))
7133 return;
7134
7135 del_timer_sync(&sp->alarm_timer);
7136 /* If s2io_set_link task is executing, wait till it completes. */
7137 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7138 msleep(50);
7139 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7140
7141 /* Disable napi */
7142 if (sp->config.napi) {
7143 int off = 0;
7144 if (config->intr_type == MSI_X) {
7145 for (; off < sp->config.rx_ring_num; off++)
7146 napi_disable(&sp->mac_control.rings[off].napi);
7147 }
7148 else
7149 napi_disable(&sp->napi);
7150 }
7151
7152 /* disable Tx and Rx traffic on the NIC */
7153 if (do_io)
7154 stop_nic(sp);
7155
7156 s2io_rem_isr(sp);
7157
7158 /* stop the tx queue, indicate link down */
7159 s2io_link(sp, LINK_DOWN);
7160
7161 /* Check if the device is Quiescent and then Reset the NIC */
7162 while (do_io) {
7163 /* As per the HW requirement we need to replenish the
7164 * receive buffer to avoid the ring bump. Since there is
7165 * no intention of processing the Rx frame at this pointwe are
7166 * just settting the ownership bit of rxd in Each Rx
7167 * ring to HW and set the appropriate buffer size
7168 * based on the ring mode
7169 */
7170 rxd_owner_bit_reset(sp);
7171
7172 val64 = readq(&bar0->adapter_status);
7173 if (verify_xena_quiescence(sp)) {
7174 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7175 break;
7176 }
7177
7178 msleep(50);
7179 cnt++;
7180 if (cnt == 10) {
7181 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7182 "adapter status reads 0x%llx\n",
7183 (unsigned long long)val64);
7184 break;
7185 }
7186 }
7187 if (do_io)
7188 s2io_reset(sp);
7189
7190 /* Free all Tx buffers */
7191 free_tx_buffers(sp);
7192
7193 /* Free all Rx buffers */
7194 free_rx_buffers(sp);
7195
7196 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7197 }
7198
7199 static void s2io_card_down(struct s2io_nic *sp)
7200 {
7201 do_s2io_card_down(sp, 1);
7202 }
7203
7204 static int s2io_card_up(struct s2io_nic *sp)
7205 {
7206 int i, ret = 0;
7207 struct config_param *config;
7208 struct mac_info *mac_control;
7209 struct net_device *dev = (struct net_device *)sp->dev;
7210 u16 interruptible;
7211
7212 /* Initialize the H/W I/O registers */
7213 ret = init_nic(sp);
7214 if (ret != 0) {
7215 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7216 dev->name);
7217 if (ret != -EIO)
7218 s2io_reset(sp);
7219 return ret;
7220 }
7221
7222 /*
7223 * Initializing the Rx buffers. For now we are considering only 1
7224 * Rx ring and initializing buffers into 30 Rx blocks
7225 */
7226 config = &sp->config;
7227 mac_control = &sp->mac_control;
7228
7229 for (i = 0; i < config->rx_ring_num; i++) {
7230 struct ring_info *ring = &mac_control->rings[i];
7231
7232 ring->mtu = dev->mtu;
7233 ret = fill_rx_buffers(sp, ring, 1);
7234 if (ret) {
7235 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7236 dev->name);
7237 s2io_reset(sp);
7238 free_rx_buffers(sp);
7239 return -ENOMEM;
7240 }
7241 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7242 ring->rx_bufs_left);
7243 }
7244
7245 /* Initialise napi */
7246 if (config->napi) {
7247 if (config->intr_type == MSI_X) {
7248 for (i = 0; i < sp->config.rx_ring_num; i++)
7249 napi_enable(&sp->mac_control.rings[i].napi);
7250 } else {
7251 napi_enable(&sp->napi);
7252 }
7253 }
7254
7255 /* Maintain the state prior to the open */
7256 if (sp->promisc_flg)
7257 sp->promisc_flg = 0;
7258 if (sp->m_cast_flg) {
7259 sp->m_cast_flg = 0;
7260 sp->all_multi_pos = 0;
7261 }
7262
7263 /* Setting its receive mode */
7264 s2io_set_multicast(dev);
7265
7266 if (sp->lro) {
7267 /* Initialize max aggregatable pkts per session based on MTU */
7268 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7269 /* Check if we can use (if specified) user provided value */
7270 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7271 sp->lro_max_aggr_per_sess = lro_max_pkts;
7272 }
7273
7274 /* Enable Rx Traffic and interrupts on the NIC */
7275 if (start_nic(sp)) {
7276 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7277 s2io_reset(sp);
7278 free_rx_buffers(sp);
7279 return -ENODEV;
7280 }
7281
7282 /* Add interrupt service routine */
7283 if (s2io_add_isr(sp) != 0) {
7284 if (sp->config.intr_type == MSI_X)
7285 s2io_rem_isr(sp);
7286 s2io_reset(sp);
7287 free_rx_buffers(sp);
7288 return -ENODEV;
7289 }
7290
7291 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7292
7293 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7294
7295 /* Enable select interrupts */
7296 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7297 if (sp->config.intr_type != INTA) {
7298 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7299 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7300 } else {
7301 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7302 interruptible |= TX_PIC_INTR;
7303 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7304 }
7305
7306 return 0;
7307 }
7308
7309 /**
7310 * s2io_restart_nic - Resets the NIC.
7311 * @data : long pointer to the device private structure
7312 * Description:
7313 * This function is scheduled to be run by the s2io_tx_watchdog
7314 * function after 0.5 secs to reset the NIC. The idea is to reduce
7315 * the run time of the watch dog routine which is run holding a
7316 * spin lock.
7317 */
7318
7319 static void s2io_restart_nic(struct work_struct *work)
7320 {
7321 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7322 struct net_device *dev = sp->dev;
7323
7324 rtnl_lock();
7325
7326 if (!netif_running(dev))
7327 goto out_unlock;
7328
7329 s2io_card_down(sp);
7330 if (s2io_card_up(sp)) {
7331 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7332 }
7333 s2io_wake_all_tx_queue(sp);
7334 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7335 out_unlock:
7336 rtnl_unlock();
7337 }
7338
7339 /**
7340 * s2io_tx_watchdog - Watchdog for transmit side.
7341 * @dev : Pointer to net device structure
7342 * Description:
7343 * This function is triggered if the Tx Queue is stopped
7344 * for a pre-defined amount of time when the Interface is still up.
7345 * If the Interface is jammed in such a situation, the hardware is
7346 * reset (by s2io_close) and restarted again (by s2io_open) to
7347 * overcome any problem that might have been caused in the hardware.
7348 * Return value:
7349 * void
7350 */
7351
7352 static void s2io_tx_watchdog(struct net_device *dev)
7353 {
7354 struct s2io_nic *sp = netdev_priv(dev);
7355 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7356
7357 if (netif_carrier_ok(dev)) {
7358 swstats->watchdog_timer_cnt++;
7359 schedule_work(&sp->rst_timer_task);
7360 swstats->soft_reset_cnt++;
7361 }
7362 }
7363
7364 /**
7365 * rx_osm_handler - To perform some OS related operations on SKB.
7366 * @sp: private member of the device structure,pointer to s2io_nic structure.
7367 * @skb : the socket buffer pointer.
7368 * @len : length of the packet
7369 * @cksum : FCS checksum of the frame.
7370 * @ring_no : the ring from which this RxD was extracted.
7371 * Description:
7372 * This function is called by the Rx interrupt serivce routine to perform
7373 * some OS related operations on the SKB before passing it to the upper
7374 * layers. It mainly checks if the checksum is OK, if so adds it to the
7375 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7376 * to the upper layer. If the checksum is wrong, it increments the Rx
7377 * packet error count, frees the SKB and returns error.
7378 * Return value:
7379 * SUCCESS on success and -1 on failure.
7380 */
7381 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7382 {
7383 struct s2io_nic *sp = ring_data->nic;
7384 struct net_device *dev = (struct net_device *)ring_data->dev;
7385 struct sk_buff *skb = (struct sk_buff *)
7386 ((unsigned long)rxdp->Host_Control);
7387 int ring_no = ring_data->ring_no;
7388 u16 l3_csum, l4_csum;
7389 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7390 struct lro *uninitialized_var(lro);
7391 u8 err_mask;
7392 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7393
7394 skb->dev = dev;
7395
7396 if (err) {
7397 /* Check for parity error */
7398 if (err & 0x1)
7399 swstats->parity_err_cnt++;
7400
7401 err_mask = err >> 48;
7402 switch (err_mask) {
7403 case 1:
7404 swstats->rx_parity_err_cnt++;
7405 break;
7406
7407 case 2:
7408 swstats->rx_abort_cnt++;
7409 break;
7410
7411 case 3:
7412 swstats->rx_parity_abort_cnt++;
7413 break;
7414
7415 case 4:
7416 swstats->rx_rda_fail_cnt++;
7417 break;
7418
7419 case 5:
7420 swstats->rx_unkn_prot_cnt++;
7421 break;
7422
7423 case 6:
7424 swstats->rx_fcs_err_cnt++;
7425 break;
7426
7427 case 7:
7428 swstats->rx_buf_size_err_cnt++;
7429 break;
7430
7431 case 8:
7432 swstats->rx_rxd_corrupt_cnt++;
7433 break;
7434
7435 case 15:
7436 swstats->rx_unkn_err_cnt++;
7437 break;
7438 }
7439 /*
7440 * Drop the packet if bad transfer code. Exception being
7441 * 0x5, which could be due to unsupported IPv6 extension header.
7442 * In this case, we let stack handle the packet.
7443 * Note that in this case, since checksum will be incorrect,
7444 * stack will validate the same.
7445 */
7446 if (err_mask != 0x5) {
7447 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7448 dev->name, err_mask);
7449 dev->stats.rx_crc_errors++;
7450 swstats->mem_freed
7451 += skb->truesize;
7452 dev_kfree_skb(skb);
7453 ring_data->rx_bufs_left -= 1;
7454 rxdp->Host_Control = 0;
7455 return 0;
7456 }
7457 }
7458
7459 /* Updating statistics */
7460 ring_data->rx_packets++;
7461 rxdp->Host_Control = 0;
7462 if (sp->rxd_mode == RXD_MODE_1) {
7463 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7464
7465 ring_data->rx_bytes += len;
7466 skb_put(skb, len);
7467
7468 } else if (sp->rxd_mode == RXD_MODE_3B) {
7469 int get_block = ring_data->rx_curr_get_info.block_index;
7470 int get_off = ring_data->rx_curr_get_info.offset;
7471 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7472 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7473 unsigned char *buff = skb_push(skb, buf0_len);
7474
7475 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7476 ring_data->rx_bytes += buf0_len + buf2_len;
7477 memcpy(buff, ba->ba_0, buf0_len);
7478 skb_put(skb, buf2_len);
7479 }
7480
7481 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7482 ((!ring_data->lro) ||
7483 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7484 (sp->rx_csum)) {
7485 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7486 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7487 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7488 /*
7489 * NIC verifies if the Checksum of the received
7490 * frame is Ok or not and accordingly returns
7491 * a flag in the RxD.
7492 */
7493 skb->ip_summed = CHECKSUM_UNNECESSARY;
7494 if (ring_data->lro) {
7495 u32 tcp_len;
7496 u8 *tcp;
7497 int ret = 0;
7498
7499 ret = s2io_club_tcp_session(ring_data,
7500 skb->data, &tcp,
7501 &tcp_len, &lro,
7502 rxdp, sp);
7503 switch (ret) {
7504 case 3: /* Begin anew */
7505 lro->parent = skb;
7506 goto aggregate;
7507 case 1: /* Aggregate */
7508 lro_append_pkt(sp, lro, skb, tcp_len);
7509 goto aggregate;
7510 case 4: /* Flush session */
7511 lro_append_pkt(sp, lro, skb, tcp_len);
7512 queue_rx_frame(lro->parent,
7513 lro->vlan_tag);
7514 clear_lro_session(lro);
7515 swstats->flush_max_pkts++;
7516 goto aggregate;
7517 case 2: /* Flush both */
7518 lro->parent->data_len = lro->frags_len;
7519 swstats->sending_both++;
7520 queue_rx_frame(lro->parent,
7521 lro->vlan_tag);
7522 clear_lro_session(lro);
7523 goto send_up;
7524 case 0: /* sessions exceeded */
7525 case -1: /* non-TCP or not L2 aggregatable */
7526 case 5: /*
7527 * First pkt in session not
7528 * L3/L4 aggregatable
7529 */
7530 break;
7531 default:
7532 DBG_PRINT(ERR_DBG,
7533 "%s: Samadhana!!\n",
7534 __func__);
7535 BUG();
7536 }
7537 }
7538 } else {
7539 /*
7540 * Packet with erroneous checksum, let the
7541 * upper layers deal with it.
7542 */
7543 skb->ip_summed = CHECKSUM_NONE;
7544 }
7545 } else
7546 skb->ip_summed = CHECKSUM_NONE;
7547
7548 swstats->mem_freed += skb->truesize;
7549 send_up:
7550 skb_record_rx_queue(skb, ring_no);
7551 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7552 aggregate:
7553 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7554 return SUCCESS;
7555 }
7556
7557 /**
7558 * s2io_link - stops/starts the Tx queue.
7559 * @sp : private member of the device structure, which is a pointer to the
7560 * s2io_nic structure.
7561 * @link : inidicates whether link is UP/DOWN.
7562 * Description:
7563 * This function stops/starts the Tx queue depending on whether the link
7564 * status of the NIC is is down or up. This is called by the Alarm
7565 * interrupt handler whenever a link change interrupt comes up.
7566 * Return value:
7567 * void.
7568 */
7569
7570 static void s2io_link(struct s2io_nic *sp, int link)
7571 {
7572 struct net_device *dev = (struct net_device *)sp->dev;
7573 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7574
7575 if (link != sp->last_link_state) {
7576 init_tti(sp, link);
7577 if (link == LINK_DOWN) {
7578 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7579 s2io_stop_all_tx_queue(sp);
7580 netif_carrier_off(dev);
7581 if (swstats->link_up_cnt)
7582 swstats->link_up_time =
7583 jiffies - sp->start_time;
7584 swstats->link_down_cnt++;
7585 } else {
7586 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7587 if (swstats->link_down_cnt)
7588 swstats->link_down_time =
7589 jiffies - sp->start_time;
7590 swstats->link_up_cnt++;
7591 netif_carrier_on(dev);
7592 s2io_wake_all_tx_queue(sp);
7593 }
7594 }
7595 sp->last_link_state = link;
7596 sp->start_time = jiffies;
7597 }
7598
7599 /**
7600 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7601 * @sp : private member of the device structure, which is a pointer to the
7602 * s2io_nic structure.
7603 * Description:
7604 * This function initializes a few of the PCI and PCI-X configuration registers
7605 * with recommended values.
7606 * Return value:
7607 * void
7608 */
7609
7610 static void s2io_init_pci(struct s2io_nic *sp)
7611 {
7612 u16 pci_cmd = 0, pcix_cmd = 0;
7613
7614 /* Enable Data Parity Error Recovery in PCI-X command register. */
7615 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7616 &(pcix_cmd));
7617 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7618 (pcix_cmd | 1));
7619 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7620 &(pcix_cmd));
7621
7622 /* Set the PErr Response bit in PCI command register. */
7623 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7624 pci_write_config_word(sp->pdev, PCI_COMMAND,
7625 (pci_cmd | PCI_COMMAND_PARITY));
7626 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7627 }
7628
7629 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7630 u8 *dev_multiq)
7631 {
7632 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7633 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7634 "(%d) not supported\n", tx_fifo_num);
7635
7636 if (tx_fifo_num < 1)
7637 tx_fifo_num = 1;
7638 else
7639 tx_fifo_num = MAX_TX_FIFOS;
7640
7641 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7642 }
7643
7644 if (multiq)
7645 *dev_multiq = multiq;
7646
7647 if (tx_steering_type && (1 == tx_fifo_num)) {
7648 if (tx_steering_type != TX_DEFAULT_STEERING)
7649 DBG_PRINT(ERR_DBG,
7650 "Tx steering is not supported with "
7651 "one fifo. Disabling Tx steering.\n");
7652 tx_steering_type = NO_STEERING;
7653 }
7654
7655 if ((tx_steering_type < NO_STEERING) ||
7656 (tx_steering_type > TX_DEFAULT_STEERING)) {
7657 DBG_PRINT(ERR_DBG,
7658 "Requested transmit steering not supported\n");
7659 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7660 tx_steering_type = NO_STEERING;
7661 }
7662
7663 if (rx_ring_num > MAX_RX_RINGS) {
7664 DBG_PRINT(ERR_DBG,
7665 "Requested number of rx rings not supported\n");
7666 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7667 MAX_RX_RINGS);
7668 rx_ring_num = MAX_RX_RINGS;
7669 }
7670
7671 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7672 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7673 "Defaulting to INTA\n");
7674 *dev_intr_type = INTA;
7675 }
7676
7677 if ((*dev_intr_type == MSI_X) &&
7678 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7679 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7680 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7681 "Defaulting to INTA\n");
7682 *dev_intr_type = INTA;
7683 }
7684
7685 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7686 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7687 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7688 rx_ring_mode = 1;
7689 }
7690 return SUCCESS;
7691 }
7692
7693 /**
7694 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7695 * or Traffic class respectively.
7696 * @nic: device private variable
7697 * Description: The function configures the receive steering to
7698 * desired receive ring.
7699 * Return Value: SUCCESS on success and
7700 * '-1' on failure (endian settings incorrect).
7701 */
7702 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7703 {
7704 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7705 register u64 val64 = 0;
7706
7707 if (ds_codepoint > 63)
7708 return FAILURE;
7709
7710 val64 = RTS_DS_MEM_DATA(ring);
7711 writeq(val64, &bar0->rts_ds_mem_data);
7712
7713 val64 = RTS_DS_MEM_CTRL_WE |
7714 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7715 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7716
7717 writeq(val64, &bar0->rts_ds_mem_ctrl);
7718
7719 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7720 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7721 S2IO_BIT_RESET);
7722 }
7723
7724 static const struct net_device_ops s2io_netdev_ops = {
7725 .ndo_open = s2io_open,
7726 .ndo_stop = s2io_close,
7727 .ndo_get_stats = s2io_get_stats,
7728 .ndo_start_xmit = s2io_xmit,
7729 .ndo_validate_addr = eth_validate_addr,
7730 .ndo_set_multicast_list = s2io_set_multicast,
7731 .ndo_do_ioctl = s2io_ioctl,
7732 .ndo_set_mac_address = s2io_set_mac_addr,
7733 .ndo_change_mtu = s2io_change_mtu,
7734 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7735 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7736 .ndo_tx_timeout = s2io_tx_watchdog,
7737 #ifdef CONFIG_NET_POLL_CONTROLLER
7738 .ndo_poll_controller = s2io_netpoll,
7739 #endif
7740 };
7741
7742 /**
7743 * s2io_init_nic - Initialization of the adapter .
7744 * @pdev : structure containing the PCI related information of the device.
7745 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7746 * Description:
7747 * The function initializes an adapter identified by the pci_dec structure.
7748 * All OS related initialization including memory and device structure and
7749 * initlaization of the device private variable is done. Also the swapper
7750 * control register is initialized to enable read and write into the I/O
7751 * registers of the device.
7752 * Return value:
7753 * returns 0 on success and negative on failure.
7754 */
7755
7756 static int __devinit
7757 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7758 {
7759 struct s2io_nic *sp;
7760 struct net_device *dev;
7761 int i, j, ret;
7762 int dma_flag = false;
7763 u32 mac_up, mac_down;
7764 u64 val64 = 0, tmp64 = 0;
7765 struct XENA_dev_config __iomem *bar0 = NULL;
7766 u16 subid;
7767 struct config_param *config;
7768 struct mac_info *mac_control;
7769 int mode;
7770 u8 dev_intr_type = intr_type;
7771 u8 dev_multiq = 0;
7772
7773 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7774 if (ret)
7775 return ret;
7776
7777 ret = pci_enable_device(pdev);
7778 if (ret) {
7779 DBG_PRINT(ERR_DBG,
7780 "%s: pci_enable_device failed\n", __func__);
7781 return ret;
7782 }
7783
7784 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7785 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7786 dma_flag = true;
7787 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7788 DBG_PRINT(ERR_DBG,
7789 "Unable to obtain 64bit DMA "
7790 "for consistent allocations\n");
7791 pci_disable_device(pdev);
7792 return -ENOMEM;
7793 }
7794 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7795 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7796 } else {
7797 pci_disable_device(pdev);
7798 return -ENOMEM;
7799 }
7800 ret = pci_request_regions(pdev, s2io_driver_name);
7801 if (ret) {
7802 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7803 __func__, ret);
7804 pci_disable_device(pdev);
7805 return -ENODEV;
7806 }
7807 if (dev_multiq)
7808 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7809 else
7810 dev = alloc_etherdev(sizeof(struct s2io_nic));
7811 if (dev == NULL) {
7812 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7813 pci_disable_device(pdev);
7814 pci_release_regions(pdev);
7815 return -ENODEV;
7816 }
7817
7818 pci_set_master(pdev);
7819 pci_set_drvdata(pdev, dev);
7820 SET_NETDEV_DEV(dev, &pdev->dev);
7821
7822 /* Private member variable initialized to s2io NIC structure */
7823 sp = netdev_priv(dev);
7824 memset(sp, 0, sizeof(struct s2io_nic));
7825 sp->dev = dev;
7826 sp->pdev = pdev;
7827 sp->high_dma_flag = dma_flag;
7828 sp->device_enabled_once = false;
7829 if (rx_ring_mode == 1)
7830 sp->rxd_mode = RXD_MODE_1;
7831 if (rx_ring_mode == 2)
7832 sp->rxd_mode = RXD_MODE_3B;
7833
7834 sp->config.intr_type = dev_intr_type;
7835
7836 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7837 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7838 sp->device_type = XFRAME_II_DEVICE;
7839 else
7840 sp->device_type = XFRAME_I_DEVICE;
7841
7842 sp->lro = lro_enable;
7843
7844 /* Initialize some PCI/PCI-X fields of the NIC. */
7845 s2io_init_pci(sp);
7846
7847 /*
7848 * Setting the device configuration parameters.
7849 * Most of these parameters can be specified by the user during
7850 * module insertion as they are module loadable parameters. If
7851 * these parameters are not not specified during load time, they
7852 * are initialized with default values.
7853 */
7854 config = &sp->config;
7855 mac_control = &sp->mac_control;
7856
7857 config->napi = napi;
7858 config->tx_steering_type = tx_steering_type;
7859
7860 /* Tx side parameters. */
7861 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7862 config->tx_fifo_num = MAX_TX_FIFOS;
7863 else
7864 config->tx_fifo_num = tx_fifo_num;
7865
7866 /* Initialize the fifos used for tx steering */
7867 if (config->tx_fifo_num < 5) {
7868 if (config->tx_fifo_num == 1)
7869 sp->total_tcp_fifos = 1;
7870 else
7871 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7872 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7873 sp->total_udp_fifos = 1;
7874 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7875 } else {
7876 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7877 FIFO_OTHER_MAX_NUM);
7878 sp->udp_fifo_idx = sp->total_tcp_fifos;
7879 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7880 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7881 }
7882
7883 config->multiq = dev_multiq;
7884 for (i = 0; i < config->tx_fifo_num; i++) {
7885 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7886
7887 tx_cfg->fifo_len = tx_fifo_len[i];
7888 tx_cfg->fifo_priority = i;
7889 }
7890
7891 /* mapping the QoS priority to the configured fifos */
7892 for (i = 0; i < MAX_TX_FIFOS; i++)
7893 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7894
7895 /* map the hashing selector table to the configured fifos */
7896 for (i = 0; i < config->tx_fifo_num; i++)
7897 sp->fifo_selector[i] = fifo_selector[i];
7898
7899
7900 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7901 for (i = 0; i < config->tx_fifo_num; i++) {
7902 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7903
7904 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7905 if (tx_cfg->fifo_len < 65) {
7906 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7907 break;
7908 }
7909 }
7910 /* + 2 because one Txd for skb->data and one Txd for UFO */
7911 config->max_txds = MAX_SKB_FRAGS + 2;
7912
7913 /* Rx side parameters. */
7914 config->rx_ring_num = rx_ring_num;
7915 for (i = 0; i < config->rx_ring_num; i++) {
7916 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7917 struct ring_info *ring = &mac_control->rings[i];
7918
7919 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7920 rx_cfg->ring_priority = i;
7921 ring->rx_bufs_left = 0;
7922 ring->rxd_mode = sp->rxd_mode;
7923 ring->rxd_count = rxd_count[sp->rxd_mode];
7924 ring->pdev = sp->pdev;
7925 ring->dev = sp->dev;
7926 }
7927
7928 for (i = 0; i < rx_ring_num; i++) {
7929 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7930
7931 rx_cfg->ring_org = RING_ORG_BUFF1;
7932 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7933 }
7934
7935 /* Setting Mac Control parameters */
7936 mac_control->rmac_pause_time = rmac_pause_time;
7937 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7938 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7939
7940
7941 /* initialize the shared memory used by the NIC and the host */
7942 if (init_shared_mem(sp)) {
7943 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7944 ret = -ENOMEM;
7945 goto mem_alloc_failed;
7946 }
7947
7948 sp->bar0 = pci_ioremap_bar(pdev, 0);
7949 if (!sp->bar0) {
7950 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7951 dev->name);
7952 ret = -ENOMEM;
7953 goto bar0_remap_failed;
7954 }
7955
7956 sp->bar1 = pci_ioremap_bar(pdev, 2);
7957 if (!sp->bar1) {
7958 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7959 dev->name);
7960 ret = -ENOMEM;
7961 goto bar1_remap_failed;
7962 }
7963
7964 dev->irq = pdev->irq;
7965 dev->base_addr = (unsigned long)sp->bar0;
7966
7967 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7968 for (j = 0; j < MAX_TX_FIFOS; j++) {
7969 mac_control->tx_FIFO_start[j] =
7970 (struct TxFIFO_element __iomem *)
7971 (sp->bar1 + (j * 0x00020000));
7972 }
7973
7974 /* Driver entry points */
7975 dev->netdev_ops = &s2io_netdev_ops;
7976 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7977 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7978
7979 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7980 if (sp->high_dma_flag == true)
7981 dev->features |= NETIF_F_HIGHDMA;
7982 dev->features |= NETIF_F_TSO;
7983 dev->features |= NETIF_F_TSO6;
7984 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7985 dev->features |= NETIF_F_UFO;
7986 dev->features |= NETIF_F_HW_CSUM;
7987 }
7988 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7989 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7990 INIT_WORK(&sp->set_link_task, s2io_set_link);
7991
7992 pci_save_state(sp->pdev);
7993
7994 /* Setting swapper control on the NIC, for proper reset operation */
7995 if (s2io_set_swapper(sp)) {
7996 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7997 dev->name);
7998 ret = -EAGAIN;
7999 goto set_swap_failed;
8000 }
8001
8002 /* Verify if the Herc works on the slot its placed into */
8003 if (sp->device_type & XFRAME_II_DEVICE) {
8004 mode = s2io_verify_pci_mode(sp);
8005 if (mode < 0) {
8006 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8007 __func__);
8008 ret = -EBADSLT;
8009 goto set_swap_failed;
8010 }
8011 }
8012
8013 if (sp->config.intr_type == MSI_X) {
8014 sp->num_entries = config->rx_ring_num + 1;
8015 ret = s2io_enable_msi_x(sp);
8016
8017 if (!ret) {
8018 ret = s2io_test_msi(sp);
8019 /* rollback MSI-X, will re-enable during add_isr() */
8020 remove_msix_isr(sp);
8021 }
8022 if (ret) {
8023
8024 DBG_PRINT(ERR_DBG,
8025 "MSI-X requested but failed to enable\n");
8026 sp->config.intr_type = INTA;
8027 }
8028 }
8029
8030 if (config->intr_type == MSI_X) {
8031 for (i = 0; i < config->rx_ring_num ; i++) {
8032 struct ring_info *ring = &mac_control->rings[i];
8033
8034 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8035 }
8036 } else {
8037 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8038 }
8039
8040 /* Not needed for Herc */
8041 if (sp->device_type & XFRAME_I_DEVICE) {
8042 /*
8043 * Fix for all "FFs" MAC address problems observed on
8044 * Alpha platforms
8045 */
8046 fix_mac_address(sp);
8047 s2io_reset(sp);
8048 }
8049
8050 /*
8051 * MAC address initialization.
8052 * For now only one mac address will be read and used.
8053 */
8054 bar0 = sp->bar0;
8055 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8056 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8057 writeq(val64, &bar0->rmac_addr_cmd_mem);
8058 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8059 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8060 S2IO_BIT_RESET);
8061 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8062 mac_down = (u32)tmp64;
8063 mac_up = (u32) (tmp64 >> 32);
8064
8065 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8066 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8067 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8068 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8069 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8070 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8071
8072 /* Set the factory defined MAC address initially */
8073 dev->addr_len = ETH_ALEN;
8074 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8075 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8076
8077 /* initialize number of multicast & unicast MAC entries variables */
8078 if (sp->device_type == XFRAME_I_DEVICE) {
8079 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8080 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8081 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8082 } else if (sp->device_type == XFRAME_II_DEVICE) {
8083 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8084 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8085 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8086 }
8087
8088 /* store mac addresses from CAM to s2io_nic structure */
8089 do_s2io_store_unicast_mc(sp);
8090
8091 /* Configure MSIX vector for number of rings configured plus one */
8092 if ((sp->device_type == XFRAME_II_DEVICE) &&
8093 (config->intr_type == MSI_X))
8094 sp->num_entries = config->rx_ring_num + 1;
8095
8096 /* Store the values of the MSIX table in the s2io_nic structure */
8097 store_xmsi_data(sp);
8098 /* reset Nic and bring it to known state */
8099 s2io_reset(sp);
8100
8101 /*
8102 * Initialize link state flags
8103 * and the card state parameter
8104 */
8105 sp->state = 0;
8106
8107 /* Initialize spinlocks */
8108 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8109 struct fifo_info *fifo = &mac_control->fifos[i];
8110
8111 spin_lock_init(&fifo->tx_lock);
8112 }
8113
8114 /*
8115 * SXE-002: Configure link and activity LED to init state
8116 * on driver load.
8117 */
8118 subid = sp->pdev->subsystem_device;
8119 if ((subid & 0xFF) >= 0x07) {
8120 val64 = readq(&bar0->gpio_control);
8121 val64 |= 0x0000800000000000ULL;
8122 writeq(val64, &bar0->gpio_control);
8123 val64 = 0x0411040400000000ULL;
8124 writeq(val64, (void __iomem *)bar0 + 0x2700);
8125 val64 = readq(&bar0->gpio_control);
8126 }
8127
8128 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8129
8130 if (register_netdev(dev)) {
8131 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8132 ret = -ENODEV;
8133 goto register_failed;
8134 }
8135 s2io_vpd_read(sp);
8136 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
8137 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8138 sp->product_name, pdev->revision);
8139 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8140 s2io_driver_version);
8141 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8142 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8143 if (sp->device_type & XFRAME_II_DEVICE) {
8144 mode = s2io_print_pci_mode(sp);
8145 if (mode < 0) {
8146 ret = -EBADSLT;
8147 unregister_netdev(dev);
8148 goto set_swap_failed;
8149 }
8150 }
8151 switch (sp->rxd_mode) {
8152 case RXD_MODE_1:
8153 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8154 dev->name);
8155 break;
8156 case RXD_MODE_3B:
8157 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8158 dev->name);
8159 break;
8160 }
8161
8162 switch (sp->config.napi) {
8163 case 0:
8164 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8165 break;
8166 case 1:
8167 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8168 break;
8169 }
8170
8171 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8172 sp->config.tx_fifo_num);
8173
8174 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8175 sp->config.rx_ring_num);
8176
8177 switch (sp->config.intr_type) {
8178 case INTA:
8179 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8180 break;
8181 case MSI_X:
8182 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8183 break;
8184 }
8185 if (sp->config.multiq) {
8186 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8187 struct fifo_info *fifo = &mac_control->fifos[i];
8188
8189 fifo->multiq = config->multiq;
8190 }
8191 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8192 dev->name);
8193 } else
8194 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8195 dev->name);
8196
8197 switch (sp->config.tx_steering_type) {
8198 case NO_STEERING:
8199 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8200 dev->name);
8201 break;
8202 case TX_PRIORITY_STEERING:
8203 DBG_PRINT(ERR_DBG,
8204 "%s: Priority steering enabled for transmit\n",
8205 dev->name);
8206 break;
8207 case TX_DEFAULT_STEERING:
8208 DBG_PRINT(ERR_DBG,
8209 "%s: Default steering enabled for transmit\n",
8210 dev->name);
8211 }
8212
8213 if (sp->lro)
8214 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8215 dev->name);
8216 if (ufo)
8217 DBG_PRINT(ERR_DBG,
8218 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8219 dev->name);
8220 /* Initialize device name */
8221 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8222
8223 if (vlan_tag_strip)
8224 sp->vlan_strip_flag = 1;
8225 else
8226 sp->vlan_strip_flag = 0;
8227
8228 /*
8229 * Make Link state as off at this point, when the Link change
8230 * interrupt comes the state will be automatically changed to
8231 * the right state.
8232 */
8233 netif_carrier_off(dev);
8234
8235 return 0;
8236
8237 register_failed:
8238 set_swap_failed:
8239 iounmap(sp->bar1);
8240 bar1_remap_failed:
8241 iounmap(sp->bar0);
8242 bar0_remap_failed:
8243 mem_alloc_failed:
8244 free_shared_mem(sp);
8245 pci_disable_device(pdev);
8246 pci_release_regions(pdev);
8247 pci_set_drvdata(pdev, NULL);
8248 free_netdev(dev);
8249
8250 return ret;
8251 }
8252
8253 /**
8254 * s2io_rem_nic - Free the PCI device
8255 * @pdev: structure containing the PCI related information of the device.
8256 * Description: This function is called by the Pci subsystem to release a
8257 * PCI device and free up all resource held up by the device. This could
8258 * be in response to a Hot plug event or when the driver is to be removed
8259 * from memory.
8260 */
8261
8262 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8263 {
8264 struct net_device *dev =
8265 (struct net_device *)pci_get_drvdata(pdev);
8266 struct s2io_nic *sp;
8267
8268 if (dev == NULL) {
8269 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8270 return;
8271 }
8272
8273 flush_scheduled_work();
8274
8275 sp = netdev_priv(dev);
8276 unregister_netdev(dev);
8277
8278 free_shared_mem(sp);
8279 iounmap(sp->bar0);
8280 iounmap(sp->bar1);
8281 pci_release_regions(pdev);
8282 pci_set_drvdata(pdev, NULL);
8283 free_netdev(dev);
8284 pci_disable_device(pdev);
8285 }
8286
8287 /**
8288 * s2io_starter - Entry point for the driver
8289 * Description: This function is the entry point for the driver. It verifies
8290 * the module loadable parameters and initializes PCI configuration space.
8291 */
8292
8293 static int __init s2io_starter(void)
8294 {
8295 return pci_register_driver(&s2io_driver);
8296 }
8297
8298 /**
8299 * s2io_closer - Cleanup routine for the driver
8300 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8301 */
8302
8303 static __exit void s2io_closer(void)
8304 {
8305 pci_unregister_driver(&s2io_driver);
8306 DBG_PRINT(INIT_DBG, "cleanup done\n");
8307 }
8308
8309 module_init(s2io_starter);
8310 module_exit(s2io_closer);
8311
8312 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8313 struct tcphdr **tcp, struct RxD_t *rxdp,
8314 struct s2io_nic *sp)
8315 {
8316 int ip_off;
8317 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8318
8319 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8320 DBG_PRINT(INIT_DBG,
8321 "%s: Non-TCP frames not supported for LRO\n",
8322 __func__);
8323 return -1;
8324 }
8325
8326 /* Checking for DIX type or DIX type with VLAN */
8327 if ((l2_type == 0) || (l2_type == 4)) {
8328 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8329 /*
8330 * If vlan stripping is disabled and the frame is VLAN tagged,
8331 * shift the offset by the VLAN header size bytes.
8332 */
8333 if ((!sp->vlan_strip_flag) &&
8334 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8335 ip_off += HEADER_VLAN_SIZE;
8336 } else {
8337 /* LLC, SNAP etc are considered non-mergeable */
8338 return -1;
8339 }
8340
8341 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8342 ip_len = (u8)((*ip)->ihl);
8343 ip_len <<= 2;
8344 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8345
8346 return 0;
8347 }
8348
8349 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8350 struct tcphdr *tcp)
8351 {
8352 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8353 if ((lro->iph->saddr != ip->saddr) ||
8354 (lro->iph->daddr != ip->daddr) ||
8355 (lro->tcph->source != tcp->source) ||
8356 (lro->tcph->dest != tcp->dest))
8357 return -1;
8358 return 0;
8359 }
8360
8361 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8362 {
8363 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8364 }
8365
8366 static void initiate_new_session(struct lro *lro, u8 *l2h,
8367 struct iphdr *ip, struct tcphdr *tcp,
8368 u32 tcp_pyld_len, u16 vlan_tag)
8369 {
8370 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8371 lro->l2h = l2h;
8372 lro->iph = ip;
8373 lro->tcph = tcp;
8374 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8375 lro->tcp_ack = tcp->ack_seq;
8376 lro->sg_num = 1;
8377 lro->total_len = ntohs(ip->tot_len);
8378 lro->frags_len = 0;
8379 lro->vlan_tag = vlan_tag;
8380 /*
8381 * Check if we saw TCP timestamp.
8382 * Other consistency checks have already been done.
8383 */
8384 if (tcp->doff == 8) {
8385 __be32 *ptr;
8386 ptr = (__be32 *)(tcp+1);
8387 lro->saw_ts = 1;
8388 lro->cur_tsval = ntohl(*(ptr+1));
8389 lro->cur_tsecr = *(ptr+2);
8390 }
8391 lro->in_use = 1;
8392 }
8393
8394 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8395 {
8396 struct iphdr *ip = lro->iph;
8397 struct tcphdr *tcp = lro->tcph;
8398 __sum16 nchk;
8399 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8400
8401 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8402
8403 /* Update L3 header */
8404 ip->tot_len = htons(lro->total_len);
8405 ip->check = 0;
8406 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8407 ip->check = nchk;
8408
8409 /* Update L4 header */
8410 tcp->ack_seq = lro->tcp_ack;
8411 tcp->window = lro->window;
8412
8413 /* Update tsecr field if this session has timestamps enabled */
8414 if (lro->saw_ts) {
8415 __be32 *ptr = (__be32 *)(tcp + 1);
8416 *(ptr+2) = lro->cur_tsecr;
8417 }
8418
8419 /* Update counters required for calculation of
8420 * average no. of packets aggregated.
8421 */
8422 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8423 swstats->num_aggregations++;
8424 }
8425
8426 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8427 struct tcphdr *tcp, u32 l4_pyld)
8428 {
8429 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8430 lro->total_len += l4_pyld;
8431 lro->frags_len += l4_pyld;
8432 lro->tcp_next_seq += l4_pyld;
8433 lro->sg_num++;
8434
8435 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8436 lro->tcp_ack = tcp->ack_seq;
8437 lro->window = tcp->window;
8438
8439 if (lro->saw_ts) {
8440 __be32 *ptr;
8441 /* Update tsecr and tsval from this packet */
8442 ptr = (__be32 *)(tcp+1);
8443 lro->cur_tsval = ntohl(*(ptr+1));
8444 lro->cur_tsecr = *(ptr + 2);
8445 }
8446 }
8447
8448 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8449 struct tcphdr *tcp, u32 tcp_pyld_len)
8450 {
8451 u8 *ptr;
8452
8453 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8454
8455 if (!tcp_pyld_len) {
8456 /* Runt frame or a pure ack */
8457 return -1;
8458 }
8459
8460 if (ip->ihl != 5) /* IP has options */
8461 return -1;
8462
8463 /* If we see CE codepoint in IP header, packet is not mergeable */
8464 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8465 return -1;
8466
8467 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8468 if (tcp->urg || tcp->psh || tcp->rst ||
8469 tcp->syn || tcp->fin ||
8470 tcp->ece || tcp->cwr || !tcp->ack) {
8471 /*
8472 * Currently recognize only the ack control word and
8473 * any other control field being set would result in
8474 * flushing the LRO session
8475 */
8476 return -1;
8477 }
8478
8479 /*
8480 * Allow only one TCP timestamp option. Don't aggregate if
8481 * any other options are detected.
8482 */
8483 if (tcp->doff != 5 && tcp->doff != 8)
8484 return -1;
8485
8486 if (tcp->doff == 8) {
8487 ptr = (u8 *)(tcp + 1);
8488 while (*ptr == TCPOPT_NOP)
8489 ptr++;
8490 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8491 return -1;
8492
8493 /* Ensure timestamp value increases monotonically */
8494 if (l_lro)
8495 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8496 return -1;
8497
8498 /* timestamp echo reply should be non-zero */
8499 if (*((__be32 *)(ptr+6)) == 0)
8500 return -1;
8501 }
8502
8503 return 0;
8504 }
8505
8506 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8507 u8 **tcp, u32 *tcp_len, struct lro **lro,
8508 struct RxD_t *rxdp, struct s2io_nic *sp)
8509 {
8510 struct iphdr *ip;
8511 struct tcphdr *tcph;
8512 int ret = 0, i;
8513 u16 vlan_tag = 0;
8514 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8515
8516 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8517 rxdp, sp);
8518 if (ret)
8519 return ret;
8520
8521 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8522
8523 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8524 tcph = (struct tcphdr *)*tcp;
8525 *tcp_len = get_l4_pyld_length(ip, tcph);
8526 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8527 struct lro *l_lro = &ring_data->lro0_n[i];
8528 if (l_lro->in_use) {
8529 if (check_for_socket_match(l_lro, ip, tcph))
8530 continue;
8531 /* Sock pair matched */
8532 *lro = l_lro;
8533
8534 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8535 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8536 "expected 0x%x, actual 0x%x\n",
8537 __func__,
8538 (*lro)->tcp_next_seq,
8539 ntohl(tcph->seq));
8540
8541 swstats->outof_sequence_pkts++;
8542 ret = 2;
8543 break;
8544 }
8545
8546 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8547 *tcp_len))
8548 ret = 1; /* Aggregate */
8549 else
8550 ret = 2; /* Flush both */
8551 break;
8552 }
8553 }
8554
8555 if (ret == 0) {
8556 /* Before searching for available LRO objects,
8557 * check if the pkt is L3/L4 aggregatable. If not
8558 * don't create new LRO session. Just send this
8559 * packet up.
8560 */
8561 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8562 return 5;
8563
8564 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8565 struct lro *l_lro = &ring_data->lro0_n[i];
8566 if (!(l_lro->in_use)) {
8567 *lro = l_lro;
8568 ret = 3; /* Begin anew */
8569 break;
8570 }
8571 }
8572 }
8573
8574 if (ret == 0) { /* sessions exceeded */
8575 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8576 __func__);
8577 *lro = NULL;
8578 return ret;
8579 }
8580
8581 switch (ret) {
8582 case 3:
8583 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8584 vlan_tag);
8585 break;
8586 case 2:
8587 update_L3L4_header(sp, *lro);
8588 break;
8589 case 1:
8590 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8591 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8592 update_L3L4_header(sp, *lro);
8593 ret = 4; /* Flush the LRO */
8594 }
8595 break;
8596 default:
8597 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8598 break;
8599 }
8600
8601 return ret;
8602 }
8603
8604 static void clear_lro_session(struct lro *lro)
8605 {
8606 static u16 lro_struct_size = sizeof(struct lro);
8607
8608 memset(lro, 0, lro_struct_size);
8609 }
8610
8611 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8612 {
8613 struct net_device *dev = skb->dev;
8614 struct s2io_nic *sp = netdev_priv(dev);
8615
8616 skb->protocol = eth_type_trans(skb, dev);
8617 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
8618 /* Queueing the vlan frame to the upper layer */
8619 if (sp->config.napi)
8620 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8621 else
8622 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8623 } else {
8624 if (sp->config.napi)
8625 netif_receive_skb(skb);
8626 else
8627 netif_rx(skb);
8628 }
8629 }
8630
8631 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8632 struct sk_buff *skb, u32 tcp_len)
8633 {
8634 struct sk_buff *first = lro->parent;
8635 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8636
8637 first->len += tcp_len;
8638 first->data_len = lro->frags_len;
8639 skb_pull(skb, (skb->len - tcp_len));
8640 if (skb_shinfo(first)->frag_list)
8641 lro->last_frag->next = skb;
8642 else
8643 skb_shinfo(first)->frag_list = skb;
8644 first->truesize += skb->truesize;
8645 lro->last_frag = skb;
8646 swstats->clubbed_frms_cnt++;
8647 return;
8648 }
8649
8650 /**
8651 * s2io_io_error_detected - called when PCI error is detected
8652 * @pdev: Pointer to PCI device
8653 * @state: The current pci connection state
8654 *
8655 * This function is called after a PCI bus error affecting
8656 * this device has been detected.
8657 */
8658 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8659 pci_channel_state_t state)
8660 {
8661 struct net_device *netdev = pci_get_drvdata(pdev);
8662 struct s2io_nic *sp = netdev_priv(netdev);
8663
8664 netif_device_detach(netdev);
8665
8666 if (state == pci_channel_io_perm_failure)
8667 return PCI_ERS_RESULT_DISCONNECT;
8668
8669 if (netif_running(netdev)) {
8670 /* Bring down the card, while avoiding PCI I/O */
8671 do_s2io_card_down(sp, 0);
8672 }
8673 pci_disable_device(pdev);
8674
8675 return PCI_ERS_RESULT_NEED_RESET;
8676 }
8677
8678 /**
8679 * s2io_io_slot_reset - called after the pci bus has been reset.
8680 * @pdev: Pointer to PCI device
8681 *
8682 * Restart the card from scratch, as if from a cold-boot.
8683 * At this point, the card has exprienced a hard reset,
8684 * followed by fixups by BIOS, and has its config space
8685 * set up identically to what it was at cold boot.
8686 */
8687 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8688 {
8689 struct net_device *netdev = pci_get_drvdata(pdev);
8690 struct s2io_nic *sp = netdev_priv(netdev);
8691
8692 if (pci_enable_device(pdev)) {
8693 pr_err("Cannot re-enable PCI device after reset.\n");
8694 return PCI_ERS_RESULT_DISCONNECT;
8695 }
8696
8697 pci_set_master(pdev);
8698 s2io_reset(sp);
8699
8700 return PCI_ERS_RESULT_RECOVERED;
8701 }
8702
8703 /**
8704 * s2io_io_resume - called when traffic can start flowing again.
8705 * @pdev: Pointer to PCI device
8706 *
8707 * This callback is called when the error recovery driver tells
8708 * us that its OK to resume normal operation.
8709 */
8710 static void s2io_io_resume(struct pci_dev *pdev)
8711 {
8712 struct net_device *netdev = pci_get_drvdata(pdev);
8713 struct s2io_nic *sp = netdev_priv(netdev);
8714
8715 if (netif_running(netdev)) {
8716 if (s2io_card_up(sp)) {
8717 pr_err("Can't bring device back up after reset.\n");
8718 return;
8719 }
8720
8721 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8722 s2io_card_down(sp);
8723 pr_err("Can't restore mac addr after reset.\n");
8724 return;
8725 }
8726 }
8727
8728 netif_device_attach(netdev);
8729 netif_tx_wake_all_queues(netdev);
8730 }
Linux for Ginger Game Console