| blob | a9a0df522ca3882f940a729653dadbdfcc50b6e2 |
1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
4 /*
5 * OMAP24XX Clock Management register bits
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
19 /* Bits shared between registers */
21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22 #define OMAP24XX_EN_CAM_SHIFT 31
23 #define OMAP24XX_EN_CAM (1 << 31)
24 #define OMAP24XX_EN_WDT4_SHIFT 29
25 #define OMAP24XX_EN_WDT4 (1 << 29)
26 #define OMAP2420_EN_WDT3_SHIFT 28
27 #define OMAP2420_EN_WDT3 (1 << 28)
28 #define OMAP24XX_EN_MSPRO_SHIFT 27
29 #define OMAP24XX_EN_MSPRO (1 << 27)
30 #define OMAP24XX_EN_FAC_SHIFT 25
31 #define OMAP24XX_EN_FAC (1 << 25)
32 #define OMAP2420_EN_EAC_SHIFT 24
33 #define OMAP2420_EN_EAC (1 << 24)
34 #define OMAP24XX_EN_HDQ_SHIFT 23
35 #define OMAP24XX_EN_HDQ (1 << 23)
36 #define OMAP2420_EN_I2C2_SHIFT 20
37 #define OMAP2420_EN_I2C2 (1 << 20)
38 #define OMAP2420_EN_I2C1_SHIFT 19
39 #define OMAP2420_EN_I2C1 (1 << 19)
41 /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
42 #define OMAP2430_EN_MCBSP5_SHIFT 5
43 #define OMAP2430_EN_MCBSP5 (1 << 5)
44 #define OMAP2430_EN_MCBSP4_SHIFT 4
45 #define OMAP2430_EN_MCBSP4 (1 << 4)
46 #define OMAP2430_EN_MCBSP3_SHIFT 3
47 #define OMAP2430_EN_MCBSP3 (1 << 3)
48 #define OMAP24XX_EN_SSI_SHIFT 1
49 #define OMAP24XX_EN_SSI (1 << 1)
51 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
52 #define OMAP24XX_EN_MPU_WDT_SHIFT 3
53 #define OMAP24XX_EN_MPU_WDT (1 << 3)
55 /* Bits specific to each register */
57 /* CM_IDLEST_MPU */
58 /* 2430 only */
59 #define OMAP2430_ST_MPU (1 << 0)
61 /* CM_CLKSEL_MPU */
62 #define OMAP24XX_CLKSEL_MPU_SHIFT 0
63 #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
65 /* CM_CLKSTCTRL_MPU */
66 #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
67 #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
69 /* CM_FCLKEN1_CORE specific bits*/
70 #define OMAP24XX_EN_TV_SHIFT 2
71 #define OMAP24XX_EN_TV (1 << 2)
72 #define OMAP24XX_EN_DSS2_SHIFT 1
73 #define OMAP24XX_EN_DSS2 (1 << 1)
74 #define OMAP24XX_EN_DSS1_SHIFT 0
75 #define OMAP24XX_EN_DSS1 (1 << 0)
77 /* CM_FCLKEN2_CORE specific bits */
78 #define OMAP2430_EN_I2CHS2_SHIFT 20
79 #define OMAP2430_EN_I2CHS2 (1 << 20)
80 #define OMAP2430_EN_I2CHS1_SHIFT 19
81 #define OMAP2430_EN_I2CHS1 (1 << 19)
82 #define OMAP2430_EN_MMCHSDB2_SHIFT 17
83 #define OMAP2430_EN_MMCHSDB2 (1 << 17)
84 #define OMAP2430_EN_MMCHSDB1_SHIFT 16
85 #define OMAP2430_EN_MMCHSDB1 (1 << 16)
87 /* CM_ICLKEN1_CORE specific bits */
88 #define OMAP24XX_EN_MAILBOXES_SHIFT 30
89 #define OMAP24XX_EN_MAILBOXES (1 << 30)
90 #define OMAP24XX_EN_DSS_SHIFT 0
91 #define OMAP24XX_EN_DSS (1 << 0)
93 /* CM_ICLKEN2_CORE specific bits */
95 /* CM_ICLKEN3_CORE */
96 /* 2430 only */
97 #define OMAP2430_EN_SDRC_SHIFT 2
98 #define OMAP2430_EN_SDRC (1 << 2)
100 /* CM_ICLKEN4_CORE */
101 #define OMAP24XX_EN_PKA_SHIFT 4
102 #define OMAP24XX_EN_PKA (1 << 4)
103 #define OMAP24XX_EN_AES_SHIFT 3
104 #define OMAP24XX_EN_AES (1 << 3)
105 #define OMAP24XX_EN_RNG_SHIFT 2
106 #define OMAP24XX_EN_RNG (1 << 2)
107 #define OMAP24XX_EN_SHA_SHIFT 1
108 #define OMAP24XX_EN_SHA (1 << 1)
109 #define OMAP24XX_EN_DES_SHIFT 0
110 #define OMAP24XX_EN_DES (1 << 0)
112 /* CM_IDLEST1_CORE specific bits */
113 #define OMAP24XX_ST_MAILBOXES_SHIFT 30
114 #define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
115 #define OMAP24XX_ST_WDT4_SHIFT 29
116 #define OMAP24XX_ST_WDT4_MASK (1 << 29)
117 #define OMAP2420_ST_WDT3_SHIFT 28
118 #define OMAP2420_ST_WDT3_MASK (1 << 28)
119 #define OMAP24XX_ST_MSPRO_SHIFT 27
120 #define OMAP24XX_ST_MSPRO_MASK (1 << 27)
121 #define OMAP24XX_ST_FAC_SHIFT 25
122 #define OMAP24XX_ST_FAC_MASK (1 << 25)
123 #define OMAP2420_ST_EAC_SHIFT 24
124 #define OMAP2420_ST_EAC_MASK (1 << 24)
125 #define OMAP24XX_ST_HDQ_SHIFT 23
126 #define OMAP24XX_ST_HDQ_MASK (1 << 23)
127 #define OMAP2420_ST_I2C2_SHIFT 20
128 #define OMAP2420_ST_I2C2_MASK (1 << 20)
129 #define OMAP2420_ST_I2C1_SHIFT 19
130 #define OMAP2420_ST_I2C1_MASK (1 << 19)
131 #define OMAP24XX_ST_MCBSP2_SHIFT 16
132 #define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
133 #define OMAP24XX_ST_MCBSP1_SHIFT 15
134 #define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
135 #define OMAP24XX_ST_DSS_SHIFT 0
136 #define OMAP24XX_ST_DSS_MASK (1 << 0)
138 /* CM_IDLEST2_CORE */
139 #define OMAP2430_ST_MCBSP5_SHIFT 5
140 #define OMAP2430_ST_MCBSP5_MASK (1 << 5)
141 #define OMAP2430_ST_MCBSP4_SHIFT 4
142 #define OMAP2430_ST_MCBSP4_MASK (1 << 4)
143 #define OMAP2430_ST_MCBSP3_SHIFT 3
144 #define OMAP2430_ST_MCBSP3_MASK (1 << 3)
145 #define OMAP24XX_ST_SSI_SHIFT 1
146 #define OMAP24XX_ST_SSI_MASK (1 << 1)
148 /* CM_IDLEST3_CORE */
149 /* 2430 only */
150 #define OMAP2430_ST_SDRC_SHIFT 2
151 #define OMAP2430_ST_SDRC_MASK (1 << 2)
153 /* CM_IDLEST4_CORE */
154 #define OMAP24XX_ST_PKA_SHIFT 4
155 #define OMAP24XX_ST_PKA_MASK (1 << 4)
156 #define OMAP24XX_ST_AES_SHIFT 3
157 #define OMAP24XX_ST_AES_MASK (1 << 3)
158 #define OMAP24XX_ST_RNG_SHIFT 2
159 #define OMAP24XX_ST_RNG_MASK (1 << 2)
160 #define OMAP24XX_ST_SHA_SHIFT 1
161 #define OMAP24XX_ST_SHA_MASK (1 << 1)
162 #define OMAP24XX_ST_DES_SHIFT 0
163 #define OMAP24XX_ST_DES_MASK (1 << 0)
165 /* CM_AUTOIDLE1_CORE */
166 #define OMAP24XX_AUTO_CAM (1 << 31)
167 #define OMAP24XX_AUTO_MAILBOXES (1 << 30)
168 #define OMAP24XX_AUTO_WDT4 (1 << 29)
169 #define OMAP2420_AUTO_WDT3 (1 << 28)
170 #define OMAP24XX_AUTO_MSPRO (1 << 27)
171 #define OMAP2420_AUTO_MMC (1 << 26)
172 #define OMAP24XX_AUTO_FAC (1 << 25)
173 #define OMAP2420_AUTO_EAC (1 << 24)
174 #define OMAP24XX_AUTO_HDQ (1 << 23)
175 #define OMAP24XX_AUTO_UART2 (1 << 22)
176 #define OMAP24XX_AUTO_UART1 (1 << 21)
177 #define OMAP24XX_AUTO_I2C2 (1 << 20)
178 #define OMAP24XX_AUTO_I2C1 (1 << 19)
179 #define OMAP24XX_AUTO_MCSPI2 (1 << 18)
180 #define OMAP24XX_AUTO_MCSPI1 (1 << 17)
181 #define OMAP24XX_AUTO_MCBSP2 (1 << 16)
182 #define OMAP24XX_AUTO_MCBSP1 (1 << 15)
183 #define OMAP24XX_AUTO_GPT12 (1 << 14)
184 #define OMAP24XX_AUTO_GPT11 (1 << 13)
185 #define OMAP24XX_AUTO_GPT10 (1 << 12)
186 #define OMAP24XX_AUTO_GPT9 (1 << 11)
187 #define OMAP24XX_AUTO_GPT8 (1 << 10)
188 #define OMAP24XX_AUTO_GPT7 (1 << 9)
189 #define OMAP24XX_AUTO_GPT6 (1 << 8)
190 #define OMAP24XX_AUTO_GPT5 (1 << 7)
191 #define OMAP24XX_AUTO_GPT4 (1 << 6)
192 #define OMAP24XX_AUTO_GPT3 (1 << 5)
193 #define OMAP24XX_AUTO_GPT2 (1 << 4)
194 #define OMAP2420_AUTO_VLYNQ (1 << 3)
195 #define OMAP24XX_AUTO_DSS (1 << 0)
197 /* CM_AUTOIDLE2_CORE */
198 #define OMAP2430_AUTO_MDM_INTC (1 << 11)
199 #define OMAP2430_AUTO_GPIO5 (1 << 10)
200 #define OMAP2430_AUTO_MCSPI3 (1 << 9)
201 #define OMAP2430_AUTO_MMCHS2 (1 << 8)
202 #define OMAP2430_AUTO_MMCHS1 (1 << 7)
203 #define OMAP2430_AUTO_USBHS (1 << 6)
204 #define OMAP2430_AUTO_MCBSP5 (1 << 5)
205 #define OMAP2430_AUTO_MCBSP4 (1 << 4)
206 #define OMAP2430_AUTO_MCBSP3 (1 << 3)
207 #define OMAP24XX_AUTO_UART3 (1 << 2)
208 #define OMAP24XX_AUTO_SSI (1 << 1)
209 #define OMAP24XX_AUTO_USB (1 << 0)
211 /* CM_AUTOIDLE3_CORE */
212 #define OMAP24XX_AUTO_SDRC (1 << 2)
213 #define OMAP24XX_AUTO_GPMC (1 << 1)
214 #define OMAP24XX_AUTO_SDMA (1 << 0)
216 /* CM_AUTOIDLE4_CORE */
217 #define OMAP24XX_AUTO_PKA (1 << 4)
218 #define OMAP24XX_AUTO_AES (1 << 3)
219 #define OMAP24XX_AUTO_RNG (1 << 2)
220 #define OMAP24XX_AUTO_SHA (1 << 1)
221 #define OMAP24XX_AUTO_DES (1 << 0)
223 /* CM_CLKSEL1_CORE */
224 #define OMAP24XX_CLKSEL_USB_SHIFT 25
225 #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
226 #define OMAP24XX_CLKSEL_SSI_SHIFT 20
227 #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
228 #define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
229 #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
230 #define OMAP24XX_CLKSEL_DSS2_SHIFT 13
231 #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
232 #define OMAP24XX_CLKSEL_DSS1_SHIFT 8
233 #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
234 #define OMAP24XX_CLKSEL_L4_SHIFT 5
235 #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
236 #define OMAP24XX_CLKSEL_L3_SHIFT 0
237 #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
239 /* CM_CLKSEL2_CORE */
240 #define OMAP24XX_CLKSEL_GPT12_SHIFT 22
241 #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
242 #define OMAP24XX_CLKSEL_GPT11_SHIFT 20
243 #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
244 #define OMAP24XX_CLKSEL_GPT10_SHIFT 18
245 #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
246 #define OMAP24XX_CLKSEL_GPT9_SHIFT 16
247 #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
248 #define OMAP24XX_CLKSEL_GPT8_SHIFT 14
249 #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
250 #define OMAP24XX_CLKSEL_GPT7_SHIFT 12
251 #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
252 #define OMAP24XX_CLKSEL_GPT6_SHIFT 10
253 #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
254 #define OMAP24XX_CLKSEL_GPT5_SHIFT 8
255 #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
256 #define OMAP24XX_CLKSEL_GPT4_SHIFT 6
257 #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
258 #define OMAP24XX_CLKSEL_GPT3_SHIFT 4
259 #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
260 #define OMAP24XX_CLKSEL_GPT2_SHIFT 2
261 #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
263 /* CM_CLKSTCTRL_CORE */
264 #define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
265 #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
266 #define OMAP24XX_AUTOSTATE_L4_SHIFT 1
267 #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
268 #define OMAP24XX_AUTOSTATE_L3_SHIFT 0
269 #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
271 /* CM_FCLKEN_GFX */
272 #define OMAP24XX_EN_3D_SHIFT 2
273 #define OMAP24XX_EN_3D (1 << 2)
274 #define OMAP24XX_EN_2D_SHIFT 1
275 #define OMAP24XX_EN_2D (1 << 1)
277 /* CM_ICLKEN_GFX specific bits */
279 /* CM_IDLEST_GFX specific bits */
281 /* CM_CLKSEL_GFX specific bits */
283 /* CM_CLKSTCTRL_GFX */
284 #define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
285 #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
287 /* CM_FCLKEN_WKUP specific bits */
289 /* CM_ICLKEN_WKUP specific bits */
290 #define OMAP2430_EN_ICR_SHIFT 6
291 #define OMAP2430_EN_ICR (1 << 6)
292 #define OMAP24XX_EN_OMAPCTRL_SHIFT 5
293 #define OMAP24XX_EN_OMAPCTRL (1 << 5)
294 #define OMAP24XX_EN_WDT1_SHIFT 4
295 #define OMAP24XX_EN_WDT1 (1 << 4)
296 #define OMAP24XX_EN_32KSYNC_SHIFT 1
297 #define OMAP24XX_EN_32KSYNC (1 << 1)
299 /* CM_IDLEST_WKUP specific bits */
300 #define OMAP2430_ST_ICR_SHIFT 6
301 #define OMAP2430_ST_ICR_MASK (1 << 6)
302 #define OMAP24XX_ST_OMAPCTRL_SHIFT 5
303 #define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
304 #define OMAP24XX_ST_WDT1_SHIFT 4
305 #define OMAP24XX_ST_WDT1_MASK (1 << 4)
306 #define OMAP24XX_ST_MPU_WDT_SHIFT 3
307 #define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
308 #define OMAP24XX_ST_32KSYNC_SHIFT 1
309 #define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
311 /* CM_AUTOIDLE_WKUP */
312 #define OMAP24XX_AUTO_OMAPCTRL (1 << 5)
313 #define OMAP24XX_AUTO_WDT1 (1 << 4)
314 #define OMAP24XX_AUTO_MPU_WDT (1 << 3)
315 #define OMAP24XX_AUTO_GPIOS (1 << 2)
316 #define OMAP24XX_AUTO_32KSYNC (1 << 1)
317 #define OMAP24XX_AUTO_GPT1 (1 << 0)
319 /* CM_CLKSEL_WKUP */
320 #define OMAP24XX_CLKSEL_GPT1_SHIFT 0
321 #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
323 /* CM_CLKEN_PLL */
324 #define OMAP24XX_EN_54M_PLL_SHIFT 6
325 #define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
326 #define OMAP24XX_EN_96M_PLL_SHIFT 2
327 #define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
328 #define OMAP24XX_EN_DPLL_SHIFT 0
329 #define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
331 /* CM_IDLEST_CKGEN */
332 #define OMAP24XX_ST_54M_APLL (1 << 9)
333 #define OMAP24XX_ST_96M_APLL (1 << 8)
334 #define OMAP24XX_ST_54M_CLK (1 << 6)
335 #define OMAP24XX_ST_12M_CLK (1 << 5)
336 #define OMAP24XX_ST_48M_CLK (1 << 4)
337 #define OMAP24XX_ST_96M_CLK (1 << 2)
338 #define OMAP24XX_ST_CORE_CLK_SHIFT 0
339 #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
341 /* CM_AUTOIDLE_PLL */
342 #define OMAP24XX_AUTO_54M_SHIFT 6
343 #define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
344 #define OMAP24XX_AUTO_96M_SHIFT 2
345 #define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
346 #define OMAP24XX_AUTO_DPLL_SHIFT 0
347 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
349 /* CM_CLKSEL1_PLL */
350 #define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
351 #define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
352 #define OMAP24XX_APLLS_CLKIN_SHIFT 23
353 #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
354 #define OMAP24XX_DPLL_MULT_SHIFT 12
355 #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
356 #define OMAP24XX_DPLL_DIV_SHIFT 8
357 #define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
358 #define OMAP24XX_54M_SOURCE_SHIFT 5
359 #define OMAP24XX_54M_SOURCE (1 << 5)
360 #define OMAP2430_96M_SOURCE_SHIFT 4
361 #define OMAP2430_96M_SOURCE (1 << 4)
362 #define OMAP24XX_48M_SOURCE_SHIFT 3
363 #define OMAP24XX_48M_SOURCE (1 << 3)
364 #define OMAP2430_ALTCLK_SOURCE_SHIFT 0
365 #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
367 /* CM_CLKSEL2_PLL */
368 #define OMAP24XX_CORE_CLK_SRC_SHIFT 0
369 #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
371 /* CM_FCLKEN_DSP */
372 #define OMAP2420_EN_IVA_COP_SHIFT 10
373 #define OMAP2420_EN_IVA_COP (1 << 10)
374 #define OMAP2420_EN_IVA_MPU_SHIFT 8
375 #define OMAP2420_EN_IVA_MPU (1 << 8)
376 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
377 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0)
379 /* CM_ICLKEN_DSP */
380 #define OMAP2420_EN_DSP_IPI_SHIFT 1
381 #define OMAP2420_EN_DSP_IPI (1 << 1)
383 /* CM_IDLEST_DSP */
384 #define OMAP2420_ST_IVA (1 << 8)
385 #define OMAP2420_ST_IPI (1 << 1)
386 #define OMAP24XX_ST_DSP (1 << 0)
388 /* CM_AUTOIDLE_DSP */
389 #define OMAP2420_AUTO_DSP_IPI (1 << 1)
391 /* CM_CLKSEL_DSP */
392 #define OMAP2420_SYNC_IVA (1 << 13)
393 #define OMAP2420_CLKSEL_IVA_SHIFT 8
394 #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
395 #define OMAP24XX_SYNC_DSP (1 << 7)
396 #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
397 #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
398 #define OMAP24XX_CLKSEL_DSP_SHIFT 0
399 #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
401 /* CM_CLKSTCTRL_DSP */
402 #define OMAP2420_AUTOSTATE_IVA_SHIFT 8
403 #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
404 #define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
405 #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
407 /* CM_FCLKEN_MDM */
408 /* 2430 only */
409 #define OMAP2430_EN_OSC_SHIFT 1
410 #define OMAP2430_EN_OSC (1 << 1)
412 /* CM_ICLKEN_MDM */
413 /* 2430 only */
414 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
415 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0)
417 /* CM_IDLEST_MDM specific bits */
418 /* 2430 only */
420 /* CM_AUTOIDLE_MDM */
421 /* 2430 only */
422 #define OMAP2430_AUTO_OSC (1 << 1)
423 #define OMAP2430_AUTO_MDM (1 << 0)
425 /* CM_CLKSEL_MDM */
426 /* 2430 only */
427 #define OMAP2430_SYNC_MDM (1 << 4)
428 #define OMAP2430_CLKSEL_MDM_SHIFT 0
429 #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
431 /* CM_CLKSTCTRL_MDM */
432 /* 2430 only */
433 #define OMAP2430_AUTOSTATE_MDM_SHIFT 0
434 #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
436 #endif