DaVinci: EDMA: Add queue 2 and 3 for DM365 and DM6467
[linux-ginger.git] / drivers / net / cxgb3 / cxgb3_ctl_defs.h
blob369fe711fd7f0dc8e974c99acbd912add1bdb773
1 /*
2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
32 #ifndef _CXGB3_OFFLOAD_CTL_DEFS_H
33 #define _CXGB3_OFFLOAD_CTL_DEFS_H
35 enum {
36 GET_MAX_OUTSTANDING_WR = 0,
37 GET_TX_MAX_CHUNK = 1,
38 GET_TID_RANGE = 2,
39 GET_STID_RANGE = 3,
40 GET_RTBL_RANGE = 4,
41 GET_L2T_CAPACITY = 5,
42 GET_MTUS = 6,
43 GET_WR_LEN = 7,
44 GET_IFF_FROM_MAC = 8,
45 GET_DDP_PARAMS = 9,
46 GET_PORTS = 10,
48 ULP_ISCSI_GET_PARAMS = 11,
49 ULP_ISCSI_SET_PARAMS = 12,
51 RDMA_GET_PARAMS = 13,
52 RDMA_CQ_OP = 14,
53 RDMA_CQ_SETUP = 15,
54 RDMA_CQ_DISABLE = 16,
55 RDMA_CTRL_QP_SETUP = 17,
56 RDMA_GET_MEM = 18,
57 RDMA_GET_MIB = 19,
59 GET_RX_PAGE_INFO = 50,
60 GET_ISCSI_IPV4ADDR = 51,
62 GET_EMBEDDED_INFO = 70,
66 * Structure used to describe a TID range. Valid TIDs are [base, base+num).
68 struct tid_range {
69 unsigned int base; /* first TID */
70 unsigned int num; /* number of TIDs in range */
74 * Structure used to request the size and contents of the MTU table.
76 struct mtutab {
77 unsigned int size; /* # of entries in the MTU table */
78 const unsigned short *mtus; /* the MTU table values */
81 struct net_device;
84 * Structure used to request the adapter net_device owning a given MAC address.
86 struct iff_mac {
87 struct net_device *dev; /* the net_device */
88 const unsigned char *mac_addr; /* MAC address to lookup */
89 u16 vlan_tag;
92 /* Structure used to request a port's iSCSI IPv4 address */
93 struct iscsi_ipv4addr {
94 struct net_device *dev; /* the net_device */
95 __be32 ipv4addr; /* the return iSCSI IPv4 address */
98 struct pci_dev;
101 * Structure used to request the TCP DDP parameters.
103 struct ddp_params {
104 unsigned int llimit; /* TDDP region start address */
105 unsigned int ulimit; /* TDDP region end address */
106 unsigned int tag_mask; /* TDDP tag mask */
107 struct pci_dev *pdev;
110 struct adap_ports {
111 unsigned int nports; /* number of ports on this adapter */
112 struct net_device *lldevs[2];
116 * Structure used to return information to the iscsi layer.
118 struct ulp_iscsi_info {
119 unsigned int offset;
120 unsigned int llimit;
121 unsigned int ulimit;
122 unsigned int tagmask;
123 u8 pgsz_factor[4];
124 unsigned int max_rxsz;
125 unsigned int max_txsz;
126 struct pci_dev *pdev;
130 * Structure used to return information to the RDMA layer.
132 struct rdma_info {
133 unsigned int tpt_base; /* TPT base address */
134 unsigned int tpt_top; /* TPT last entry address */
135 unsigned int pbl_base; /* PBL base address */
136 unsigned int pbl_top; /* PBL last entry address */
137 unsigned int rqt_base; /* RQT base address */
138 unsigned int rqt_top; /* RQT last entry address */
139 unsigned int udbell_len; /* user doorbell region length */
140 unsigned long udbell_physbase; /* user doorbell physical start addr */
141 void __iomem *kdb_addr; /* kernel doorbell register address */
142 struct pci_dev *pdev; /* associated PCI device */
146 * Structure used to request an operation on an RDMA completion queue.
148 struct rdma_cq_op {
149 unsigned int id;
150 unsigned int op;
151 unsigned int credits;
155 * Structure used to setup RDMA completion queues.
157 struct rdma_cq_setup {
158 unsigned int id;
159 unsigned long long base_addr;
160 unsigned int size;
161 unsigned int credits;
162 unsigned int credit_thres;
163 unsigned int ovfl_mode;
167 * Structure used to setup the RDMA control egress context.
169 struct rdma_ctrlqp_setup {
170 unsigned long long base_addr;
171 unsigned int size;
175 * Offload TX/RX page information.
177 struct ofld_page_info {
178 unsigned int page_size; /* Page size, should be a power of 2 */
179 unsigned int num; /* Number of pages */
183 * Structure used to get firmware and protocol engine versions.
185 struct ch_embedded_info {
186 u32 fw_vers;
187 u32 tp_vers;
189 #endif /* _CXGB3_OFFLOAD_CTL_DEFS_H */