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DaVinci: EDMA: Add queue 2 and 3 for DM365 and DM6467
[linux-ginger.git] / drivers / net / dl2k.c
blob4b6a219fecea8b44be1f192db3b1352b28bc5702
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
12
13 #define DRV_NAME "DL2000/TC902x-based linux driver"
14 #define DRV_VERSION "v1.19"
15 #define DRV_RELDATE "2007/08/12"
16 #include "dl2k.h"
17 #include <linux/dma-mapping.h>
18
19 static char version[] __devinitdata =
20 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
21 #define MAX_UNITS 8
22 static int mtu[MAX_UNITS];
23 static int vlan[MAX_UNITS];
24 static int jumbo[MAX_UNITS];
25 static char *media[MAX_UNITS];
26 static int tx_flow=-1;
27 static int rx_flow=-1;
28 static int copy_thresh;
29 static int rx_coalesce=10; /* Rx frame count each interrupt */
30 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
31 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
32
33
34 MODULE_AUTHOR ("Edward Peng");
35 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
36 MODULE_LICENSE("GPL");
37 module_param_array(mtu, int, NULL, 0);
38 module_param_array(media, charp, NULL, 0);
39 module_param_array(vlan, int, NULL, 0);
40 module_param_array(jumbo, int, NULL, 0);
41 module_param(tx_flow, int, 0);
42 module_param(rx_flow, int, 0);
43 module_param(copy_thresh, int, 0);
44 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
45 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
46 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
47
48
49 /* Enable the default interrupts */
50 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
51 UpdateStats | LinkEvent)
52 #define EnableInt() \
53 writew(DEFAULT_INTR, ioaddr + IntEnable)
54
55 static const int max_intrloop = 50;
56 static const int multicast_filter_limit = 0x40;
57
58 static int rio_open (struct net_device *dev);
59 static void rio_timer (unsigned long data);
60 static void rio_tx_timeout (struct net_device *dev);
61 static void alloc_list (struct net_device *dev);
62 static int start_xmit (struct sk_buff *skb, struct net_device *dev);
63 static irqreturn_t rio_interrupt (int irq, void *dev_instance);
64 static void rio_free_tx (struct net_device *dev, int irq);
65 static void tx_error (struct net_device *dev, int tx_status);
66 static int receive_packet (struct net_device *dev);
67 static void rio_error (struct net_device *dev, int int_status);
68 static int change_mtu (struct net_device *dev, int new_mtu);
69 static void set_multicast (struct net_device *dev);
70 static struct net_device_stats *get_stats (struct net_device *dev);
71 static int clear_stats (struct net_device *dev);
72 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
73 static int rio_close (struct net_device *dev);
74 static int find_miiphy (struct net_device *dev);
75 static int parse_eeprom (struct net_device *dev);
76 static int read_eeprom (long ioaddr, int eep_addr);
77 static int mii_wait_link (struct net_device *dev, int wait);
78 static int mii_set_media (struct net_device *dev);
79 static int mii_get_media (struct net_device *dev);
80 static int mii_set_media_pcs (struct net_device *dev);
81 static int mii_get_media_pcs (struct net_device *dev);
82 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
83 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
84 u16 data);
85
86 static const struct ethtool_ops ethtool_ops;
87
88 static const struct net_device_ops netdev_ops = {
89 .ndo_open = rio_open,
90 .ndo_start_xmit = start_xmit,
91 .ndo_stop = rio_close,
92 .ndo_get_stats = get_stats,
93 .ndo_validate_addr = eth_validate_addr,
94 .ndo_set_mac_address = eth_mac_addr,
95 .ndo_set_multicast_list = set_multicast,
96 .ndo_do_ioctl = rio_ioctl,
97 .ndo_tx_timeout = rio_tx_timeout,
98 .ndo_change_mtu = change_mtu,
99 };
100
101 static int __devinit
102 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
103 {
104 struct net_device *dev;
105 struct netdev_private *np;
106 static int card_idx;
107 int chip_idx = ent->driver_data;
108 int err, irq;
109 long ioaddr;
110 static int version_printed;
111 void *ring_space;
112 dma_addr_t ring_dma;
113
114 if (!version_printed++)
115 printk ("%s", version);
116
117 err = pci_enable_device (pdev);
118 if (err)
119 return err;
120
121 irq = pdev->irq;
122 err = pci_request_regions (pdev, "dl2k");
123 if (err)
124 goto err_out_disable;
125
126 pci_set_master (pdev);
127 dev = alloc_etherdev (sizeof (*np));
128 if (!dev) {
129 err = -ENOMEM;
130 goto err_out_res;
131 }
132 SET_NETDEV_DEV(dev, &pdev->dev);
133
134 #ifdef MEM_MAPPING
135 ioaddr = pci_resource_start (pdev, 1);
136 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
137 if (!ioaddr) {
138 err = -ENOMEM;
139 goto err_out_dev;
140 }
141 #else
142 ioaddr = pci_resource_start (pdev, 0);
143 #endif
144 dev->base_addr = ioaddr;
145 dev->irq = irq;
146 np = netdev_priv(dev);
147 np->chip_id = chip_idx;
148 np->pdev = pdev;
149 spin_lock_init (&np->tx_lock);
150 spin_lock_init (&np->rx_lock);
151
152 /* Parse manual configuration */
153 np->an_enable = 1;
154 np->tx_coalesce = 1;
155 if (card_idx < MAX_UNITS) {
156 if (media[card_idx] != NULL) {
157 np->an_enable = 0;
158 if (strcmp (media[card_idx], "auto") == 0 ||
159 strcmp (media[card_idx], "autosense") == 0 ||
160 strcmp (media[card_idx], "0") == 0 ) {
161 np->an_enable = 2;
162 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
163 strcmp (media[card_idx], "4") == 0) {
164 np->speed = 100;
165 np->full_duplex = 1;
166 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
167 || strcmp (media[card_idx], "3") == 0) {
168 np->speed = 100;
169 np->full_duplex = 0;
170 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
171 strcmp (media[card_idx], "2") == 0) {
172 np->speed = 10;
173 np->full_duplex = 1;
174 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
175 strcmp (media[card_idx], "1") == 0) {
176 np->speed = 10;
177 np->full_duplex = 0;
178 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
179 strcmp (media[card_idx], "6") == 0) {
180 np->speed=1000;
181 np->full_duplex=1;
182 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
183 strcmp (media[card_idx], "5") == 0) {
184 np->speed = 1000;
185 np->full_duplex = 0;
186 } else {
187 np->an_enable = 1;
188 }
189 }
190 if (jumbo[card_idx] != 0) {
191 np->jumbo = 1;
192 dev->mtu = MAX_JUMBO;
193 } else {
194 np->jumbo = 0;
195 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
196 dev->mtu = mtu[card_idx];
197 }
198 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
199 vlan[card_idx] : 0;
200 if (rx_coalesce > 0 && rx_timeout > 0) {
201 np->rx_coalesce = rx_coalesce;
202 np->rx_timeout = rx_timeout;
203 np->coalesce = 1;
204 }
205 np->tx_flow = (tx_flow == 0) ? 0 : 1;
206 np->rx_flow = (rx_flow == 0) ? 0 : 1;
207
208 if (tx_coalesce < 1)
209 tx_coalesce = 1;
210 else if (tx_coalesce > TX_RING_SIZE-1)
211 tx_coalesce = TX_RING_SIZE - 1;
212 }
213 dev->netdev_ops = &netdev_ops;
214 dev->watchdog_timeo = TX_TIMEOUT;
215 SET_ETHTOOL_OPS(dev, &ethtool_ops);
216 #if 0
217 dev->features = NETIF_F_IP_CSUM;
218 #endif
219 pci_set_drvdata (pdev, dev);
220
221 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
222 if (!ring_space)
223 goto err_out_iounmap;
224 np->tx_ring = (struct netdev_desc *) ring_space;
225 np->tx_ring_dma = ring_dma;
226
227 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
228 if (!ring_space)
229 goto err_out_unmap_tx;
230 np->rx_ring = (struct netdev_desc *) ring_space;
231 np->rx_ring_dma = ring_dma;
232
233 /* Parse eeprom data */
234 parse_eeprom (dev);
235
236 /* Find PHY address */
237 err = find_miiphy (dev);
238 if (err)
239 goto err_out_unmap_rx;
240
241 /* Fiber device? */
242 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
243 np->link_status = 0;
244 /* Set media and reset PHY */
245 if (np->phy_media) {
246 /* default Auto-Negotiation for fiber deivices */
247 if (np->an_enable == 2) {
248 np->an_enable = 1;
249 }
250 mii_set_media_pcs (dev);
251 } else {
252 /* Auto-Negotiation is mandatory for 1000BASE-T,
253 IEEE 802.3ab Annex 28D page 14 */
254 if (np->speed == 1000)
255 np->an_enable = 1;
256 mii_set_media (dev);
257 }
258
259 err = register_netdev (dev);
260 if (err)
261 goto err_out_unmap_rx;
262
263 card_idx++;
264
265 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
266 dev->name, np->name, dev->dev_addr, irq);
267 if (tx_coalesce > 1)
268 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
269 tx_coalesce);
270 if (np->coalesce)
271 printk(KERN_INFO
272 "rx_coalesce:\t%d packets\n"
273 "rx_timeout: \t%d ns\n",
274 np->rx_coalesce, np->rx_timeout*640);
275 if (np->vlan)
276 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
277 return 0;
278
279 err_out_unmap_rx:
280 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
281 err_out_unmap_tx:
282 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
283 err_out_iounmap:
284 #ifdef MEM_MAPPING
285 iounmap ((void *) ioaddr);
286
287 err_out_dev:
288 #endif
289 free_netdev (dev);
290
291 err_out_res:
292 pci_release_regions (pdev);
293
294 err_out_disable:
295 pci_disable_device (pdev);
296 return err;
297 }
298
299 static int
300 find_miiphy (struct net_device *dev)
301 {
302 int i, phy_found = 0;
303 struct netdev_private *np;
304 long ioaddr;
305 np = netdev_priv(dev);
306 ioaddr = dev->base_addr;
307 np->phy_addr = 1;
308
309 for (i = 31; i >= 0; i--) {
310 int mii_status = mii_read (dev, i, 1);
311 if (mii_status != 0xffff && mii_status != 0x0000) {
312 np->phy_addr = i;
313 phy_found++;
314 }
315 }
316 if (!phy_found) {
317 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
318 return -ENODEV;
319 }
320 return 0;
321 }
322
323 static int
324 parse_eeprom (struct net_device *dev)
325 {
326 int i, j;
327 long ioaddr = dev->base_addr;
328 u8 sromdata[256];
329 u8 *psib;
330 u32 crc;
331 PSROM_t psrom = (PSROM_t) sromdata;
332 struct netdev_private *np = netdev_priv(dev);
333
334 int cid, next;
335
336 #ifdef MEM_MAPPING
337 ioaddr = pci_resource_start (np->pdev, 0);
338 #endif
339 /* Read eeprom */
340 for (i = 0; i < 128; i++) {
341 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i));
342 }
343 #ifdef MEM_MAPPING
344 ioaddr = dev->base_addr;
345 #endif
346 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
347 /* Check CRC */
348 crc = ~ether_crc_le (256 - 4, sromdata);
349 if (psrom->crc != crc) {
350 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
351 dev->name);
352 return -1;
353 }
354 }
355
356 /* Set MAC address */
357 for (i = 0; i < 6; i++)
358 dev->dev_addr[i] = psrom->mac_addr[i];
359
360 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
361 return 0;
362 }
363
364 /* Parse Software Information Block */
365 i = 0x30;
366 psib = (u8 *) sromdata;
367 do {
368 cid = psib[i++];
369 next = psib[i++];
370 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
371 printk (KERN_ERR "Cell data error\n");
372 return -1;
373 }
374 switch (cid) {
375 case 0: /* Format version */
376 break;
377 case 1: /* End of cell */
378 return 0;
379 case 2: /* Duplex Polarity */
380 np->duplex_polarity = psib[i];
381 writeb (readb (ioaddr + PhyCtrl) | psib[i],
382 ioaddr + PhyCtrl);
383 break;
384 case 3: /* Wake Polarity */
385 np->wake_polarity = psib[i];
386 break;
387 case 9: /* Adapter description */
388 j = (next - i > 255) ? 255 : next - i;
389 memcpy (np->name, &(psib[i]), j);
390 break;
391 case 4:
392 case 5:
393 case 6:
394 case 7:
395 case 8: /* Reversed */
396 break;
397 default: /* Unknown cell */
398 return -1;
399 }
400 i = next;
401 } while (1);
402
403 return 0;
404 }
405
406 static int
407 rio_open (struct net_device *dev)
408 {
409 struct netdev_private *np = netdev_priv(dev);
410 long ioaddr = dev->base_addr;
411 int i;
412 u16 macctrl;
413
414 i = request_irq (dev->irq, &rio_interrupt, IRQF_SHARED, dev->name, dev);
415 if (i)
416 return i;
417
418 /* Reset all logic functions */
419 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
420 ioaddr + ASICCtrl + 2);
421 mdelay(10);
422
423 /* DebugCtrl bit 4, 5, 9 must set */
424 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
425
426 /* Jumbo frame */
427 if (np->jumbo != 0)
428 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
429
430 alloc_list (dev);
431
432 /* Get station address */
433 for (i = 0; i < 6; i++)
434 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
435
436 set_multicast (dev);
437 if (np->coalesce) {
438 writel (np->rx_coalesce | np->rx_timeout << 16,
439 ioaddr + RxDMAIntCtrl);
440 }
441 /* Set RIO to poll every N*320nsec. */
442 writeb (0x20, ioaddr + RxDMAPollPeriod);
443 writeb (0xff, ioaddr + TxDMAPollPeriod);
444 writeb (0x30, ioaddr + RxDMABurstThresh);
445 writeb (0x30, ioaddr + RxDMAUrgentThresh);
446 writel (0x0007ffff, ioaddr + RmonStatMask);
447 /* clear statistics */
448 clear_stats (dev);
449
450 /* VLAN supported */
451 if (np->vlan) {
452 /* priority field in RxDMAIntCtrl */
453 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
454 ioaddr + RxDMAIntCtrl);
455 /* VLANId */
456 writew (np->vlan, ioaddr + VLANId);
457 /* Length/Type should be 0x8100 */
458 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
459 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
460 VLAN information tagged by TFC' VID, CFI fields. */
461 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
462 ioaddr + MACCtrl);
463 }
464
465 init_timer (&np->timer);
466 np->timer.expires = jiffies + 1*HZ;
467 np->timer.data = (unsigned long) dev;
468 np->timer.function = &rio_timer;
469 add_timer (&np->timer);
470
471 /* Start Tx/Rx */
472 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
473 ioaddr + MACCtrl);
474
475 macctrl = 0;
476 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
477 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
478 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
479 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
480 writew(macctrl, ioaddr + MACCtrl);
481
482 netif_start_queue (dev);
483
484 /* Enable default interrupts */
485 EnableInt ();
486 return 0;
487 }
488
489 static void
490 rio_timer (unsigned long data)
491 {
492 struct net_device *dev = (struct net_device *)data;
493 struct netdev_private *np = netdev_priv(dev);
494 unsigned int entry;
495 int next_tick = 1*HZ;
496 unsigned long flags;
497
498 spin_lock_irqsave(&np->rx_lock, flags);
499 /* Recover rx ring exhausted error */
500 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
501 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
502 /* Re-allocate skbuffs to fill the descriptor ring */
503 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
504 struct sk_buff *skb;
505 entry = np->old_rx % RX_RING_SIZE;
506 /* Dropped packets don't need to re-allocate */
507 if (np->rx_skbuff[entry] == NULL) {
508 skb = netdev_alloc_skb (dev, np->rx_buf_sz);
509 if (skb == NULL) {
510 np->rx_ring[entry].fraginfo = 0;
511 printk (KERN_INFO
512 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
513 dev->name, entry);
514 break;
515 }
516 np->rx_skbuff[entry] = skb;
517 /* 16 byte align the IP header */
518 skb_reserve (skb, 2);
519 np->rx_ring[entry].fraginfo =
520 cpu_to_le64 (pci_map_single
521 (np->pdev, skb->data, np->rx_buf_sz,
522 PCI_DMA_FROMDEVICE));
523 }
524 np->rx_ring[entry].fraginfo |=
525 cpu_to_le64((u64)np->rx_buf_sz << 48);
526 np->rx_ring[entry].status = 0;
527 } /* end for */
528 } /* end if */
529 spin_unlock_irqrestore (&np->rx_lock, flags);
530 np->timer.expires = jiffies + next_tick;
531 add_timer(&np->timer);
532 }
533
534 static void
535 rio_tx_timeout (struct net_device *dev)
536 {
537 long ioaddr = dev->base_addr;
538
539 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
540 dev->name, readl (ioaddr + TxStatus));
541 rio_free_tx(dev, 0);
542 dev->if_port = 0;
543 dev->trans_start = jiffies; /* prevent tx timeout */
544 }
545
546 /* allocate and initialize Tx and Rx descriptors */
547 static void
548 alloc_list (struct net_device *dev)
549 {
550 struct netdev_private *np = netdev_priv(dev);
551 int i;
552
553 np->cur_rx = np->cur_tx = 0;
554 np->old_rx = np->old_tx = 0;
555 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
556
557 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
558 for (i = 0; i < TX_RING_SIZE; i++) {
559 np->tx_skbuff[i] = NULL;
560 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
561 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
562 ((i+1)%TX_RING_SIZE) *
563 sizeof (struct netdev_desc));
564 }
565
566 /* Initialize Rx descriptors */
567 for (i = 0; i < RX_RING_SIZE; i++) {
568 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
569 ((i + 1) % RX_RING_SIZE) *
570 sizeof (struct netdev_desc));
571 np->rx_ring[i].status = 0;
572 np->rx_ring[i].fraginfo = 0;
573 np->rx_skbuff[i] = NULL;
574 }
575
576 /* Allocate the rx buffers */
577 for (i = 0; i < RX_RING_SIZE; i++) {
578 /* Allocated fixed size of skbuff */
579 struct sk_buff *skb = netdev_alloc_skb (dev, np->rx_buf_sz);
580 np->rx_skbuff[i] = skb;
581 if (skb == NULL) {
582 printk (KERN_ERR
583 "%s: alloc_list: allocate Rx buffer error! ",
584 dev->name);
585 break;
586 }
587 skb_reserve (skb, 2); /* 16 byte align the IP header. */
588 /* Rubicon now supports 40 bits of addressing space. */
589 np->rx_ring[i].fraginfo =
590 cpu_to_le64 ( pci_map_single (
591 np->pdev, skb->data, np->rx_buf_sz,
592 PCI_DMA_FROMDEVICE));
593 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
594 }
595
596 /* Set RFDListPtr */
597 writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0);
598 writel (0, dev->base_addr + RFDListPtr1);
599
600 return;
601 }
602
603 static int
604 start_xmit (struct sk_buff *skb, struct net_device *dev)
605 {
606 struct netdev_private *np = netdev_priv(dev);
607 struct netdev_desc *txdesc;
608 unsigned entry;
609 u32 ioaddr;
610 u64 tfc_vlan_tag = 0;
611
612 if (np->link_status == 0) { /* Link Down */
613 dev_kfree_skb(skb);
614 return NETDEV_TX_OK;
615 }
616 ioaddr = dev->base_addr;
617 entry = np->cur_tx % TX_RING_SIZE;
618 np->tx_skbuff[entry] = skb;
619 txdesc = &np->tx_ring[entry];
620
621 #if 0
622 if (skb->ip_summed == CHECKSUM_PARTIAL) {
623 txdesc->status |=
624 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
625 IPChecksumEnable);
626 }
627 #endif
628 if (np->vlan) {
629 tfc_vlan_tag = VLANTagInsert |
630 ((u64)np->vlan << 32) |
631 ((u64)skb->priority << 45);
632 }
633 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
634 skb->len,
635 PCI_DMA_TODEVICE));
636 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
637
638 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
639 * Work around: Always use 1 descriptor in 10Mbps mode */
640 if (entry % np->tx_coalesce == 0 || np->speed == 10)
641 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
642 WordAlignDisable |
643 TxDMAIndicate |
644 (1 << FragCountShift));
645 else
646 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
647 WordAlignDisable |
648 (1 << FragCountShift));
649
650 /* TxDMAPollNow */
651 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
652 /* Schedule ISR */
653 writel(10000, ioaddr + CountDown);
654 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
655 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
656 < TX_QUEUE_LEN - 1 && np->speed != 10) {
657 /* do nothing */
658 } else if (!netif_queue_stopped(dev)) {
659 netif_stop_queue (dev);
660 }
661
662 /* The first TFDListPtr */
663 if (readl (dev->base_addr + TFDListPtr0) == 0) {
664 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
665 dev->base_addr + TFDListPtr0);
666 writel (0, dev->base_addr + TFDListPtr1);
667 }
668
669 return NETDEV_TX_OK;
670 }
671
672 static irqreturn_t
673 rio_interrupt (int irq, void *dev_instance)
674 {
675 struct net_device *dev = dev_instance;
676 struct netdev_private *np;
677 unsigned int_status;
678 long ioaddr;
679 int cnt = max_intrloop;
680 int handled = 0;
681
682 ioaddr = dev->base_addr;
683 np = netdev_priv(dev);
684 while (1) {
685 int_status = readw (ioaddr + IntStatus);
686 writew (int_status, ioaddr + IntStatus);
687 int_status &= DEFAULT_INTR;
688 if (int_status == 0 || --cnt < 0)
689 break;
690 handled = 1;
691 /* Processing received packets */
692 if (int_status & RxDMAComplete)
693 receive_packet (dev);
694 /* TxDMAComplete interrupt */
695 if ((int_status & (TxDMAComplete|IntRequested))) {
696 int tx_status;
697 tx_status = readl (ioaddr + TxStatus);
698 if (tx_status & 0x01)
699 tx_error (dev, tx_status);
700 /* Free used tx skbuffs */
701 rio_free_tx (dev, 1);
702 }
703
704 /* Handle uncommon events */
705 if (int_status &
706 (HostError | LinkEvent | UpdateStats))
707 rio_error (dev, int_status);
708 }
709 if (np->cur_tx != np->old_tx)
710 writel (100, ioaddr + CountDown);
711 return IRQ_RETVAL(handled);
712 }
713
714 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
715 {
716 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
717 }
718
719 static void
720 rio_free_tx (struct net_device *dev, int irq)
721 {
722 struct netdev_private *np = netdev_priv(dev);
723 int entry = np->old_tx % TX_RING_SIZE;
724 int tx_use = 0;
725 unsigned long flag = 0;
726
727 if (irq)
728 spin_lock(&np->tx_lock);
729 else
730 spin_lock_irqsave(&np->tx_lock, flag);
731
732 /* Free used tx skbuffs */
733 while (entry != np->cur_tx) {
734 struct sk_buff *skb;
735
736 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
737 break;
738 skb = np->tx_skbuff[entry];
739 pci_unmap_single (np->pdev,
740 desc_to_dma(&np->tx_ring[entry]),
741 skb->len, PCI_DMA_TODEVICE);
742 if (irq)
743 dev_kfree_skb_irq (skb);
744 else
745 dev_kfree_skb (skb);
746
747 np->tx_skbuff[entry] = NULL;
748 entry = (entry + 1) % TX_RING_SIZE;
749 tx_use++;
750 }
751 if (irq)
752 spin_unlock(&np->tx_lock);
753 else
754 spin_unlock_irqrestore(&np->tx_lock, flag);
755 np->old_tx = entry;
756
757 /* If the ring is no longer full, clear tx_full and
758 call netif_wake_queue() */
759
760 if (netif_queue_stopped(dev) &&
761 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
762 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
763 netif_wake_queue (dev);
764 }
765 }
766
767 static void
768 tx_error (struct net_device *dev, int tx_status)
769 {
770 struct netdev_private *np;
771 long ioaddr = dev->base_addr;
772 int frame_id;
773 int i;
774
775 np = netdev_priv(dev);
776
777 frame_id = (tx_status & 0xffff0000);
778 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
779 dev->name, tx_status, frame_id);
780 np->stats.tx_errors++;
781 /* Ttransmit Underrun */
782 if (tx_status & 0x10) {
783 np->stats.tx_fifo_errors++;
784 writew (readw (ioaddr + TxStartThresh) + 0x10,
785 ioaddr + TxStartThresh);
786 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
787 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
788 ioaddr + ASICCtrl + 2);
789 /* Wait for ResetBusy bit clear */
790 for (i = 50; i > 0; i--) {
791 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
792 break;
793 mdelay (1);
794 }
795 rio_free_tx (dev, 1);
796 /* Reset TFDListPtr */
797 writel (np->tx_ring_dma +
798 np->old_tx * sizeof (struct netdev_desc),
799 dev->base_addr + TFDListPtr0);
800 writel (0, dev->base_addr + TFDListPtr1);
801
802 /* Let TxStartThresh stay default value */
803 }
804 /* Late Collision */
805 if (tx_status & 0x04) {
806 np->stats.tx_fifo_errors++;
807 /* TxReset and clear FIFO */
808 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
809 /* Wait reset done */
810 for (i = 50; i > 0; i--) {
811 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
812 break;
813 mdelay (1);
814 }
815 /* Let TxStartThresh stay default value */
816 }
817 /* Maximum Collisions */
818 #ifdef ETHER_STATS
819 if (tx_status & 0x08)
820 np->stats.collisions16++;
821 #else
822 if (tx_status & 0x08)
823 np->stats.collisions++;
824 #endif
825 /* Restart the Tx */
826 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
827 }
828
829 static int
830 receive_packet (struct net_device *dev)
831 {
832 struct netdev_private *np = netdev_priv(dev);
833 int entry = np->cur_rx % RX_RING_SIZE;
834 int cnt = 30;
835
836 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
837 while (1) {
838 struct netdev_desc *desc = &np->rx_ring[entry];
839 int pkt_len;
840 u64 frame_status;
841
842 if (!(desc->status & cpu_to_le64(RFDDone)) ||
843 !(desc->status & cpu_to_le64(FrameStart)) ||
844 !(desc->status & cpu_to_le64(FrameEnd)))
845 break;
846
847 /* Chip omits the CRC. */
848 frame_status = le64_to_cpu(desc->status);
849 pkt_len = frame_status & 0xffff;
850 if (--cnt < 0)
851 break;
852 /* Update rx error statistics, drop packet. */
853 if (frame_status & RFS_Errors) {
854 np->stats.rx_errors++;
855 if (frame_status & (RxRuntFrame | RxLengthError))
856 np->stats.rx_length_errors++;
857 if (frame_status & RxFCSError)
858 np->stats.rx_crc_errors++;
859 if (frame_status & RxAlignmentError && np->speed != 1000)
860 np->stats.rx_frame_errors++;
861 if (frame_status & RxFIFOOverrun)
862 np->stats.rx_fifo_errors++;
863 } else {
864 struct sk_buff *skb;
865
866 /* Small skbuffs for short packets */
867 if (pkt_len > copy_thresh) {
868 pci_unmap_single (np->pdev,
869 desc_to_dma(desc),
870 np->rx_buf_sz,
871 PCI_DMA_FROMDEVICE);
872 skb_put (skb = np->rx_skbuff[entry], pkt_len);
873 np->rx_skbuff[entry] = NULL;
874 } else if ((skb = netdev_alloc_skb(dev, pkt_len + 2))) {
875 pci_dma_sync_single_for_cpu(np->pdev,
876 desc_to_dma(desc),
877 np->rx_buf_sz,
878 PCI_DMA_FROMDEVICE);
879 /* 16 byte align the IP header */
880 skb_reserve (skb, 2);
881 skb_copy_to_linear_data (skb,
882 np->rx_skbuff[entry]->data,
883 pkt_len);
884 skb_put (skb, pkt_len);
885 pci_dma_sync_single_for_device(np->pdev,
886 desc_to_dma(desc),
887 np->rx_buf_sz,
888 PCI_DMA_FROMDEVICE);
889 }
890 skb->protocol = eth_type_trans (skb, dev);
891 #if 0
892 /* Checksum done by hw, but csum value unavailable. */
893 if (np->pdev->pci_rev_id >= 0x0c &&
894 !(frame_status & (TCPError | UDPError | IPError))) {
895 skb->ip_summed = CHECKSUM_UNNECESSARY;
896 }
897 #endif
898 netif_rx (skb);
899 }
900 entry = (entry + 1) % RX_RING_SIZE;
901 }
902 spin_lock(&np->rx_lock);
903 np->cur_rx = entry;
904 /* Re-allocate skbuffs to fill the descriptor ring */
905 entry = np->old_rx;
906 while (entry != np->cur_rx) {
907 struct sk_buff *skb;
908 /* Dropped packets don't need to re-allocate */
909 if (np->rx_skbuff[entry] == NULL) {
910 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
911 if (skb == NULL) {
912 np->rx_ring[entry].fraginfo = 0;
913 printk (KERN_INFO
914 "%s: receive_packet: "
915 "Unable to re-allocate Rx skbuff.#%d\n",
916 dev->name, entry);
917 break;
918 }
919 np->rx_skbuff[entry] = skb;
920 /* 16 byte align the IP header */
921 skb_reserve (skb, 2);
922 np->rx_ring[entry].fraginfo =
923 cpu_to_le64 (pci_map_single
924 (np->pdev, skb->data, np->rx_buf_sz,
925 PCI_DMA_FROMDEVICE));
926 }
927 np->rx_ring[entry].fraginfo |=
928 cpu_to_le64((u64)np->rx_buf_sz << 48);
929 np->rx_ring[entry].status = 0;
930 entry = (entry + 1) % RX_RING_SIZE;
931 }
932 np->old_rx = entry;
933 spin_unlock(&np->rx_lock);
934 return 0;
935 }
936
937 static void
938 rio_error (struct net_device *dev, int int_status)
939 {
940 long ioaddr = dev->base_addr;
941 struct netdev_private *np = netdev_priv(dev);
942 u16 macctrl;
943
944 /* Link change event */
945 if (int_status & LinkEvent) {
946 if (mii_wait_link (dev, 10) == 0) {
947 printk (KERN_INFO "%s: Link up\n", dev->name);
948 if (np->phy_media)
949 mii_get_media_pcs (dev);
950 else
951 mii_get_media (dev);
952 if (np->speed == 1000)
953 np->tx_coalesce = tx_coalesce;
954 else
955 np->tx_coalesce = 1;
956 macctrl = 0;
957 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
958 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
959 macctrl |= (np->tx_flow) ?
960 TxFlowControlEnable : 0;
961 macctrl |= (np->rx_flow) ?
962 RxFlowControlEnable : 0;
963 writew(macctrl, ioaddr + MACCtrl);
964 np->link_status = 1;
965 netif_carrier_on(dev);
966 } else {
967 printk (KERN_INFO "%s: Link off\n", dev->name);
968 np->link_status = 0;
969 netif_carrier_off(dev);
970 }
971 }
972
973 /* UpdateStats statistics registers */
974 if (int_status & UpdateStats) {
975 get_stats (dev);
976 }
977
978 /* PCI Error, a catastronphic error related to the bus interface
979 occurs, set GlobalReset and HostReset to reset. */
980 if (int_status & HostError) {
981 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
982 dev->name, int_status);
983 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
984 mdelay (500);
985 }
986 }
987
988 static struct net_device_stats *
989 get_stats (struct net_device *dev)
990 {
991 long ioaddr = dev->base_addr;
992 struct netdev_private *np = netdev_priv(dev);
993 #ifdef MEM_MAPPING
994 int i;
995 #endif
996 unsigned int stat_reg;
997
998 /* All statistics registers need to be acknowledged,
999 else statistic overflow could cause problems */
1000
1001 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
1002 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
1003 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1004 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1005
1006 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1007 np->stats.collisions += readl (ioaddr + SingleColFrames)
1008 + readl (ioaddr + MultiColFrames);
1009
1010 /* detailed tx errors */
1011 stat_reg = readw (ioaddr + FramesAbortXSColls);
1012 np->stats.tx_aborted_errors += stat_reg;
1013 np->stats.tx_errors += stat_reg;
1014
1015 stat_reg = readw (ioaddr + CarrierSenseErrors);
1016 np->stats.tx_carrier_errors += stat_reg;
1017 np->stats.tx_errors += stat_reg;
1018
1019 /* Clear all other statistic register. */
1020 readl (ioaddr + McstOctetXmtOk);
1021 readw (ioaddr + BcstFramesXmtdOk);
1022 readl (ioaddr + McstFramesXmtdOk);
1023 readw (ioaddr + BcstFramesRcvdOk);
1024 readw (ioaddr + MacControlFramesRcvd);
1025 readw (ioaddr + FrameTooLongErrors);
1026 readw (ioaddr + InRangeLengthErrors);
1027 readw (ioaddr + FramesCheckSeqErrors);
1028 readw (ioaddr + FramesLostRxErrors);
1029 readl (ioaddr + McstOctetXmtOk);
1030 readl (ioaddr + BcstOctetXmtOk);
1031 readl (ioaddr + McstFramesXmtdOk);
1032 readl (ioaddr + FramesWDeferredXmt);
1033 readl (ioaddr + LateCollisions);
1034 readw (ioaddr + BcstFramesXmtdOk);
1035 readw (ioaddr + MacControlFramesXmtd);
1036 readw (ioaddr + FramesWEXDeferal);
1037
1038 #ifdef MEM_MAPPING
1039 for (i = 0x100; i <= 0x150; i += 4)
1040 readl (ioaddr + i);
1041 #endif
1042 readw (ioaddr + TxJumboFrames);
1043 readw (ioaddr + RxJumboFrames);
1044 readw (ioaddr + TCPCheckSumErrors);
1045 readw (ioaddr + UDPCheckSumErrors);
1046 readw (ioaddr + IPCheckSumErrors);
1047 return &np->stats;
1048 }
1049
1050 static int
1051 clear_stats (struct net_device *dev)
1052 {
1053 long ioaddr = dev->base_addr;
1054 #ifdef MEM_MAPPING
1055 int i;
1056 #endif
1057
1058 /* All statistics registers need to be acknowledged,
1059 else statistic overflow could cause problems */
1060 readl (ioaddr + FramesRcvOk);
1061 readl (ioaddr + FramesXmtOk);
1062 readl (ioaddr + OctetRcvOk);
1063 readl (ioaddr + OctetXmtOk);
1064
1065 readl (ioaddr + McstFramesRcvdOk);
1066 readl (ioaddr + SingleColFrames);
1067 readl (ioaddr + MultiColFrames);
1068 readl (ioaddr + LateCollisions);
1069 /* detailed rx errors */
1070 readw (ioaddr + FrameTooLongErrors);
1071 readw (ioaddr + InRangeLengthErrors);
1072 readw (ioaddr + FramesCheckSeqErrors);
1073 readw (ioaddr + FramesLostRxErrors);
1074
1075 /* detailed tx errors */
1076 readw (ioaddr + FramesAbortXSColls);
1077 readw (ioaddr + CarrierSenseErrors);
1078
1079 /* Clear all other statistic register. */
1080 readl (ioaddr + McstOctetXmtOk);
1081 readw (ioaddr + BcstFramesXmtdOk);
1082 readl (ioaddr + McstFramesXmtdOk);
1083 readw (ioaddr + BcstFramesRcvdOk);
1084 readw (ioaddr + MacControlFramesRcvd);
1085 readl (ioaddr + McstOctetXmtOk);
1086 readl (ioaddr + BcstOctetXmtOk);
1087 readl (ioaddr + McstFramesXmtdOk);
1088 readl (ioaddr + FramesWDeferredXmt);
1089 readw (ioaddr + BcstFramesXmtdOk);
1090 readw (ioaddr + MacControlFramesXmtd);
1091 readw (ioaddr + FramesWEXDeferal);
1092 #ifdef MEM_MAPPING
1093 for (i = 0x100; i <= 0x150; i += 4)
1094 readl (ioaddr + i);
1095 #endif
1096 readw (ioaddr + TxJumboFrames);
1097 readw (ioaddr + RxJumboFrames);
1098 readw (ioaddr + TCPCheckSumErrors);
1099 readw (ioaddr + UDPCheckSumErrors);
1100 readw (ioaddr + IPCheckSumErrors);
1101 return 0;
1102 }
1103
1104
1105 static int
1106 change_mtu (struct net_device *dev, int new_mtu)
1107 {
1108 struct netdev_private *np = netdev_priv(dev);
1109 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1110
1111 if ((new_mtu < 68) || (new_mtu > max)) {
1112 return -EINVAL;
1113 }
1114
1115 dev->mtu = new_mtu;
1116
1117 return 0;
1118 }
1119
1120 static void
1121 set_multicast (struct net_device *dev)
1122 {
1123 long ioaddr = dev->base_addr;
1124 u32 hash_table[2];
1125 u16 rx_mode = 0;
1126 struct netdev_private *np = netdev_priv(dev);
1127
1128 hash_table[0] = hash_table[1] = 0;
1129 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1130 hash_table[1] |= 0x02000000;
1131 if (dev->flags & IFF_PROMISC) {
1132 /* Receive all frames promiscuously. */
1133 rx_mode = ReceiveAllFrames;
1134 } else if ((dev->flags & IFF_ALLMULTI) ||
1135 (dev->mc_count > multicast_filter_limit)) {
1136 /* Receive broadcast and multicast frames */
1137 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1138 } else if (dev->mc_count > 0) {
1139 int i;
1140 struct dev_mc_list *mclist;
1141 /* Receive broadcast frames and multicast frames filtering
1142 by Hashtable */
1143 rx_mode =
1144 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1145 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1146 i++, mclist=mclist->next)
1147 {
1148 int bit, index = 0;
1149 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1150 /* The inverted high significant 6 bits of CRC are
1151 used as an index to hashtable */
1152 for (bit = 0; bit < 6; bit++)
1153 if (crc & (1 << (31 - bit)))
1154 index |= (1 << bit);
1155 hash_table[index / 32] |= (1 << (index % 32));
1156 }
1157 } else {
1158 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1159 }
1160 if (np->vlan) {
1161 /* ReceiveVLANMatch field in ReceiveMode */
1162 rx_mode |= ReceiveVLANMatch;
1163 }
1164
1165 writel (hash_table[0], ioaddr + HashTable0);
1166 writel (hash_table[1], ioaddr + HashTable1);
1167 writew (rx_mode, ioaddr + ReceiveMode);
1168 }
1169
1170 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1171 {
1172 struct netdev_private *np = netdev_priv(dev);
1173 strcpy(info->driver, "dl2k");
1174 strcpy(info->version, DRV_VERSION);
1175 strcpy(info->bus_info, pci_name(np->pdev));
1176 }
1177
1178 static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1179 {
1180 struct netdev_private *np = netdev_priv(dev);
1181 if (np->phy_media) {
1182 /* fiber device */
1183 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1184 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1185 cmd->port = PORT_FIBRE;
1186 cmd->transceiver = XCVR_INTERNAL;
1187 } else {
1188 /* copper device */
1189 cmd->supported = SUPPORTED_10baseT_Half |
1190 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1191 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1192 SUPPORTED_Autoneg | SUPPORTED_MII;
1193 cmd->advertising = ADVERTISED_10baseT_Half |
1194 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1195 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1196 ADVERTISED_Autoneg | ADVERTISED_MII;
1197 cmd->port = PORT_MII;
1198 cmd->transceiver = XCVR_INTERNAL;
1199 }
1200 if ( np->link_status ) {
1201 cmd->speed = np->speed;
1202 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1203 } else {
1204 cmd->speed = -1;
1205 cmd->duplex = -1;
1206 }
1207 if ( np->an_enable)
1208 cmd->autoneg = AUTONEG_ENABLE;
1209 else
1210 cmd->autoneg = AUTONEG_DISABLE;
1211
1212 cmd->phy_address = np->phy_addr;
1213 return 0;
1214 }
1215
1216 static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1217 {
1218 struct netdev_private *np = netdev_priv(dev);
1219 netif_carrier_off(dev);
1220 if (cmd->autoneg == AUTONEG_ENABLE) {
1221 if (np->an_enable)
1222 return 0;
1223 else {
1224 np->an_enable = 1;
1225 mii_set_media(dev);
1226 return 0;
1227 }
1228 } else {
1229 np->an_enable = 0;
1230 if (np->speed == 1000) {
1231 cmd->speed = SPEED_100;
1232 cmd->duplex = DUPLEX_FULL;
1233 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1234 }
1235 switch(cmd->speed + cmd->duplex) {
1236
1237 case SPEED_10 + DUPLEX_HALF:
1238 np->speed = 10;
1239 np->full_duplex = 0;
1240 break;
1241
1242 case SPEED_10 + DUPLEX_FULL:
1243 np->speed = 10;
1244 np->full_duplex = 1;
1245 break;
1246 case SPEED_100 + DUPLEX_HALF:
1247 np->speed = 100;
1248 np->full_duplex = 0;
1249 break;
1250 case SPEED_100 + DUPLEX_FULL:
1251 np->speed = 100;
1252 np->full_duplex = 1;
1253 break;
1254 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1255 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1256 default:
1257 return -EINVAL;
1258 }
1259 mii_set_media(dev);
1260 }
1261 return 0;
1262 }
1263
1264 static u32 rio_get_link(struct net_device *dev)
1265 {
1266 struct netdev_private *np = netdev_priv(dev);
1267 return np->link_status;
1268 }
1269
1270 static const struct ethtool_ops ethtool_ops = {
1271 .get_drvinfo = rio_get_drvinfo,
1272 .get_settings = rio_get_settings,
1273 .set_settings = rio_set_settings,
1274 .get_link = rio_get_link,
1275 };
1276
1277 static int
1278 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1279 {
1280 int phy_addr;
1281 struct netdev_private *np = netdev_priv(dev);
1282 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
1283
1284 struct netdev_desc *desc;
1285 int i;
1286
1287 phy_addr = np->phy_addr;
1288 switch (cmd) {
1289 case SIOCDEVPRIVATE:
1290 break;
1291
1292 case SIOCDEVPRIVATE + 1:
1293 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1294 break;
1295 case SIOCDEVPRIVATE + 2:
1296 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1297 break;
1298 case SIOCDEVPRIVATE + 3:
1299 break;
1300 case SIOCDEVPRIVATE + 4:
1301 break;
1302 case SIOCDEVPRIVATE + 5:
1303 netif_stop_queue (dev);
1304 break;
1305 case SIOCDEVPRIVATE + 6:
1306 netif_wake_queue (dev);
1307 break;
1308 case SIOCDEVPRIVATE + 7:
1309 printk
1310 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1311 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1312 np->old_rx);
1313 break;
1314 case SIOCDEVPRIVATE + 8:
1315 printk("TX ring:\n");
1316 for (i = 0; i < TX_RING_SIZE; i++) {
1317 desc = &np->tx_ring[i];
1318 printk
1319 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1320 i,
1321 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1322 (u32)le64_to_cpu(desc->next_desc),
1323 (u32)le64_to_cpu(desc->status),
1324 (u32)(le64_to_cpu(desc->fraginfo) >> 32),
1325 (u32)le64_to_cpu(desc->fraginfo));
1326 printk ("\n");
1327 }
1328 printk ("\n");
1329 break;
1330
1331 default:
1332 return -EOPNOTSUPP;
1333 }
1334 return 0;
1335 }
1336
1337 #define EEP_READ 0x0200
1338 #define EEP_BUSY 0x8000
1339 /* Read the EEPROM word */
1340 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1341 static int
1342 read_eeprom (long ioaddr, int eep_addr)
1343 {
1344 int i = 1000;
1345 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1346 while (i-- > 0) {
1347 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1348 return inw (ioaddr + EepromData);
1349 }
1350 }
1351 return 0;
1352 }
1353
1354 enum phy_ctrl_bits {
1355 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1356 MII_DUPLEX = 0x08,
1357 };
1358
1359 #define mii_delay() readb(ioaddr)
1360 static void
1361 mii_sendbit (struct net_device *dev, u32 data)
1362 {
1363 long ioaddr = dev->base_addr + PhyCtrl;
1364 data = (data) ? MII_DATA1 : 0;
1365 data |= MII_WRITE;
1366 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1367 writeb (data, ioaddr);
1368 mii_delay ();
1369 writeb (data | MII_CLK, ioaddr);
1370 mii_delay ();
1371 }
1372
1373 static int
1374 mii_getbit (struct net_device *dev)
1375 {
1376 long ioaddr = dev->base_addr + PhyCtrl;
1377 u8 data;
1378
1379 data = (readb (ioaddr) & 0xf8) | MII_READ;
1380 writeb (data, ioaddr);
1381 mii_delay ();
1382 writeb (data | MII_CLK, ioaddr);
1383 mii_delay ();
1384 return ((readb (ioaddr) >> 1) & 1);
1385 }
1386
1387 static void
1388 mii_send_bits (struct net_device *dev, u32 data, int len)
1389 {
1390 int i;
1391 for (i = len - 1; i >= 0; i--) {
1392 mii_sendbit (dev, data & (1 << i));
1393 }
1394 }
1395
1396 static int
1397 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1398 {
1399 u32 cmd;
1400 int i;
1401 u32 retval = 0;
1402
1403 /* Preamble */
1404 mii_send_bits (dev, 0xffffffff, 32);
1405 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1406 /* ST,OP = 0110'b for read operation */
1407 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1408 mii_send_bits (dev, cmd, 14);
1409 /* Turnaround */
1410 if (mii_getbit (dev))
1411 goto err_out;
1412 /* Read data */
1413 for (i = 0; i < 16; i++) {
1414 retval |= mii_getbit (dev);
1415 retval <<= 1;
1416 }
1417 /* End cycle */
1418 mii_getbit (dev);
1419 return (retval >> 1) & 0xffff;
1420
1421 err_out:
1422 return 0;
1423 }
1424 static int
1425 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1426 {
1427 u32 cmd;
1428
1429 /* Preamble */
1430 mii_send_bits (dev, 0xffffffff, 32);
1431 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1432 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1433 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1434 mii_send_bits (dev, cmd, 32);
1435 /* End cycle */
1436 mii_getbit (dev);
1437 return 0;
1438 }
1439 static int
1440 mii_wait_link (struct net_device *dev, int wait)
1441 {
1442 __u16 bmsr;
1443 int phy_addr;
1444 struct netdev_private *np;
1445
1446 np = netdev_priv(dev);
1447 phy_addr = np->phy_addr;
1448
1449 do {
1450 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1451 if (bmsr & MII_BMSR_LINK_STATUS)
1452 return 0;
1453 mdelay (1);
1454 } while (--wait > 0);
1455 return -1;
1456 }
1457 static int
1458 mii_get_media (struct net_device *dev)
1459 {
1460 __u16 negotiate;
1461 __u16 bmsr;
1462 __u16 mscr;
1463 __u16 mssr;
1464 int phy_addr;
1465 struct netdev_private *np;
1466
1467 np = netdev_priv(dev);
1468 phy_addr = np->phy_addr;
1469
1470 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1471 if (np->an_enable) {
1472 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1473 /* Auto-Negotiation not completed */
1474 return -1;
1475 }
1476 negotiate = mii_read (dev, phy_addr, MII_ANAR) &
1477 mii_read (dev, phy_addr, MII_ANLPAR);
1478 mscr = mii_read (dev, phy_addr, MII_MSCR);
1479 mssr = mii_read (dev, phy_addr, MII_MSSR);
1480 if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
1481 np->speed = 1000;
1482 np->full_duplex = 1;
1483 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1484 } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
1485 np->speed = 1000;
1486 np->full_duplex = 0;
1487 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1488 } else if (negotiate & MII_ANAR_100BX_FD) {
1489 np->speed = 100;
1490 np->full_duplex = 1;
1491 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1492 } else if (negotiate & MII_ANAR_100BX_HD) {
1493 np->speed = 100;
1494 np->full_duplex = 0;
1495 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1496 } else if (negotiate & MII_ANAR_10BT_FD) {
1497 np->speed = 10;
1498 np->full_duplex = 1;
1499 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1500 } else if (negotiate & MII_ANAR_10BT_HD) {
1501 np->speed = 10;
1502 np->full_duplex = 0;
1503 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1504 }
1505 if (negotiate & MII_ANAR_PAUSE) {
1506 np->tx_flow &= 1;
1507 np->rx_flow &= 1;
1508 } else if (negotiate & MII_ANAR_ASYMMETRIC) {
1509 np->tx_flow = 0;
1510 np->rx_flow &= 1;
1511 }
1512 /* else tx_flow, rx_flow = user select */
1513 } else {
1514 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1515 switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
1516 case MII_BMCR_SPEED_1000:
1517 printk (KERN_INFO "Operating at 1000 Mbps, ");
1518 break;
1519 case MII_BMCR_SPEED_100:
1520 printk (KERN_INFO "Operating at 100 Mbps, ");
1521 break;
1522 case 0:
1523 printk (KERN_INFO "Operating at 10 Mbps, ");
1524 }
1525 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1526 printk (KERN_CONT "Full duplex\n");
1527 } else {
1528 printk (KERN_CONT "Half duplex\n");
1529 }
1530 }
1531 if (np->tx_flow)
1532 printk(KERN_INFO "Enable Tx Flow Control\n");
1533 else
1534 printk(KERN_INFO "Disable Tx Flow Control\n");
1535 if (np->rx_flow)
1536 printk(KERN_INFO "Enable Rx Flow Control\n");
1537 else
1538 printk(KERN_INFO "Disable Rx Flow Control\n");
1539
1540 return 0;
1541 }
1542
1543 static int
1544 mii_set_media (struct net_device *dev)
1545 {
1546 __u16 pscr;
1547 __u16 bmcr;
1548 __u16 bmsr;
1549 __u16 anar;
1550 int phy_addr;
1551 struct netdev_private *np;
1552 np = netdev_priv(dev);
1553 phy_addr = np->phy_addr;
1554
1555 /* Does user set speed? */
1556 if (np->an_enable) {
1557 /* Advertise capabilities */
1558 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1559 anar = mii_read (dev, phy_addr, MII_ANAR) &
1560 ~MII_ANAR_100BX_FD &
1561 ~MII_ANAR_100BX_HD &
1562 ~MII_ANAR_100BT4 &
1563 ~MII_ANAR_10BT_FD &
1564 ~MII_ANAR_10BT_HD;
1565 if (bmsr & MII_BMSR_100BX_FD)
1566 anar |= MII_ANAR_100BX_FD;
1567 if (bmsr & MII_BMSR_100BX_HD)
1568 anar |= MII_ANAR_100BX_HD;
1569 if (bmsr & MII_BMSR_100BT4)
1570 anar |= MII_ANAR_100BT4;
1571 if (bmsr & MII_BMSR_10BT_FD)
1572 anar |= MII_ANAR_10BT_FD;
1573 if (bmsr & MII_BMSR_10BT_HD)
1574 anar |= MII_ANAR_10BT_HD;
1575 anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
1576 mii_write (dev, phy_addr, MII_ANAR, anar);
1577
1578 /* Enable Auto crossover */
1579 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1580 pscr |= 3 << 5; /* 11'b */
1581 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1582
1583 /* Soft reset PHY */
1584 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1585 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
1586 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1587 mdelay(1);
1588 } else {
1589 /* Force speed setting */
1590 /* 1) Disable Auto crossover */
1591 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1592 pscr &= ~(3 << 5);
1593 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1594
1595 /* 2) PHY Reset */
1596 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1597 bmcr |= MII_BMCR_RESET;
1598 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1599
1600 /* 3) Power Down */
1601 bmcr = 0x1940; /* must be 0x1940 */
1602 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1603 mdelay (100); /* wait a certain time */
1604
1605 /* 4) Advertise nothing */
1606 mii_write (dev, phy_addr, MII_ANAR, 0);
1607
1608 /* 5) Set media and Power Up */
1609 bmcr = MII_BMCR_POWER_DOWN;
1610 if (np->speed == 100) {
1611 bmcr |= MII_BMCR_SPEED_100;
1612 printk (KERN_INFO "Manual 100 Mbps, ");
1613 } else if (np->speed == 10) {
1614 printk (KERN_INFO "Manual 10 Mbps, ");
1615 }
1616 if (np->full_duplex) {
1617 bmcr |= MII_BMCR_DUPLEX_MODE;
1618 printk (KERN_CONT "Full duplex\n");
1619 } else {
1620 printk (KERN_CONT "Half duplex\n");
1621 }
1622 #if 0
1623 /* Set 1000BaseT Master/Slave setting */
1624 mscr = mii_read (dev, phy_addr, MII_MSCR);
1625 mscr |= MII_MSCR_CFG_ENABLE;
1626 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1627 #endif
1628 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1629 mdelay(10);
1630 }
1631 return 0;
1632 }
1633
1634 static int
1635 mii_get_media_pcs (struct net_device *dev)
1636 {
1637 __u16 negotiate;
1638 __u16 bmsr;
1639 int phy_addr;
1640 struct netdev_private *np;
1641
1642 np = netdev_priv(dev);
1643 phy_addr = np->phy_addr;
1644
1645 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1646 if (np->an_enable) {
1647 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1648 /* Auto-Negotiation not completed */
1649 return -1;
1650 }
1651 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1652 mii_read (dev, phy_addr, PCS_ANLPAR);
1653 np->speed = 1000;
1654 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1655 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1656 np->full_duplex = 1;
1657 } else {
1658 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1659 np->full_duplex = 0;
1660 }
1661 if (negotiate & PCS_ANAR_PAUSE) {
1662 np->tx_flow &= 1;
1663 np->rx_flow &= 1;
1664 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1665 np->tx_flow = 0;
1666 np->rx_flow &= 1;
1667 }
1668 /* else tx_flow, rx_flow = user select */
1669 } else {
1670 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1671 printk (KERN_INFO "Operating at 1000 Mbps, ");
1672 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1673 printk (KERN_CONT "Full duplex\n");
1674 } else {
1675 printk (KERN_CONT "Half duplex\n");
1676 }
1677 }
1678 if (np->tx_flow)
1679 printk(KERN_INFO "Enable Tx Flow Control\n");
1680 else
1681 printk(KERN_INFO "Disable Tx Flow Control\n");
1682 if (np->rx_flow)
1683 printk(KERN_INFO "Enable Rx Flow Control\n");
1684 else
1685 printk(KERN_INFO "Disable Rx Flow Control\n");
1686
1687 return 0;
1688 }
1689
1690 static int
1691 mii_set_media_pcs (struct net_device *dev)
1692 {
1693 __u16 bmcr;
1694 __u16 esr;
1695 __u16 anar;
1696 int phy_addr;
1697 struct netdev_private *np;
1698 np = netdev_priv(dev);
1699 phy_addr = np->phy_addr;
1700
1701 /* Auto-Negotiation? */
1702 if (np->an_enable) {
1703 /* Advertise capabilities */
1704 esr = mii_read (dev, phy_addr, PCS_ESR);
1705 anar = mii_read (dev, phy_addr, MII_ANAR) &
1706 ~PCS_ANAR_HALF_DUPLEX &
1707 ~PCS_ANAR_FULL_DUPLEX;
1708 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1709 anar |= PCS_ANAR_HALF_DUPLEX;
1710 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1711 anar |= PCS_ANAR_FULL_DUPLEX;
1712 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1713 mii_write (dev, phy_addr, MII_ANAR, anar);
1714
1715 /* Soft reset PHY */
1716 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1717 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
1718 MII_BMCR_RESET;
1719 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1720 mdelay(1);
1721 } else {
1722 /* Force speed setting */
1723 /* PHY Reset */
1724 bmcr = MII_BMCR_RESET;
1725 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1726 mdelay(10);
1727 if (np->full_duplex) {
1728 bmcr = MII_BMCR_DUPLEX_MODE;
1729 printk (KERN_INFO "Manual full duplex\n");
1730 } else {
1731 bmcr = 0;
1732 printk (KERN_INFO "Manual half duplex\n");
1733 }
1734 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1735 mdelay(10);
1736
1737 /* Advertise nothing */
1738 mii_write (dev, phy_addr, MII_ANAR, 0);
1739 }
1740 return 0;
1741 }
1742
1743
1744 static int
1745 rio_close (struct net_device *dev)
1746 {
1747 long ioaddr = dev->base_addr;
1748 struct netdev_private *np = netdev_priv(dev);
1749 struct sk_buff *skb;
1750 int i;
1751
1752 netif_stop_queue (dev);
1753
1754 /* Disable interrupts */
1755 writew (0, ioaddr + IntEnable);
1756
1757 /* Stop Tx and Rx logics */
1758 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1759
1760 free_irq (dev->irq, dev);
1761 del_timer_sync (&np->timer);
1762
1763 /* Free all the skbuffs in the queue. */
1764 for (i = 0; i < RX_RING_SIZE; i++) {
1765 np->rx_ring[i].status = 0;
1766 np->rx_ring[i].fraginfo = 0;
1767 skb = np->rx_skbuff[i];
1768 if (skb) {
1769 pci_unmap_single(np->pdev,
1770 desc_to_dma(&np->rx_ring[i]),
1771 skb->len, PCI_DMA_FROMDEVICE);
1772 dev_kfree_skb (skb);
1773 np->rx_skbuff[i] = NULL;
1774 }
1775 }
1776 for (i = 0; i < TX_RING_SIZE; i++) {
1777 skb = np->tx_skbuff[i];
1778 if (skb) {
1779 pci_unmap_single(np->pdev,
1780 desc_to_dma(&np->tx_ring[i]),
1781 skb->len, PCI_DMA_TODEVICE);
1782 dev_kfree_skb (skb);
1783 np->tx_skbuff[i] = NULL;
1784 }
1785 }
1786
1787 return 0;
1788 }
1789
1790 static void __devexit
1791 rio_remove1 (struct pci_dev *pdev)
1792 {
1793 struct net_device *dev = pci_get_drvdata (pdev);
1794
1795 if (dev) {
1796 struct netdev_private *np = netdev_priv(dev);
1797
1798 unregister_netdev (dev);
1799 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1800 np->rx_ring_dma);
1801 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1802 np->tx_ring_dma);
1803 #ifdef MEM_MAPPING
1804 iounmap ((char *) (dev->base_addr));
1805 #endif
1806 free_netdev (dev);
1807 pci_release_regions (pdev);
1808 pci_disable_device (pdev);
1809 }
1810 pci_set_drvdata (pdev, NULL);
1811 }
1812
1813 static struct pci_driver rio_driver = {
1814 .name = "dl2k",
1815 .id_table = rio_pci_tbl,
1816 .probe = rio_probe1,
1817 .remove = __devexit_p(rio_remove1),
1818 };
1819
1820 static int __init
1821 rio_init (void)
1822 {
1823 return pci_register_driver(&rio_driver);
1824 }
1825
1826 static void __exit
1827 rio_exit (void)
1828 {
1829 pci_unregister_driver (&rio_driver);
1830 }
1831
1832 module_init (rio_init);
1833 module_exit (rio_exit);
1834
1835 /*
1836
1837 Compile command:
1838
1839 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1840
1841 Read Documentation/networking/dl2k.txt for details.
1842
1843 */
1844
Linux for Ginger Game Console