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OMAP3: PM: decouple PER and CORE context save and restore
[linux-ginger.git] / drivers / net / qlge / qlge.h
blobe7285f01bd04ef3bda4b6d37f5d0cbc9b2b92c92
1 /*
2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qlge for copyright and licensing details.
6 */
7 #ifndef _QLGE_H_
8 #define _QLGE_H_
9
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
12 #include <linux/rtnetlink.h>
13
14 /*
15 * General definitions...
16 */
17 #define DRV_NAME "qlge"
18 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
19 #define DRV_VERSION "v1.00.00-b3"
20
21 #define PFX "qlge: "
22 #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
23 do { \
24 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
25 ; \
26 else \
27 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
28 "%s: " fmt, __func__, ##args); \
29 } while (0)
30
31 #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
32
33 #define QLGE_VENDOR_ID 0x1077
34 #define QLGE_DEVICE_ID_8012 0x8012
35 #define QLGE_DEVICE_ID_8000 0x8000
36 #define MAX_CPUS 8
37 #define MAX_TX_RINGS MAX_CPUS
38 #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
39
40 #define NUM_TX_RING_ENTRIES 256
41 #define NUM_RX_RING_ENTRIES 256
42
43 #define NUM_SMALL_BUFFERS 512
44 #define NUM_LARGE_BUFFERS 512
45 #define DB_PAGE_SIZE 4096
46
47 /* Calculate the number of (4k) pages required to
48 * contain a buffer queue of the given length.
49 */
50 #define MAX_DB_PAGES_PER_BQ(x) \
51 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
52 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
53
54 #define RX_RING_SHADOW_SPACE (sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
56 MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))
57 #define SMALL_BUFFER_SIZE 256
58 #define LARGE_BUFFER_SIZE PAGE_SIZE
59 #define MAX_SPLIT_SIZE 1023
60 #define QLGE_SB_PAD 32
61
62 #define MAX_CQ 128
63 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
64 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
65 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
66 #define UDELAY_COUNT 3
67 #define UDELAY_DELAY 100
68
69
70 #define TX_DESC_PER_IOCB 8
71 /* The maximum number of frags we handle is based
72 * on PAGE_SIZE...
73 */
74 #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
75 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
76 #else /* all other page sizes */
77 #define TX_DESC_PER_OAL 0
78 #endif
79
80 /* MPI test register definitions. This register
81 * is used for determining alternate NIC function's
82 * PCI->func number.
83 */
84 enum {
85 MPI_TEST_FUNC_PORT_CFG = 0x1002,
86 MPI_TEST_NIC1_FUNC_SHIFT = 1,
87 MPI_TEST_NIC2_FUNC_SHIFT = 5,
88 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
89 };
90
91 /*
92 * Processor Address Register (PROC_ADDR) bit definitions.
93 */
94 enum {
95
96 /* Misc. stuff */
97 MAILBOX_COUNT = 16,
98
99 PROC_ADDR_RDY = (1 << 31),
100 PROC_ADDR_R = (1 << 30),
101 PROC_ADDR_ERR = (1 << 29),
102 PROC_ADDR_DA = (1 << 28),
103 PROC_ADDR_FUNC0_MBI = 0x00001180,
104 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
105 PROC_ADDR_FUNC0_CTL = 0x000011a1,
106 PROC_ADDR_FUNC2_MBI = 0x00001280,
107 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
108 PROC_ADDR_FUNC2_CTL = 0x000012a1,
109 PROC_ADDR_MPI_RISC = 0x00000000,
110 PROC_ADDR_MDE = 0x00010000,
111 PROC_ADDR_REGBLOCK = 0x00020000,
112 PROC_ADDR_RISC_REG = 0x00030000,
113 };
114
115 /*
116 * System Register (SYS) bit definitions.
117 */
118 enum {
119 SYS_EFE = (1 << 0),
120 SYS_FAE = (1 << 1),
121 SYS_MDC = (1 << 2),
122 SYS_DST = (1 << 3),
123 SYS_DWC = (1 << 4),
124 SYS_EVW = (1 << 5),
125 SYS_OMP_DLY_MASK = 0x3f000000,
126 /*
127 * There are no values defined as of edit #15.
128 */
129 SYS_ODI = (1 << 14),
130 };
131
132 /*
133 * Reset/Failover Register (RST_FO) bit definitions.
134 */
135 enum {
136 RST_FO_TFO = (1 << 0),
137 RST_FO_RR_MASK = 0x00060000,
138 RST_FO_RR_CQ_CAM = 0x00000000,
139 RST_FO_RR_DROP = 0x00000002,
140 RST_FO_RR_DQ = 0x00000004,
141 RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
142 RST_FO_FRB = (1 << 12),
143 RST_FO_MOP = (1 << 13),
144 RST_FO_REG = (1 << 14),
145 RST_FO_FR = (1 << 15),
146 };
147
148 /*
149 * Function Specific Control Register (FSC) bit definitions.
150 */
151 enum {
152 FSC_DBRST_MASK = 0x00070000,
153 FSC_DBRST_256 = 0x00000000,
154 FSC_DBRST_512 = 0x00000001,
155 FSC_DBRST_768 = 0x00000002,
156 FSC_DBRST_1024 = 0x00000003,
157 FSC_DBL_MASK = 0x00180000,
158 FSC_DBL_DBRST = 0x00000000,
159 FSC_DBL_MAX_PLD = 0x00000008,
160 FSC_DBL_MAX_BRST = 0x00000010,
161 FSC_DBL_128_BYTES = 0x00000018,
162 FSC_EC = (1 << 5),
163 FSC_EPC_MASK = 0x00c00000,
164 FSC_EPC_INBOUND = (1 << 6),
165 FSC_EPC_OUTBOUND = (1 << 7),
166 FSC_VM_PAGESIZE_MASK = 0x07000000,
167 FSC_VM_PAGE_2K = 0x00000100,
168 FSC_VM_PAGE_4K = 0x00000200,
169 FSC_VM_PAGE_8K = 0x00000300,
170 FSC_VM_PAGE_64K = 0x00000600,
171 FSC_SH = (1 << 11),
172 FSC_DSB = (1 << 12),
173 FSC_STE = (1 << 13),
174 FSC_FE = (1 << 15),
175 };
176
177 /*
178 * Host Command Status Register (CSR) bit definitions.
179 */
180 enum {
181 CSR_ERR_STS_MASK = 0x0000003f,
182 /*
183 * There are no valued defined as of edit #15.
184 */
185 CSR_RR = (1 << 8),
186 CSR_HRI = (1 << 9),
187 CSR_RP = (1 << 10),
188 CSR_CMD_PARM_SHIFT = 22,
189 CSR_CMD_NOP = 0x00000000,
190 CSR_CMD_SET_RST = 0x10000000,
191 CSR_CMD_CLR_RST = 0x20000000,
192 CSR_CMD_SET_PAUSE = 0x30000000,
193 CSR_CMD_CLR_PAUSE = 0x40000000,
194 CSR_CMD_SET_H2R_INT = 0x50000000,
195 CSR_CMD_CLR_H2R_INT = 0x60000000,
196 CSR_CMD_PAR_EN = 0x70000000,
197 CSR_CMD_SET_BAD_PAR = 0x80000000,
198 CSR_CMD_CLR_BAD_PAR = 0x90000000,
199 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
200 };
201
202 /*
203 * Configuration Register (CFG) bit definitions.
204 */
205 enum {
206 CFG_LRQ = (1 << 0),
207 CFG_DRQ = (1 << 1),
208 CFG_LR = (1 << 2),
209 CFG_DR = (1 << 3),
210 CFG_LE = (1 << 5),
211 CFG_LCQ = (1 << 6),
212 CFG_DCQ = (1 << 7),
213 CFG_Q_SHIFT = 8,
214 CFG_Q_MASK = 0x7f000000,
215 };
216
217 /*
218 * Status Register (STS) bit definitions.
219 */
220 enum {
221 STS_FE = (1 << 0),
222 STS_PI = (1 << 1),
223 STS_PL0 = (1 << 2),
224 STS_PL1 = (1 << 3),
225 STS_PI0 = (1 << 4),
226 STS_PI1 = (1 << 5),
227 STS_FUNC_ID_MASK = 0x000000c0,
228 STS_FUNC_ID_SHIFT = 6,
229 STS_F0E = (1 << 8),
230 STS_F1E = (1 << 9),
231 STS_F2E = (1 << 10),
232 STS_F3E = (1 << 11),
233 STS_NFE = (1 << 12),
234 };
235
236 /*
237 * Interrupt Enable Register (INTR_EN) bit definitions.
238 */
239 enum {
240 INTR_EN_INTR_MASK = 0x007f0000,
241 INTR_EN_TYPE_MASK = 0x03000000,
242 INTR_EN_TYPE_ENABLE = 0x00000100,
243 INTR_EN_TYPE_DISABLE = 0x00000200,
244 INTR_EN_TYPE_READ = 0x00000300,
245 INTR_EN_IHD = (1 << 13),
246 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
247 INTR_EN_EI = (1 << 14),
248 INTR_EN_EN = (1 << 15),
249 };
250
251 /*
252 * Interrupt Mask Register (INTR_MASK) bit definitions.
253 */
254 enum {
255 INTR_MASK_PI = (1 << 0),
256 INTR_MASK_HL0 = (1 << 1),
257 INTR_MASK_LH0 = (1 << 2),
258 INTR_MASK_HL1 = (1 << 3),
259 INTR_MASK_LH1 = (1 << 4),
260 INTR_MASK_SE = (1 << 5),
261 INTR_MASK_LSC = (1 << 6),
262 INTR_MASK_MC = (1 << 7),
263 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
264 };
265
266 /*
267 * Register (REV_ID) bit definitions.
268 */
269 enum {
270 REV_ID_MASK = 0x0000000f,
271 REV_ID_NICROLL_SHIFT = 0,
272 REV_ID_NICREV_SHIFT = 4,
273 REV_ID_XGROLL_SHIFT = 8,
274 REV_ID_XGREV_SHIFT = 12,
275 REV_ID_CHIPREV_SHIFT = 28,
276 };
277
278 /*
279 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
280 */
281 enum {
282 FRC_ECC_ERR_VW = (1 << 12),
283 FRC_ECC_ERR_VB = (1 << 13),
284 FRC_ECC_ERR_NI = (1 << 14),
285 FRC_ECC_ERR_NO = (1 << 15),
286 FRC_ECC_PFE_SHIFT = 16,
287 FRC_ECC_ERR_DO = (1 << 18),
288 FRC_ECC_P14 = (1 << 19),
289 };
290
291 /*
292 * Error Status Register (ERR_STS) bit definitions.
293 */
294 enum {
295 ERR_STS_NOF = (1 << 0),
296 ERR_STS_NIF = (1 << 1),
297 ERR_STS_DRP = (1 << 2),
298 ERR_STS_XGP = (1 << 3),
299 ERR_STS_FOU = (1 << 4),
300 ERR_STS_FOC = (1 << 5),
301 ERR_STS_FOF = (1 << 6),
302 ERR_STS_FIU = (1 << 7),
303 ERR_STS_FIC = (1 << 8),
304 ERR_STS_FIF = (1 << 9),
305 ERR_STS_MOF = (1 << 10),
306 ERR_STS_TA = (1 << 11),
307 ERR_STS_MA = (1 << 12),
308 ERR_STS_MPE = (1 << 13),
309 ERR_STS_SCE = (1 << 14),
310 ERR_STS_STE = (1 << 15),
311 ERR_STS_FOW = (1 << 16),
312 ERR_STS_UE = (1 << 17),
313 ERR_STS_MCH = (1 << 26),
314 ERR_STS_LOC_SHIFT = 27,
315 };
316
317 /*
318 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
319 */
320 enum {
321 RAM_DBG_ADDR_FW = (1 << 30),
322 RAM_DBG_ADDR_FR = (1 << 31),
323 };
324
325 /*
326 * Semaphore Register (SEM) bit definitions.
327 */
328 enum {
329 /*
330 * Example:
331 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
332 */
333 SEM_CLEAR = 0,
334 SEM_SET = 1,
335 SEM_FORCE = 3,
336 SEM_XGMAC0_SHIFT = 0,
337 SEM_XGMAC1_SHIFT = 2,
338 SEM_ICB_SHIFT = 4,
339 SEM_MAC_ADDR_SHIFT = 6,
340 SEM_FLASH_SHIFT = 8,
341 SEM_PROBE_SHIFT = 10,
342 SEM_RT_IDX_SHIFT = 12,
343 SEM_PROC_REG_SHIFT = 14,
344 SEM_XGMAC0_MASK = 0x00030000,
345 SEM_XGMAC1_MASK = 0x000c0000,
346 SEM_ICB_MASK = 0x00300000,
347 SEM_MAC_ADDR_MASK = 0x00c00000,
348 SEM_FLASH_MASK = 0x03000000,
349 SEM_PROBE_MASK = 0x0c000000,
350 SEM_RT_IDX_MASK = 0x30000000,
351 SEM_PROC_REG_MASK = 0xc0000000,
352 };
353
354 /*
355 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
356 */
357 enum {
358 XGMAC_ADDR_RDY = (1 << 31),
359 XGMAC_ADDR_R = (1 << 30),
360 XGMAC_ADDR_XME = (1 << 29),
361
362 /* XGMAC control registers */
363 PAUSE_SRC_LO = 0x00000100,
364 PAUSE_SRC_HI = 0x00000104,
365 GLOBAL_CFG = 0x00000108,
366 GLOBAL_CFG_RESET = (1 << 0),
367 GLOBAL_CFG_JUMBO = (1 << 6),
368 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
369 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
370 TX_CFG = 0x0000010c,
371 TX_CFG_RESET = (1 << 0),
372 TX_CFG_EN = (1 << 1),
373 TX_CFG_PREAM = (1 << 2),
374 RX_CFG = 0x00000110,
375 RX_CFG_RESET = (1 << 0),
376 RX_CFG_EN = (1 << 1),
377 RX_CFG_PREAM = (1 << 2),
378 FLOW_CTL = 0x0000011c,
379 PAUSE_OPCODE = 0x00000120,
380 PAUSE_TIMER = 0x00000124,
381 PAUSE_FRM_DEST_LO = 0x00000128,
382 PAUSE_FRM_DEST_HI = 0x0000012c,
383 MAC_TX_PARAMS = 0x00000134,
384 MAC_TX_PARAMS_JUMBO = (1 << 31),
385 MAC_TX_PARAMS_SIZE_SHIFT = 16,
386 MAC_RX_PARAMS = 0x00000138,
387 MAC_SYS_INT = 0x00000144,
388 MAC_SYS_INT_MASK = 0x00000148,
389 MAC_MGMT_INT = 0x0000014c,
390 MAC_MGMT_IN_MASK = 0x00000150,
391 EXT_ARB_MODE = 0x000001fc,
392
393 /* XGMAC TX statistics registers */
394 TX_PKTS = 0x00000200,
395 TX_BYTES = 0x00000208,
396 TX_MCAST_PKTS = 0x00000210,
397 TX_BCAST_PKTS = 0x00000218,
398 TX_UCAST_PKTS = 0x00000220,
399 TX_CTL_PKTS = 0x00000228,
400 TX_PAUSE_PKTS = 0x00000230,
401 TX_64_PKT = 0x00000238,
402 TX_65_TO_127_PKT = 0x00000240,
403 TX_128_TO_255_PKT = 0x00000248,
404 TX_256_511_PKT = 0x00000250,
405 TX_512_TO_1023_PKT = 0x00000258,
406 TX_1024_TO_1518_PKT = 0x00000260,
407 TX_1519_TO_MAX_PKT = 0x00000268,
408 TX_UNDERSIZE_PKT = 0x00000270,
409 TX_OVERSIZE_PKT = 0x00000278,
410
411 /* XGMAC statistics control registers */
412 RX_HALF_FULL_DET = 0x000002a0,
413 TX_HALF_FULL_DET = 0x000002a4,
414 RX_OVERFLOW_DET = 0x000002a8,
415 TX_OVERFLOW_DET = 0x000002ac,
416 RX_HALF_FULL_MASK = 0x000002b0,
417 TX_HALF_FULL_MASK = 0x000002b4,
418 RX_OVERFLOW_MASK = 0x000002b8,
419 TX_OVERFLOW_MASK = 0x000002bc,
420 STAT_CNT_CTL = 0x000002c0,
421 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
422 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
423 AUX_RX_HALF_FULL_DET = 0x000002d0,
424 AUX_TX_HALF_FULL_DET = 0x000002d4,
425 AUX_RX_OVERFLOW_DET = 0x000002d8,
426 AUX_TX_OVERFLOW_DET = 0x000002dc,
427 AUX_RX_HALF_FULL_MASK = 0x000002f0,
428 AUX_TX_HALF_FULL_MASK = 0x000002f4,
429 AUX_RX_OVERFLOW_MASK = 0x000002f8,
430 AUX_TX_OVERFLOW_MASK = 0x000002fc,
431
432 /* XGMAC RX statistics registers */
433 RX_BYTES = 0x00000300,
434 RX_BYTES_OK = 0x00000308,
435 RX_PKTS = 0x00000310,
436 RX_PKTS_OK = 0x00000318,
437 RX_BCAST_PKTS = 0x00000320,
438 RX_MCAST_PKTS = 0x00000328,
439 RX_UCAST_PKTS = 0x00000330,
440 RX_UNDERSIZE_PKTS = 0x00000338,
441 RX_OVERSIZE_PKTS = 0x00000340,
442 RX_JABBER_PKTS = 0x00000348,
443 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
444 RX_DROP_EVENTS = 0x00000358,
445 RX_FCERR_PKTS = 0x00000360,
446 RX_ALIGN_ERR = 0x00000368,
447 RX_SYMBOL_ERR = 0x00000370,
448 RX_MAC_ERR = 0x00000378,
449 RX_CTL_PKTS = 0x00000380,
450 RX_PAUSE_PKTS = 0x00000388,
451 RX_64_PKTS = 0x00000390,
452 RX_65_TO_127_PKTS = 0x00000398,
453 RX_128_255_PKTS = 0x000003a0,
454 RX_256_511_PKTS = 0x000003a8,
455 RX_512_TO_1023_PKTS = 0x000003b0,
456 RX_1024_TO_1518_PKTS = 0x000003b8,
457 RX_1519_TO_MAX_PKTS = 0x000003c0,
458 RX_LEN_ERR_PKTS = 0x000003c8,
459
460 /* XGMAC MDIO control registers */
461 MDIO_TX_DATA = 0x00000400,
462 MDIO_RX_DATA = 0x00000410,
463 MDIO_CMD = 0x00000420,
464 MDIO_PHY_ADDR = 0x00000430,
465 MDIO_PORT = 0x00000440,
466 MDIO_STATUS = 0x00000450,
467
468 /* XGMAC AUX statistics registers */
469 };
470
471 /*
472 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
473 */
474 enum {
475 ETS_QUEUE_SHIFT = 29,
476 ETS_REF = (1 << 26),
477 ETS_RS = (1 << 27),
478 ETS_P = (1 << 28),
479 ETS_FC_COS_SHIFT = 23,
480 };
481
482 /*
483 * Flash Address Register (FLASH_ADDR) bit definitions.
484 */
485 enum {
486 FLASH_ADDR_RDY = (1 << 31),
487 FLASH_ADDR_R = (1 << 30),
488 FLASH_ADDR_ERR = (1 << 29),
489 };
490
491 /*
492 * Stop CQ Processing Register (CQ_STOP) bit definitions.
493 */
494 enum {
495 CQ_STOP_QUEUE_MASK = (0x007f0000),
496 CQ_STOP_TYPE_MASK = (0x03000000),
497 CQ_STOP_TYPE_START = 0x00000100,
498 CQ_STOP_TYPE_STOP = 0x00000200,
499 CQ_STOP_TYPE_READ = 0x00000300,
500 CQ_STOP_EN = (1 << 15),
501 };
502
503 /*
504 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
505 */
506 enum {
507 MAC_ADDR_IDX_SHIFT = 4,
508 MAC_ADDR_TYPE_SHIFT = 16,
509 MAC_ADDR_TYPE_MASK = 0x000f0000,
510 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
511 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
512 MAC_ADDR_TYPE_VLAN = 0x00020000,
513 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
514 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
515 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
516 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
517 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
518 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
519 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
520 MAC_ADDR_ADR = (1 << 25),
521 MAC_ADDR_RS = (1 << 26),
522 MAC_ADDR_E = (1 << 27),
523 MAC_ADDR_MR = (1 << 30),
524 MAC_ADDR_MW = (1 << 31),
525 MAX_MULTICAST_ENTRIES = 32,
526 };
527
528 /*
529 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
530 */
531 enum {
532 SPLT_HDR_EP = (1 << 31),
533 };
534
535 /*
536 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
537 */
538 enum {
539 FC_RCV_CFG_ECT = (1 << 15),
540 FC_RCV_CFG_DFH = (1 << 20),
541 FC_RCV_CFG_DVF = (1 << 21),
542 FC_RCV_CFG_RCE = (1 << 27),
543 FC_RCV_CFG_RFE = (1 << 28),
544 FC_RCV_CFG_TEE = (1 << 29),
545 FC_RCV_CFG_TCE = (1 << 30),
546 FC_RCV_CFG_TFE = (1 << 31),
547 };
548
549 /*
550 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
551 */
552 enum {
553 NIC_RCV_CFG_PPE = (1 << 0),
554 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
555 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
556 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
557 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
558 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
559 NIC_RCV_CFG_RV = (1 << 3),
560 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
561 NIC_RCV_CFG_DFQ_SHIFT = 8,
562 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
563 };
564
565 /*
566 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
567 */
568 enum {
569 MGMT_RCV_CFG_ARP = (1 << 0),
570 MGMT_RCV_CFG_DHC = (1 << 1),
571 MGMT_RCV_CFG_DHS = (1 << 2),
572 MGMT_RCV_CFG_NP = (1 << 3),
573 MGMT_RCV_CFG_I6N = (1 << 4),
574 MGMT_RCV_CFG_I6R = (1 << 5),
575 MGMT_RCV_CFG_DH6 = (1 << 6),
576 MGMT_RCV_CFG_UD1 = (1 << 7),
577 MGMT_RCV_CFG_UD0 = (1 << 8),
578 MGMT_RCV_CFG_BCT = (1 << 9),
579 MGMT_RCV_CFG_MCT = (1 << 10),
580 MGMT_RCV_CFG_DM = (1 << 11),
581 MGMT_RCV_CFG_RM = (1 << 12),
582 MGMT_RCV_CFG_STL = (1 << 13),
583 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
584 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
585 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
586 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
587 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
588 };
589
590 /*
591 * Routing Index Register (RT_IDX) bit definitions.
592 */
593 enum {
594 RT_IDX_IDX_SHIFT = 8,
595 RT_IDX_TYPE_MASK = 0x000f0000,
596 RT_IDX_TYPE_RT = 0x00000000,
597 RT_IDX_TYPE_RT_INV = 0x00010000,
598 RT_IDX_TYPE_NICQ = 0x00020000,
599 RT_IDX_TYPE_NICQ_INV = 0x00030000,
600 RT_IDX_DST_MASK = 0x00700000,
601 RT_IDX_DST_RSS = 0x00000000,
602 RT_IDX_DST_CAM_Q = 0x00100000,
603 RT_IDX_DST_COS_Q = 0x00200000,
604 RT_IDX_DST_DFLT_Q = 0x00300000,
605 RT_IDX_DST_DEST_Q = 0x00400000,
606 RT_IDX_RS = (1 << 26),
607 RT_IDX_E = (1 << 27),
608 RT_IDX_MR = (1 << 30),
609 RT_IDX_MW = (1 << 31),
610
611 /* Nic Queue format - type 2 bits */
612 RT_IDX_BCAST = (1 << 0),
613 RT_IDX_MCAST = (1 << 1),
614 RT_IDX_MCAST_MATCH = (1 << 2),
615 RT_IDX_MCAST_REG_MATCH = (1 << 3),
616 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
617 RT_IDX_FC_MACH = (1 << 5),
618 RT_IDX_ETH_FCOE = (1 << 6),
619 RT_IDX_CAM_HIT = (1 << 7),
620 RT_IDX_CAM_BIT0 = (1 << 8),
621 RT_IDX_CAM_BIT1 = (1 << 9),
622 RT_IDX_VLAN_TAG = (1 << 10),
623 RT_IDX_VLAN_MATCH = (1 << 11),
624 RT_IDX_VLAN_FILTER = (1 << 12),
625 RT_IDX_ETH_SKIP1 = (1 << 13),
626 RT_IDX_ETH_SKIP2 = (1 << 14),
627 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
628 RT_IDX_802_3 = (1 << 16),
629 RT_IDX_LLDP = (1 << 17),
630 RT_IDX_UNUSED018 = (1 << 18),
631 RT_IDX_UNUSED019 = (1 << 19),
632 RT_IDX_UNUSED20 = (1 << 20),
633 RT_IDX_UNUSED21 = (1 << 21),
634 RT_IDX_ERR = (1 << 22),
635 RT_IDX_VALID = (1 << 23),
636 RT_IDX_TU_CSUM_ERR = (1 << 24),
637 RT_IDX_IP_CSUM_ERR = (1 << 25),
638 RT_IDX_MAC_ERR = (1 << 26),
639 RT_IDX_RSS_TCP6 = (1 << 27),
640 RT_IDX_RSS_TCP4 = (1 << 28),
641 RT_IDX_RSS_IPV6 = (1 << 29),
642 RT_IDX_RSS_IPV4 = (1 << 30),
643 RT_IDX_RSS_MATCH = (1 << 31),
644
645 /* Hierarchy for the NIC Queue Mask */
646 RT_IDX_ALL_ERR_SLOT = 0,
647 RT_IDX_MAC_ERR_SLOT = 0,
648 RT_IDX_IP_CSUM_ERR_SLOT = 1,
649 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
650 RT_IDX_BCAST_SLOT = 3,
651 RT_IDX_MCAST_MATCH_SLOT = 4,
652 RT_IDX_ALLMULTI_SLOT = 5,
653 RT_IDX_UNUSED6_SLOT = 6,
654 RT_IDX_UNUSED7_SLOT = 7,
655 RT_IDX_RSS_MATCH_SLOT = 8,
656 RT_IDX_RSS_IPV4_SLOT = 8,
657 RT_IDX_RSS_IPV6_SLOT = 9,
658 RT_IDX_RSS_TCP4_SLOT = 10,
659 RT_IDX_RSS_TCP6_SLOT = 11,
660 RT_IDX_CAM_HIT_SLOT = 12,
661 RT_IDX_UNUSED013 = 13,
662 RT_IDX_UNUSED014 = 14,
663 RT_IDX_PROMISCUOUS_SLOT = 15,
664 RT_IDX_MAX_SLOTS = 16,
665 };
666
667 /*
668 * Control Register Set Map
669 */
670 enum {
671 PROC_ADDR = 0, /* Use semaphore */
672 PROC_DATA = 0x04, /* Use semaphore */
673 SYS = 0x08,
674 RST_FO = 0x0c,
675 FSC = 0x10,
676 CSR = 0x14,
677 LED = 0x18,
678 ICB_RID = 0x1c, /* Use semaphore */
679 ICB_L = 0x20, /* Use semaphore */
680 ICB_H = 0x24, /* Use semaphore */
681 CFG = 0x28,
682 BIOS_ADDR = 0x2c,
683 STS = 0x30,
684 INTR_EN = 0x34,
685 INTR_MASK = 0x38,
686 ISR1 = 0x3c,
687 ISR2 = 0x40,
688 ISR3 = 0x44,
689 ISR4 = 0x48,
690 REV_ID = 0x4c,
691 FRC_ECC_ERR = 0x50,
692 ERR_STS = 0x54,
693 RAM_DBG_ADDR = 0x58,
694 RAM_DBG_DATA = 0x5c,
695 ECC_ERR_CNT = 0x60,
696 SEM = 0x64,
697 GPIO_1 = 0x68, /* Use semaphore */
698 GPIO_2 = 0x6c, /* Use semaphore */
699 GPIO_3 = 0x70, /* Use semaphore */
700 RSVD2 = 0x74,
701 XGMAC_ADDR = 0x78, /* Use semaphore */
702 XGMAC_DATA = 0x7c, /* Use semaphore */
703 NIC_ETS = 0x80,
704 CNA_ETS = 0x84,
705 FLASH_ADDR = 0x88, /* Use semaphore */
706 FLASH_DATA = 0x8c, /* Use semaphore */
707 CQ_STOP = 0x90,
708 PAGE_TBL_RID = 0x94,
709 WQ_PAGE_TBL_LO = 0x98,
710 WQ_PAGE_TBL_HI = 0x9c,
711 CQ_PAGE_TBL_LO = 0xa0,
712 CQ_PAGE_TBL_HI = 0xa4,
713 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
714 MAC_ADDR_DATA = 0xac, /* Use semaphore */
715 COS_DFLT_CQ1 = 0xb0,
716 COS_DFLT_CQ2 = 0xb4,
717 ETYPE_SKIP1 = 0xb8,
718 ETYPE_SKIP2 = 0xbc,
719 SPLT_HDR = 0xc0,
720 FC_PAUSE_THRES = 0xc4,
721 NIC_PAUSE_THRES = 0xc8,
722 FC_ETHERTYPE = 0xcc,
723 FC_RCV_CFG = 0xd0,
724 NIC_RCV_CFG = 0xd4,
725 FC_COS_TAGS = 0xd8,
726 NIC_COS_TAGS = 0xdc,
727 MGMT_RCV_CFG = 0xe0,
728 RT_IDX = 0xe4,
729 RT_DATA = 0xe8,
730 RSVD7 = 0xec,
731 XG_SERDES_ADDR = 0xf0,
732 XG_SERDES_DATA = 0xf4,
733 PRB_MX_ADDR = 0xf8, /* Use semaphore */
734 PRB_MX_DATA = 0xfc, /* Use semaphore */
735 };
736
737 /*
738 * CAM output format.
739 */
740 enum {
741 CAM_OUT_ROUTE_FC = 0,
742 CAM_OUT_ROUTE_NIC = 1,
743 CAM_OUT_FUNC_SHIFT = 2,
744 CAM_OUT_RV = (1 << 4),
745 CAM_OUT_SH = (1 << 15),
746 CAM_OUT_CQ_ID_SHIFT = 5,
747 };
748
749 /*
750 * Mailbox definitions
751 */
752 enum {
753 /* Asynchronous Event Notifications */
754 AEN_SYS_ERR = 0x00008002,
755 AEN_LINK_UP = 0x00008011,
756 AEN_LINK_DOWN = 0x00008012,
757 AEN_IDC_CMPLT = 0x00008100,
758 AEN_IDC_REQ = 0x00008101,
759 AEN_IDC_EXT = 0x00008102,
760 AEN_DCBX_CHG = 0x00008110,
761 AEN_AEN_LOST = 0x00008120,
762 AEN_AEN_SFP_IN = 0x00008130,
763 AEN_AEN_SFP_OUT = 0x00008131,
764 AEN_FW_INIT_DONE = 0x00008400,
765 AEN_FW_INIT_FAIL = 0x00008401,
766
767 /* Mailbox Command Opcodes. */
768 MB_CMD_NOP = 0x00000000,
769 MB_CMD_EX_FW = 0x00000002,
770 MB_CMD_MB_TEST = 0x00000006,
771 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
772 MB_CMD_ABOUT_FW = 0x00000008,
773 MB_CMD_COPY_RISC_RAM = 0x0000000a,
774 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
775 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
776 MB_CMD_WRITE_RAM = 0x0000000d,
777 MB_CMD_INIT_RISC_RAM = 0x0000000e,
778 MB_CMD_READ_RAM = 0x0000000f,
779 MB_CMD_STOP_FW = 0x00000014,
780 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
781 MB_CMD_WRITE_SFP = 0x00000030,
782 MB_CMD_READ_SFP = 0x00000031,
783 MB_CMD_INIT_FW = 0x00000060,
784 MB_CMD_GET_IFCB = 0x00000061,
785 MB_CMD_GET_FW_STATE = 0x00000069,
786 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
787 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
788 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
789 MB_WOL_DISABLE = 0,
790 MB_WOL_MAGIC_PKT = (1 << 1),
791 MB_WOL_FLTR = (1 << 2),
792 MB_WOL_UCAST = (1 << 3),
793 MB_WOL_MCAST = (1 << 4),
794 MB_WOL_BCAST = (1 << 5),
795 MB_WOL_LINK_UP = (1 << 6),
796 MB_WOL_LINK_DOWN = (1 << 7),
797 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
798 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
799 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
800 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
801 MB_CMD_SET_WOL_IMMED = 0x00000115,
802 MB_CMD_PORT_RESET = 0x00000120,
803 MB_CMD_SET_PORT_CFG = 0x00000122,
804 MB_CMD_GET_PORT_CFG = 0x00000123,
805 MB_CMD_GET_LINK_STS = 0x00000124,
806 MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */
807 MB_SET_MPI_TFK_STOP = (1 << 0),
808 MB_SET_MPI_TFK_RESUME = (1 << 1),
809 MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */
810 MB_GET_MPI_TFK_STOPPED = (1 << 0),
811 MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
812
813 /* Mailbox Command Status. */
814 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
815 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
816 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
817 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
818 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
819 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
820 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
821 };
822
823 struct mbox_params {
824 u32 mbox_in[MAILBOX_COUNT];
825 u32 mbox_out[MAILBOX_COUNT];
826 int in_count;
827 int out_count;
828 };
829
830 struct flash_params_8012 {
831 u8 dev_id_str[4];
832 __le16 size;
833 __le16 csum;
834 __le16 ver;
835 __le16 sub_dev_id;
836 u8 mac_addr[6];
837 __le16 res;
838 };
839
840 /* 8000 device's flash is a different structure
841 * at a different offset in flash.
842 */
843 #define FUNC0_FLASH_OFFSET 0x140200
844 #define FUNC1_FLASH_OFFSET 0x140600
845
846 /* Flash related data structures. */
847 struct flash_params_8000 {
848 u8 dev_id_str[4]; /* "8000" */
849 __le16 ver;
850 __le16 size;
851 __le16 csum;
852 __le16 reserved0;
853 __le16 total_size;
854 __le16 entry_count;
855 u8 data_type0;
856 u8 data_size0;
857 u8 mac_addr[6];
858 u8 data_type1;
859 u8 data_size1;
860 u8 mac_addr1[6];
861 u8 data_type2;
862 u8 data_size2;
863 __le16 vlan_id;
864 u8 data_type3;
865 u8 data_size3;
866 __le16 last;
867 u8 reserved1[464];
868 __le16 subsys_ven_id;
869 __le16 subsys_dev_id;
870 u8 reserved2[4];
871 };
872
873 union flash_params {
874 struct flash_params_8012 flash_params_8012;
875 struct flash_params_8000 flash_params_8000;
876 };
877
878 /*
879 * doorbell space for the rx ring context
880 */
881 struct rx_doorbell_context {
882 u32 cnsmr_idx; /* 0x00 */
883 u32 valid; /* 0x04 */
884 u32 reserved[4]; /* 0x08-0x14 */
885 u32 lbq_prod_idx; /* 0x18 */
886 u32 sbq_prod_idx; /* 0x1c */
887 };
888
889 /*
890 * doorbell space for the tx ring context
891 */
892 struct tx_doorbell_context {
893 u32 prod_idx; /* 0x00 */
894 u32 valid; /* 0x04 */
895 u32 reserved[4]; /* 0x08-0x14 */
896 u32 lbq_prod_idx; /* 0x18 */
897 u32 sbq_prod_idx; /* 0x1c */
898 };
899
900 /* DATA STRUCTURES SHARED WITH HARDWARE. */
901 struct tx_buf_desc {
902 __le64 addr;
903 __le32 len;
904 #define TX_DESC_LEN_MASK 0x000fffff
905 #define TX_DESC_C 0x40000000
906 #define TX_DESC_E 0x80000000
907 } __attribute((packed));
908
909 /*
910 * IOCB Definitions...
911 */
912
913 #define OPCODE_OB_MAC_IOCB 0x01
914 #define OPCODE_OB_MAC_TSO_IOCB 0x02
915 #define OPCODE_IB_MAC_IOCB 0x20
916 #define OPCODE_IB_MPI_IOCB 0x21
917 #define OPCODE_IB_AE_IOCB 0x3f
918
919 struct ob_mac_iocb_req {
920 u8 opcode;
921 u8 flags1;
922 #define OB_MAC_IOCB_REQ_OI 0x01
923 #define OB_MAC_IOCB_REQ_I 0x02
924 #define OB_MAC_IOCB_REQ_D 0x08
925 #define OB_MAC_IOCB_REQ_F 0x10
926 u8 flags2;
927 u8 flags3;
928 #define OB_MAC_IOCB_DFP 0x02
929 #define OB_MAC_IOCB_V 0x04
930 __le32 reserved1[2];
931 __le16 frame_len;
932 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
933 __le16 reserved2;
934 u32 tid;
935 u32 txq_idx;
936 __le32 reserved3;
937 __le16 vlan_tci;
938 __le16 reserved4;
939 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
940 } __attribute((packed));
941
942 struct ob_mac_iocb_rsp {
943 u8 opcode; /* */
944 u8 flags1; /* */
945 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
946 #define OB_MAC_IOCB_RSP_I 0x02 /* */
947 #define OB_MAC_IOCB_RSP_E 0x08 /* */
948 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
949 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
950 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
951 u8 flags2; /* */
952 u8 flags3; /* */
953 #define OB_MAC_IOCB_RSP_B 0x80 /* */
954 u32 tid;
955 u32 txq_idx;
956 __le32 reserved[13];
957 } __attribute((packed));
958
959 struct ob_mac_tso_iocb_req {
960 u8 opcode;
961 u8 flags1;
962 #define OB_MAC_TSO_IOCB_OI 0x01
963 #define OB_MAC_TSO_IOCB_I 0x02
964 #define OB_MAC_TSO_IOCB_D 0x08
965 #define OB_MAC_TSO_IOCB_IP4 0x40
966 #define OB_MAC_TSO_IOCB_IP6 0x80
967 u8 flags2;
968 #define OB_MAC_TSO_IOCB_LSO 0x20
969 #define OB_MAC_TSO_IOCB_UC 0x40
970 #define OB_MAC_TSO_IOCB_TC 0x80
971 u8 flags3;
972 #define OB_MAC_TSO_IOCB_IC 0x01
973 #define OB_MAC_TSO_IOCB_DFP 0x02
974 #define OB_MAC_TSO_IOCB_V 0x04
975 __le32 reserved1[2];
976 __le32 frame_len;
977 u32 tid;
978 u32 txq_idx;
979 __le16 total_hdrs_len;
980 __le16 net_trans_offset;
981 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
982 __le16 vlan_tci;
983 __le16 mss;
984 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
985 } __attribute((packed));
986
987 struct ob_mac_tso_iocb_rsp {
988 u8 opcode;
989 u8 flags1;
990 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
991 #define OB_MAC_TSO_IOCB_RSP_I 0x02
992 #define OB_MAC_TSO_IOCB_RSP_E 0x08
993 #define OB_MAC_TSO_IOCB_RSP_S 0x10
994 #define OB_MAC_TSO_IOCB_RSP_L 0x20
995 #define OB_MAC_TSO_IOCB_RSP_P 0x40
996 u8 flags2; /* */
997 u8 flags3; /* */
998 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
999 u32 tid;
1000 u32 txq_idx;
1001 __le32 reserved2[13];
1002 } __attribute((packed));
1003
1004 struct ib_mac_iocb_rsp {
1005 u8 opcode; /* 0x20 */
1006 u8 flags1;
1007 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
1008 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
1009 #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
1010 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
1011 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
1012 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
1013 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
1014 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
1015 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1016 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1017 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1018 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1019 u8 flags2;
1020 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1021 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1022 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1023 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1024 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1025 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1026 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1027 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1028 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1029 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1030 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1031 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1032 u8 flags3;
1033 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1034 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1035 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1036 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1037 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1038 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1039 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1040 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1041 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1042 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1043 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1044 __le32 data_len; /* */
1045 __le64 data_addr; /* */
1046 __le32 rss; /* */
1047 __le16 vlan_id; /* 12 bits */
1048 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1049 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
1050 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1051
1052 __le16 reserved1;
1053 __le32 reserved2[6];
1054 u8 reserved3[3];
1055 u8 flags4;
1056 #define IB_MAC_IOCB_RSP_HV 0x20
1057 #define IB_MAC_IOCB_RSP_HS 0x40
1058 #define IB_MAC_IOCB_RSP_HL 0x80
1059 __le32 hdr_len; /* */
1060 __le64 hdr_addr; /* */
1061 } __attribute((packed));
1062
1063 struct ib_ae_iocb_rsp {
1064 u8 opcode;
1065 u8 flags1;
1066 #define IB_AE_IOCB_RSP_OI 0x01
1067 #define IB_AE_IOCB_RSP_I 0x02
1068 u8 event;
1069 #define LINK_UP_EVENT 0x00
1070 #define LINK_DOWN_EVENT 0x01
1071 #define CAM_LOOKUP_ERR_EVENT 0x06
1072 #define SOFT_ECC_ERROR_EVENT 0x07
1073 #define MGMT_ERR_EVENT 0x08
1074 #define TEN_GIG_MAC_EVENT 0x09
1075 #define GPI0_H2L_EVENT 0x10
1076 #define GPI0_L2H_EVENT 0x20
1077 #define GPI1_H2L_EVENT 0x11
1078 #define GPI1_L2H_EVENT 0x21
1079 #define PCI_ERR_ANON_BUF_RD 0x40
1080 u8 q_id;
1081 __le32 reserved[15];
1082 } __attribute((packed));
1083
1084 /*
1085 * These three structures are for generic
1086 * handling of ib and ob iocbs.
1087 */
1088 struct ql_net_rsp_iocb {
1089 u8 opcode;
1090 u8 flags0;
1091 __le16 length;
1092 __le32 tid;
1093 __le32 reserved[14];
1094 } __attribute((packed));
1095
1096 struct net_req_iocb {
1097 u8 opcode;
1098 u8 flags0;
1099 __le16 flags1;
1100 __le32 tid;
1101 __le32 reserved1[30];
1102 } __attribute((packed));
1103
1104 /*
1105 * tx ring initialization control block for chip.
1106 * It is defined as:
1107 * "Work Queue Initialization Control Block"
1108 */
1109 struct wqicb {
1110 __le16 len;
1111 #define Q_LEN_V (1 << 4)
1112 #define Q_LEN_CPP_CONT 0x0000
1113 #define Q_LEN_CPP_16 0x0001
1114 #define Q_LEN_CPP_32 0x0002
1115 #define Q_LEN_CPP_64 0x0003
1116 #define Q_LEN_CPP_512 0x0006
1117 __le16 flags;
1118 #define Q_PRI_SHIFT 1
1119 #define Q_FLAGS_LC 0x1000
1120 #define Q_FLAGS_LB 0x2000
1121 #define Q_FLAGS_LI 0x4000
1122 #define Q_FLAGS_LO 0x8000
1123 __le16 cq_id_rss;
1124 #define Q_CQ_ID_RSS_RV 0x8000
1125 __le16 rid;
1126 __le64 addr;
1127 __le64 cnsmr_idx_addr;
1128 } __attribute((packed));
1129
1130 /*
1131 * rx ring initialization control block for chip.
1132 * It is defined as:
1133 * "Completion Queue Initialization Control Block"
1134 */
1135 struct cqicb {
1136 u8 msix_vect;
1137 u8 reserved1;
1138 u8 reserved2;
1139 u8 flags;
1140 #define FLAGS_LV 0x08
1141 #define FLAGS_LS 0x10
1142 #define FLAGS_LL 0x20
1143 #define FLAGS_LI 0x40
1144 #define FLAGS_LC 0x80
1145 __le16 len;
1146 #define LEN_V (1 << 4)
1147 #define LEN_CPP_CONT 0x0000
1148 #define LEN_CPP_32 0x0001
1149 #define LEN_CPP_64 0x0002
1150 #define LEN_CPP_128 0x0003
1151 __le16 rid;
1152 __le64 addr;
1153 __le64 prod_idx_addr;
1154 __le16 pkt_delay;
1155 __le16 irq_delay;
1156 __le64 lbq_addr;
1157 __le16 lbq_buf_size;
1158 __le16 lbq_len; /* entry count */
1159 __le64 sbq_addr;
1160 __le16 sbq_buf_size;
1161 __le16 sbq_len; /* entry count */
1162 } __attribute((packed));
1163
1164 struct ricb {
1165 u8 base_cq;
1166 #define RSS_L4K 0x80
1167 u8 flags;
1168 #define RSS_L6K 0x01
1169 #define RSS_LI 0x02
1170 #define RSS_LB 0x04
1171 #define RSS_LM 0x08
1172 #define RSS_RI4 0x10
1173 #define RSS_RT4 0x20
1174 #define RSS_RI6 0x40
1175 #define RSS_RT6 0x80
1176 __le16 mask;
1177 u8 hash_cq_id[1024];
1178 __le32 ipv6_hash_key[10];
1179 __le32 ipv4_hash_key[4];
1180 } __attribute((packed));
1181
1182 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1183
1184 struct oal {
1185 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1186 };
1187
1188 struct map_list {
1189 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1190 DECLARE_PCI_UNMAP_LEN(maplen);
1191 };
1192
1193 struct tx_ring_desc {
1194 struct sk_buff *skb;
1195 struct ob_mac_iocb_req *queue_entry;
1196 u32 index;
1197 struct oal oal;
1198 struct map_list map[MAX_SKB_FRAGS + 1];
1199 int map_cnt;
1200 struct tx_ring_desc *next;
1201 };
1202
1203 struct bq_desc {
1204 union {
1205 struct page *lbq_page;
1206 struct sk_buff *skb;
1207 } p;
1208 __le64 *addr;
1209 u32 index;
1210 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1211 DECLARE_PCI_UNMAP_LEN(maplen);
1212 };
1213
1214 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1215
1216 struct tx_ring {
1217 /*
1218 * queue info.
1219 */
1220 struct wqicb wqicb; /* structure used to inform chip of new queue */
1221 void *wq_base; /* pci_alloc:virtual addr for tx */
1222 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
1223 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
1224 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1225 u32 wq_size; /* size in bytes of queue area */
1226 u32 wq_len; /* number of entries in queue */
1227 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1228 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1229 u16 prod_idx; /* current value for prod idx */
1230 u16 cq_id; /* completion (rx) queue for tx completions */
1231 u8 wq_id; /* queue id for this entry */
1232 u8 reserved1[3];
1233 struct tx_ring_desc *q; /* descriptor list for the queue */
1234 spinlock_t lock;
1235 atomic_t tx_count; /* counts down for every outstanding IO */
1236 atomic_t queue_stopped; /* Turns queue off when full. */
1237 struct delayed_work tx_work;
1238 struct ql_adapter *qdev;
1239 };
1240
1241 /*
1242 * Type of inbound queue.
1243 */
1244 enum {
1245 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1246 TX_Q = 3, /* Handles outbound completions. */
1247 RX_Q = 4, /* Handles inbound completions. */
1248 };
1249
1250 struct rx_ring {
1251 struct cqicb cqicb; /* The chip's completion queue init control block. */
1252
1253 /* Completion queue elements. */
1254 void *cq_base;
1255 dma_addr_t cq_base_dma;
1256 u32 cq_size;
1257 u32 cq_len;
1258 u16 cq_id;
1259 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
1260 dma_addr_t prod_idx_sh_reg_dma;
1261 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1262 u32 cnsmr_idx; /* current sw idx */
1263 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1264 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1265
1266 /* Large buffer queue elements. */
1267 u32 lbq_len; /* entry count */
1268 u32 lbq_size; /* size in bytes of queue */
1269 u32 lbq_buf_size;
1270 void *lbq_base;
1271 dma_addr_t lbq_base_dma;
1272 void *lbq_base_indirect;
1273 dma_addr_t lbq_base_indirect_dma;
1274 struct bq_desc *lbq; /* array of control blocks */
1275 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1276 u32 lbq_prod_idx; /* current sw prod idx */
1277 u32 lbq_curr_idx; /* next entry we expect */
1278 u32 lbq_clean_idx; /* beginning of new descs */
1279 u32 lbq_free_cnt; /* free buffer desc cnt */
1280
1281 /* Small buffer queue elements. */
1282 u32 sbq_len; /* entry count */
1283 u32 sbq_size; /* size in bytes of queue */
1284 u32 sbq_buf_size;
1285 void *sbq_base;
1286 dma_addr_t sbq_base_dma;
1287 void *sbq_base_indirect;
1288 dma_addr_t sbq_base_indirect_dma;
1289 struct bq_desc *sbq; /* array of control blocks */
1290 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1291 u32 sbq_prod_idx; /* current sw prod idx */
1292 u32 sbq_curr_idx; /* next entry we expect */
1293 u32 sbq_clean_idx; /* beginning of new descs */
1294 u32 sbq_free_cnt; /* free buffer desc cnt */
1295
1296 /* Misc. handler elements. */
1297 u32 type; /* Type of queue, tx, rx. */
1298 u32 irq; /* Which vector this ring is assigned. */
1299 u32 cpu; /* Which CPU this should run on. */
1300 char name[IFNAMSIZ + 5];
1301 struct napi_struct napi;
1302 u8 reserved;
1303 struct ql_adapter *qdev;
1304 };
1305
1306 /*
1307 * RSS Initialization Control Block
1308 */
1309 struct hash_id {
1310 u8 value[4];
1311 };
1312
1313 struct nic_stats {
1314 /*
1315 * These stats come from offset 200h to 278h
1316 * in the XGMAC register.
1317 */
1318 u64 tx_pkts;
1319 u64 tx_bytes;
1320 u64 tx_mcast_pkts;
1321 u64 tx_bcast_pkts;
1322 u64 tx_ucast_pkts;
1323 u64 tx_ctl_pkts;
1324 u64 tx_pause_pkts;
1325 u64 tx_64_pkt;
1326 u64 tx_65_to_127_pkt;
1327 u64 tx_128_to_255_pkt;
1328 u64 tx_256_511_pkt;
1329 u64 tx_512_to_1023_pkt;
1330 u64 tx_1024_to_1518_pkt;
1331 u64 tx_1519_to_max_pkt;
1332 u64 tx_undersize_pkt;
1333 u64 tx_oversize_pkt;
1334
1335 /*
1336 * These stats come from offset 300h to 3C8h
1337 * in the XGMAC register.
1338 */
1339 u64 rx_bytes;
1340 u64 rx_bytes_ok;
1341 u64 rx_pkts;
1342 u64 rx_pkts_ok;
1343 u64 rx_bcast_pkts;
1344 u64 rx_mcast_pkts;
1345 u64 rx_ucast_pkts;
1346 u64 rx_undersize_pkts;
1347 u64 rx_oversize_pkts;
1348 u64 rx_jabber_pkts;
1349 u64 rx_undersize_fcerr_pkts;
1350 u64 rx_drop_events;
1351 u64 rx_fcerr_pkts;
1352 u64 rx_align_err;
1353 u64 rx_symbol_err;
1354 u64 rx_mac_err;
1355 u64 rx_ctl_pkts;
1356 u64 rx_pause_pkts;
1357 u64 rx_64_pkts;
1358 u64 rx_65_to_127_pkts;
1359 u64 rx_128_255_pkts;
1360 u64 rx_256_511_pkts;
1361 u64 rx_512_to_1023_pkts;
1362 u64 rx_1024_to_1518_pkts;
1363 u64 rx_1519_to_max_pkts;
1364 u64 rx_len_err_pkts;
1365 };
1366
1367 /*
1368 * intr_context structure is used during initialization
1369 * to hook the interrupts. It is also used in a single
1370 * irq environment as a context to the ISR.
1371 */
1372 struct intr_context {
1373 struct ql_adapter *qdev;
1374 u32 intr;
1375 u32 irq_mask; /* Mask of which rings the vector services. */
1376 u32 hooked;
1377 u32 intr_en_mask; /* value/mask used to enable this intr */
1378 u32 intr_dis_mask; /* value/mask used to disable this intr */
1379 u32 intr_read_mask; /* value/mask used to read this intr */
1380 char name[IFNAMSIZ * 2];
1381 atomic_t irq_cnt; /* irq_cnt is used in single vector
1382 * environment. It's incremented for each
1383 * irq handler that is scheduled. When each
1384 * handler finishes it decrements irq_cnt and
1385 * enables interrupts if it's zero. */
1386 irq_handler_t handler;
1387 };
1388
1389 /* adapter flags definitions. */
1390 enum {
1391 QL_ADAPTER_UP = 0, /* Adapter has been brought up. */
1392 QL_LEGACY_ENABLED = 1,
1393 QL_MSI_ENABLED = 2,
1394 QL_MSIX_ENABLED = 3,
1395 QL_DMA64 = 4,
1396 QL_PROMISCUOUS = 5,
1397 QL_ALLMULTI = 6,
1398 QL_PORT_CFG = 7,
1399 QL_CAM_RT_SET = 8,
1400 };
1401
1402 /* link_status bit definitions */
1403 enum {
1404 STS_LOOPBACK_MASK = 0x00000700,
1405 STS_LOOPBACK_PCS = 0x00000100,
1406 STS_LOOPBACK_HSS = 0x00000200,
1407 STS_LOOPBACK_EXT = 0x00000300,
1408 STS_PAUSE_MASK = 0x000000c0,
1409 STS_PAUSE_STD = 0x00000040,
1410 STS_PAUSE_PRI = 0x00000080,
1411 STS_SPEED_MASK = 0x00000038,
1412 STS_SPEED_100Mb = 0x00000000,
1413 STS_SPEED_1Gb = 0x00000008,
1414 STS_SPEED_10Gb = 0x00000010,
1415 STS_LINK_TYPE_MASK = 0x00000007,
1416 STS_LINK_TYPE_XFI = 0x00000001,
1417 STS_LINK_TYPE_XAUI = 0x00000002,
1418 STS_LINK_TYPE_XFI_BP = 0x00000003,
1419 STS_LINK_TYPE_XAUI_BP = 0x00000004,
1420 STS_LINK_TYPE_10GBASET = 0x00000005,
1421 };
1422
1423 /* link_config bit definitions */
1424 enum {
1425 CFG_JUMBO_FRAME_SIZE = 0x00010000,
1426 CFG_PAUSE_MASK = 0x00000060,
1427 CFG_PAUSE_STD = 0x00000020,
1428 CFG_PAUSE_PRI = 0x00000040,
1429 CFG_DCBX = 0x00000010,
1430 CFG_LOOPBACK_MASK = 0x00000007,
1431 CFG_LOOPBACK_PCS = 0x00000002,
1432 CFG_LOOPBACK_HSS = 0x00000004,
1433 CFG_LOOPBACK_EXT = 0x00000006,
1434 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
1435 };
1436
1437 struct nic_operations {
1438
1439 int (*get_flash) (struct ql_adapter *);
1440 int (*port_initialize) (struct ql_adapter *);
1441 };
1442
1443 /*
1444 * The main Adapter structure definition.
1445 * This structure has all fields relevant to the hardware.
1446 */
1447 struct ql_adapter {
1448 struct ricb ricb;
1449 unsigned long flags;
1450 u32 wol;
1451
1452 struct nic_stats nic_stats;
1453
1454 struct vlan_group *vlgrp;
1455
1456 /* PCI Configuration information for this device */
1457 struct pci_dev *pdev;
1458 struct net_device *ndev; /* Parent NET device */
1459
1460 /* Hardware information */
1461 u32 chip_rev_id;
1462 u32 fw_rev_id;
1463 u32 func; /* PCI function for this adapter */
1464 u32 alt_func; /* PCI function for alternate adapter */
1465 u32 port; /* Port number this adapter */
1466
1467 spinlock_t adapter_lock;
1468 spinlock_t hw_lock;
1469 spinlock_t stats_lock;
1470
1471 /* PCI Bus Relative Register Addresses */
1472 void __iomem *reg_base;
1473 void __iomem *doorbell_area;
1474 u32 doorbell_area_size;
1475
1476 u32 msg_enable;
1477
1478 /* Page for Shadow Registers */
1479 void *rx_ring_shadow_reg_area;
1480 dma_addr_t rx_ring_shadow_reg_dma;
1481 void *tx_ring_shadow_reg_area;
1482 dma_addr_t tx_ring_shadow_reg_dma;
1483
1484 u32 mailbox_in;
1485 u32 mailbox_out;
1486 struct mbox_params idc_mbc;
1487
1488 int tx_ring_size;
1489 int rx_ring_size;
1490 u32 intr_count;
1491 struct msix_entry *msi_x_entry;
1492 struct intr_context intr_context[MAX_RX_RINGS];
1493
1494 int tx_ring_count; /* One per online CPU. */
1495 u32 rss_ring_count; /* One per irq vector. */
1496 /*
1497 * rx_ring_count =
1498 * (CPU count * outbound completion rx_ring) +
1499 * (irq_vector_cnt * inbound (RSS) completion rx_ring)
1500 */
1501 int rx_ring_count;
1502 int ring_mem_size;
1503 void *ring_mem;
1504
1505 struct rx_ring rx_ring[MAX_RX_RINGS];
1506 struct tx_ring tx_ring[MAX_TX_RINGS];
1507
1508 int rx_csum;
1509 u32 default_rx_queue;
1510
1511 u16 rx_coalesce_usecs; /* cqicb->int_delay */
1512 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1513 u16 tx_coalesce_usecs; /* cqicb->int_delay */
1514 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1515
1516 u32 xg_sem_mask;
1517 u32 port_link_up;
1518 u32 port_init;
1519 u32 link_status;
1520 u32 link_config;
1521 u32 max_frame_size;
1522
1523 union flash_params flash;
1524
1525 struct net_device_stats stats;
1526 struct workqueue_struct *workqueue;
1527 struct delayed_work asic_reset_work;
1528 struct delayed_work mpi_reset_work;
1529 struct delayed_work mpi_work;
1530 struct delayed_work mpi_port_cfg_work;
1531 struct delayed_work mpi_idc_work;
1532 struct completion ide_completion;
1533 struct nic_operations *nic_ops;
1534 u16 device_id;
1535 };
1536
1537 /*
1538 * Typical Register accessor for memory mapped device.
1539 */
1540 static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
1541 {
1542 return readl(qdev->reg_base + reg);
1543 }
1544
1545 /*
1546 * Typical Register accessor for memory mapped device.
1547 */
1548 static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
1549 {
1550 writel(val, qdev->reg_base + reg);
1551 }
1552
1553 /*
1554 * Doorbell Registers:
1555 * Doorbell registers are virtual registers in the PCI memory space.
1556 * The space is allocated by the chip during PCI initialization. The
1557 * device driver finds the doorbell address in BAR 3 in PCI config space.
1558 * The registers are used to control outbound and inbound queues. For
1559 * example, the producer index for an outbound queue. Each queue uses
1560 * 1 4k chunk of memory. The lower half of the space is for outbound
1561 * queues. The upper half is for inbound queues.
1562 */
1563 static inline void ql_write_db_reg(u32 val, void __iomem *addr)
1564 {
1565 writel(val, addr);
1566 mmiowb();
1567 }
1568
1569 /*
1570 * Shadow Registers:
1571 * Outbound queues have a consumer index that is maintained by the chip.
1572 * Inbound queues have a producer index that is maintained by the chip.
1573 * For lower overhead, these registers are "shadowed" to host memory
1574 * which allows the device driver to track the queue progress without
1575 * PCI reads. When an entry is placed on an inbound queue, the chip will
1576 * update the relevant index register and then copy the value to the
1577 * shadow register in host memory.
1578 */
1579 static inline u32 ql_read_sh_reg(__le32 *addr)
1580 {
1581 u32 reg;
1582 reg = le32_to_cpu(*addr);
1583 rmb();
1584 return reg;
1585 }
1586
1587 extern char qlge_driver_name[];
1588 extern const char qlge_driver_version[];
1589 extern const struct ethtool_ops qlge_ethtool_ops;
1590
1591 extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
1592 extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
1593 extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1594 extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
1595 u32 *value);
1596 extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
1597 extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
1598 u16 q_id);
1599 void ql_queue_fw_error(struct ql_adapter *qdev);
1600 void ql_mpi_work(struct work_struct *work);
1601 void ql_mpi_reset_work(struct work_struct *work);
1602 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
1603 void ql_queue_asic_error(struct ql_adapter *qdev);
1604 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
1605 void ql_set_ethtool_ops(struct net_device *ndev);
1606 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
1607 void ql_mpi_idc_work(struct work_struct *work);
1608 void ql_mpi_port_cfg_work(struct work_struct *work);
1609 int ql_mb_get_fw_state(struct ql_adapter *qdev);
1610 int ql_cam_route_initialize(struct ql_adapter *qdev);
1611 int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1612 int ql_mb_about_fw(struct ql_adapter *qdev);
1613 void ql_link_on(struct ql_adapter *qdev);
1614 void ql_link_off(struct ql_adapter *qdev);
1615 int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
1616 int ql_wait_fifo_empty(struct ql_adapter *qdev);
1617
1618 #if 1
1619 #define QL_ALL_DUMP
1620 #define QL_REG_DUMP
1621 #define QL_DEV_DUMP
1622 #define QL_CB_DUMP
1623 /* #define QL_IB_DUMP */
1624 /* #define QL_OB_DUMP */
1625 #endif
1626
1627 #ifdef QL_REG_DUMP
1628 extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
1629 extern void ql_dump_routing_entries(struct ql_adapter *qdev);
1630 extern void ql_dump_regs(struct ql_adapter *qdev);
1631 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1632 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1633 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1634 #else
1635 #define QL_DUMP_REGS(qdev)
1636 #define QL_DUMP_ROUTE(qdev)
1637 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1638 #endif
1639
1640 #ifdef QL_STAT_DUMP
1641 extern void ql_dump_stat(struct ql_adapter *qdev);
1642 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1643 #else
1644 #define QL_DUMP_STAT(qdev)
1645 #endif
1646
1647 #ifdef QL_DEV_DUMP
1648 extern void ql_dump_qdev(struct ql_adapter *qdev);
1649 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1650 #else
1651 #define QL_DUMP_QDEV(qdev)
1652 #endif
1653
1654 #ifdef QL_CB_DUMP
1655 extern void ql_dump_wqicb(struct wqicb *wqicb);
1656 extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
1657 extern void ql_dump_ricb(struct ricb *ricb);
1658 extern void ql_dump_cqicb(struct cqicb *cqicb);
1659 extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
1660 extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
1661 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1662 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1663 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1664 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1665 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1666 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1667 ql_dump_hw_cb(qdev, size, bit, q_id)
1668 #else
1669 #define QL_DUMP_RICB(ricb)
1670 #define QL_DUMP_WQICB(wqicb)
1671 #define QL_DUMP_TX_RING(tx_ring)
1672 #define QL_DUMP_CQICB(cqicb)
1673 #define QL_DUMP_RX_RING(rx_ring)
1674 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1675 #endif
1676
1677 #ifdef QL_OB_DUMP
1678 extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
1679 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
1680 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
1681 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1682 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1683 #else
1684 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1685 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1686 #endif
1687
1688 #ifdef QL_IB_DUMP
1689 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
1690 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1691 #else
1692 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1693 #endif
1694
1695 #ifdef QL_ALL_DUMP
1696 extern void ql_dump_all(struct ql_adapter *qdev);
1697 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1698 #else
1699 #define QL_DUMP_ALL(qdev)
1700 #endif
1701
1702 #endif /* _QLGE_H_ */
Linux for Ginger Game Console