arch/arm/mach-ep93xx/clock.c

   1 /*
   2  * arch/arm/mach-ep93xx/clock.c
   3  * Clock control for Cirrus EP93xx chips.
   4  *
   5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or (at
  10  * your option) any later version.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <linux/string.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/clkdev.h>
  21 #include <asm/div64.h>
  22 #include <mach/hardware.h>
  23
  24 struct clk {
  25         unsigned long   rate;
  26         int             users;
  27         u32             enable_reg;
  28         u32             enable_mask;
  29 };
  30
  31 static struct clk clk_uart = {
  32         .rate           = 14745600,
  33 };
  34 static struct clk clk_pll1;
  35 static struct clk clk_f;
  36 static struct clk clk_h;
  37 static struct clk clk_p;
  38 static struct clk clk_pll2;
  39 static struct clk clk_usb_host = {
  40         .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
  41         .enable_mask    = EP93XX_SYSCON_CLOCK_USH_EN,
  42 };
  43
  44 #define INIT_CK(dev,con,ck)                                     \
  45         { .dev_id = dev, .con_id = con, .clk = ck }
  46
  47 static struct clk_lookup clocks[] = {
  48         INIT_CK("apb:uart1", NULL, &clk_uart),
  49         INIT_CK("apb:uart2", NULL, &clk_uart),
  50         INIT_CK("apb:uart3", NULL, &clk_uart),
  51         INIT_CK(NULL, "pll1", &clk_pll1),
  52         INIT_CK(NULL, "fclk", &clk_f),
  53         INIT_CK(NULL, "hclk", &clk_h),
  54         INIT_CK(NULL, "pclk", &clk_p),
  55         INIT_CK(NULL, "pll2", &clk_pll2),
  56         INIT_CK(NULL, "usb_host", &clk_usb_host),
  57 };
  58
  59
  60 int clk_enable(struct clk *clk)
  61 {
  62         if (!clk->users++ && clk->enable_reg) {
  63                 u32 value;
  64
  65                 value = __raw_readl(clk->enable_reg);
  66                 __raw_writel(value | clk->enable_mask, clk->enable_reg);
  67         }
  68
  69         return 0;
  70 }
  71 EXPORT_SYMBOL(clk_enable);
  72
  73 void clk_disable(struct clk *clk)
  74 {
  75         if (!--clk->users && clk->enable_reg) {
  76                 u32 value;
  77
  78                 value = __raw_readl(clk->enable_reg);
  79                 __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
  80         }
  81 }
  82 EXPORT_SYMBOL(clk_disable);
  83
  84 unsigned long clk_get_rate(struct clk *clk)
  85 {
  86         return clk->rate;
  87 }
  88 EXPORT_SYMBOL(clk_get_rate);
  89
  90
  91 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
  92 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
  93 static char pclk_divisors[] = { 1, 2, 4, 8 };
  94
  95 /*
  96  * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
  97  */
  98 static unsigned long calc_pll_rate(u32 config_word)
  99 {
 100         unsigned long long rate;
 101         int i;
 102
 103         rate = 14745600;
 104         rate *= ((config_word >> 11) & 0x1f) + 1;               /* X1FBD */
 105         rate *= ((config_word >> 5) & 0x3f) + 1;                /* X2FBD */
 106         do_div(rate, (config_word & 0x1f) + 1);                 /* X2IPD */
 107         for (i = 0; i < ((config_word >> 16) & 3); i++)         /* PS */
 108                 rate >>= 1;
 109
 110         return (unsigned long)rate;
 111 }
 112
 113 static int __init ep93xx_clock_init(void)
 114 {
 115         u32 value;
 116         int i;
 117
 118         value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
 119         if (!(value & 0x00800000)) {                    /* PLL1 bypassed?  */
 120                 clk_pll1.rate = 14745600;
 121         } else {
 122                 clk_pll1.rate = calc_pll_rate(value);
 123         }
 124         clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
 125         clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
 126         clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
 127
 128         value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
 129         if (!(value & 0x00080000)) {                    /* PLL2 bypassed?  */
 130                 clk_pll2.rate = 14745600;
 131         } else if (value & 0x00040000) {                /* PLL2 enabled?  */
 132                 clk_pll2.rate = calc_pll_rate(value);
 133         } else {
 134                 clk_pll2.rate = 0;
 135         }
 136         clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 137
 138         printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
 139                 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
 140         printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
 141                 clk_f.rate / 1000000, clk_h.rate / 1000000,
 142                 clk_p.rate / 1000000);
 143
 144         for (i = 0; i < ARRAY_SIZE(clocks); i++)
 145                 clkdev_add(&clocks[i]);
 146         return 0;
 147 }
 148 arch_initcall(ep93xx_clock_init);