arch/arm/mach-omap2/mailbox.c

   1 /*
   2  * Mailbox reservation modules for OMAP2/3
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
   6  *        and  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/io.h>
  18 #include <mach/mailbox.h>
  19 #include <mach/irqs.h>
  20
  21 #define DRV_NAME "omap2-mailbox"
  22
  23 #define MAILBOX_REVISION                0x000
  24 #define MAILBOX_SYSCONFIG               0x010
  25 #define MAILBOX_SYSSTATUS               0x014
  26 #define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
  27 #define MAILBOX_FIFOSTATUS(m)           (0x080 + 4 * (m))
  28 #define MAILBOX_MSGSTATUS(m)            (0x0c0 + 4 * (m))
  29 #define MAILBOX_IRQSTATUS(u)            (0x100 + 8 * (u))
  30 #define MAILBOX_IRQENABLE(u)            (0x108 + 8 * (u))
  31
  32 #define MAILBOX_IRQ_NEWMSG(u)           (1 << (2 * (u)))
  33 #define MAILBOX_IRQ_NOTFULL(u)          (1 << (2 * (u) + 1))
  34
  35 #define MBOX_REG_SIZE                   0x120
  36
  37 static void __iomem *mbox_base;
  38
  39 struct omap_mbox2_fifo {
  40         unsigned long msg;
  41         unsigned long fifo_stat;
  42         unsigned long msg_stat;
  43 };
  44
  45 struct omap_mbox2_priv {
  46         struct omap_mbox2_fifo tx_fifo;
  47         struct omap_mbox2_fifo rx_fifo;
  48         unsigned long irqenable;
  49         unsigned long irqstatus;
  50         u32 newmsg_bit;
  51         u32 notfull_bit;
  52         char ctx[MBOX_REG_SIZE];
  53 };
  54
  55 static struct clk *mbox_ick_handle;
  56
  57 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
  58                                   omap_mbox_type_t irq);
  59
  60 static inline unsigned int mbox_read_reg(size_t ofs)
  61 {
  62         return __raw_readl(mbox_base + ofs);
  63 }
  64
  65 static inline void mbox_write_reg(u32 val, size_t ofs)
  66 {
  67         __raw_writel(val, mbox_base + ofs);
  68 }
  69
  70 /* Mailbox H/W preparations */
  71 static int omap2_mbox_startup(struct omap_mbox *mbox)
  72 {
  73         unsigned int l;
  74
  75         mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
  76         if (IS_ERR(mbox_ick_handle)) {
  77                 printk("Could not get mailboxes_ick\n");
  78                 return -ENODEV;
  79         }
  80         clk_enable(mbox_ick_handle);
  81
  82         l = mbox_read_reg(MAILBOX_REVISION);
  83         pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
  84
  85         /* set smart-idle & autoidle */
  86         l = mbox_read_reg(MAILBOX_SYSCONFIG);
  87         l |= 0x00000011;
  88         mbox_write_reg(l, MAILBOX_SYSCONFIG);
  89
  90         omap2_mbox_enable_irq(mbox, IRQ_RX);
  91
  92         return 0;
  93 }
  94
  95 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
  96 {
  97         clk_disable(mbox_ick_handle);
  98         clk_put(mbox_ick_handle);
  99 }
 100
 101 /* Mailbox FIFO handle functions */
 102 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
 103 {
 104         struct omap_mbox2_fifo *fifo =
 105                 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
 106         return (mbox_msg_t) mbox_read_reg(fifo->msg);
 107 }
 108
 109 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
 110 {
 111         struct omap_mbox2_fifo *fifo =
 112                 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
 113         mbox_write_reg(msg, fifo->msg);
 114 }
 115
 116 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
 117 {
 118         struct omap_mbox2_fifo *fifo =
 119                 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
 120         return (mbox_read_reg(fifo->msg_stat) == 0);
 121 }
 122
 123 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
 124 {
 125         struct omap_mbox2_fifo *fifo =
 126                 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
 127         return (mbox_read_reg(fifo->fifo_stat));
 128 }
 129
 130 /* Mailbox IRQ handle functions */
 131 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
 132                 omap_mbox_type_t irq)
 133 {
 134         struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
 135         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 136
 137         l = mbox_read_reg(p->irqenable);
 138         l |= bit;
 139         mbox_write_reg(l, p->irqenable);
 140 }
 141
 142 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
 143                 omap_mbox_type_t irq)
 144 {
 145         struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
 146         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 147
 148         l = mbox_read_reg(p->irqenable);
 149         l &= ~bit;
 150         mbox_write_reg(l, p->irqenable);
 151 }
 152
 153 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
 154                 omap_mbox_type_t irq)
 155 {
 156         struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
 157         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 158
 159         mbox_write_reg(bit, p->irqstatus);
 160 }
 161
 162 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
 163                 omap_mbox_type_t irq)
 164 {
 165         struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
 166         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 167         u32 enable = mbox_read_reg(p->irqenable);
 168         u32 status = mbox_read_reg(p->irqstatus);
 169
 170         return (enable & status & bit);
 171 }
 172
 173 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
 174 {
 175         int i;
 176         struct omap_mbox2_priv *p = mbox->priv;
 177
 178         for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) {
 179                 u32 val;
 180
 181                 val = mbox_read_reg(i);
 182                 *(u32 *)(p->ctx + i) = val;
 183
 184                 dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val);
 185         }
 186 }
 187
 188 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
 189 {
 190         int i;
 191         struct omap_mbox2_priv *p = mbox->priv;
 192
 193         for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) {
 194                 u32 val;
 195
 196                 val = *(u32 *)(p->ctx + i);
 197                 mbox_write_reg(val, i);
 198
 199                 dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val);
 200         }
 201 }
 202
 203 static struct omap_mbox_ops omap2_mbox_ops = {
 204         .type           = OMAP_MBOX_TYPE2,
 205         .startup        = omap2_mbox_startup,
 206         .shutdown       = omap2_mbox_shutdown,
 207         .fifo_read      = omap2_mbox_fifo_read,
 208         .fifo_write     = omap2_mbox_fifo_write,
 209         .fifo_empty     = omap2_mbox_fifo_empty,
 210         .fifo_full      = omap2_mbox_fifo_full,
 211         .enable_irq     = omap2_mbox_enable_irq,
 212         .disable_irq    = omap2_mbox_disable_irq,
 213         .ack_irq        = omap2_mbox_ack_irq,
 214         .is_irq         = omap2_mbox_is_irq,
 215         .save_ctx       = omap2_mbox_save_ctx,
 216         .restore_ctx    = omap2_mbox_restore_ctx,
 217 };
 218
 219 /*
 220  * MAILBOX 0: ARM -> DSP,
 221  * MAILBOX 1: ARM <- DSP.
 222  * MAILBOX 2: ARM -> IVA,
 223  * MAILBOX 3: ARM <- IVA.
 224  */
 225
 226 /* FIXME: the following structs should be filled automatically by the user id */
 227
 228 /* DSP */
 229 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
 230         .tx_fifo = {
 231                 .msg            = MAILBOX_MESSAGE(0),
 232                 .fifo_stat      = MAILBOX_FIFOSTATUS(0),
 233         },
 234         .rx_fifo = {
 235                 .msg            = MAILBOX_MESSAGE(1),
 236                 .msg_stat       = MAILBOX_MSGSTATUS(1),
 237         },
 238         .irqenable      = MAILBOX_IRQENABLE(0),
 239         .irqstatus      = MAILBOX_IRQSTATUS(0),
 240         .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
 241         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
 242 };
 243
 244 struct omap_mbox mbox_dsp_info = {
 245         .name   = "dsp",
 246         .ops    = &omap2_mbox_ops,
 247         .priv   = &omap2_mbox_dsp_priv,
 248 };
 249 EXPORT_SYMBOL(mbox_dsp_info);
 250
 251 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
 252 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
 253         .tx_fifo = {
 254                 .msg            = MAILBOX_MESSAGE(2),
 255                 .fifo_stat      = MAILBOX_FIFOSTATUS(2),
 256         },
 257         .rx_fifo = {
 258                 .msg            = MAILBOX_MESSAGE(3),
 259                 .msg_stat       = MAILBOX_MSGSTATUS(3),
 260         },
 261         .irqenable      = MAILBOX_IRQENABLE(3),
 262         .irqstatus      = MAILBOX_IRQSTATUS(3),
 263         .notfull_bit    = MAILBOX_IRQ_NOTFULL(2),
 264         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(3),
 265 };
 266
 267 static struct omap_mbox mbox_iva_info = {
 268         .name   = "iva",
 269         .ops    = &omap2_mbox_ops,
 270         .priv   = &omap2_mbox_iva_priv,
 271 };
 272 #endif
 273
 274 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 275 {
 276         struct resource *res;
 277         int ret;
 278
 279         /* MBOX base */
 280         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 281         if (unlikely(!res)) {
 282                 dev_err(&pdev->dev, "invalid mem resource\n");
 283                 return -ENODEV;
 284         }
 285         mbox_base = ioremap(res->start, res->end - res->start);
 286         if (!mbox_base)
 287                 return -ENOMEM;
 288
 289         /* DSP or IVA2 IRQ */
 290         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 291         if (unlikely(!res)) {
 292                 dev_err(&pdev->dev, "invalid irq resource\n");
 293                 ret = -ENODEV;
 294                 goto err_dsp;
 295         }
 296         mbox_dsp_info.irq = res->start;
 297
 298         ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
 299         if (ret)
 300                 goto err_dsp;
 301
 302 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
 303         if (cpu_is_omap2420()) {
 304                 /* IVA IRQ */
 305                 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 306                 if (unlikely(!res)) {
 307                         dev_err(&pdev->dev, "invalid irq resource\n");
 308                         ret = -ENODEV;
 309                         goto err_iva1;
 310                 }
 311                 mbox_iva_info.irq = res->start;
 312                 ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
 313                 if (ret)
 314                         goto err_iva1;
 315         }
 316 #endif
 317         return 0;
 318
 319 err_iva1:
 320         omap_mbox_unregister(&mbox_dsp_info);
 321 err_dsp:
 322         iounmap(mbox_base);
 323         return ret;
 324 }
 325
 326 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
 327 {
 328 #if defined(CONFIG_ARCH_OMAP2420)
 329         omap_mbox_unregister(&mbox_iva_info);
 330 #endif
 331         omap_mbox_unregister(&mbox_dsp_info);
 332         iounmap(mbox_base);
 333         return 0;
 334 }
 335
 336 static struct platform_driver omap2_mbox_driver = {
 337         .probe = omap2_mbox_probe,
 338         .remove = __devexit_p(omap2_mbox_remove),
 339         .driver = {
 340                 .name = DRV_NAME,
 341         },
 342 };
 343
 344 static int __init omap2_mbox_init(void)
 345 {
 346         return platform_driver_register(&omap2_mbox_driver);
 347 }
 348
 349 static void __exit omap2_mbox_exit(void)
 350 {
 351         platform_driver_unregister(&omap2_mbox_driver);
 352 }
 353
 354 module_init(omap2_mbox_init);
 355 module_exit(omap2_mbox_exit);
 356
 357 MODULE_LICENSE("GPL v2");
 358 MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
 359 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
 360 MODULE_ALIAS("platform:"DRV_NAME);