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Group and resource assignments for TWL4030
[linux-ginger.git] / arch / arm / mach-omap2 / serial.c
blobfd5b9f83e0bc51ad361c2eaaf11a7b016ee65f7c
1 /*
2 * arch/arm/mach-omap2/serial.c
3 *
4 * OMAP2 serial support.
5 *
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * Major rework for PM support by Kevin Hilman
10 *
11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23
24 #include <mach/common.h>
25 #include <mach/board.h>
26 #include <mach/clock.h>
27 #include <mach/control.h>
28
29 #include "prm.h"
30 #include "pm.h"
31 #include "prm-regbits-34xx.h"
32
33 #define DEFAULT_TIMEOUT (5 * HZ)
34
35 struct omap_uart_state {
36 int num;
37 int can_sleep;
38 struct timer_list timer;
39 u32 timeout;
40
41 void __iomem *wk_st;
42 void __iomem *wk_en;
43 u32 wk_mask;
44 u32 padconf;
45
46 struct clk *ick;
47 struct clk *fck;
48 int clocked;
49
50 struct plat_serial8250_port *p;
51 struct list_head node;
52
53 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
54 int context_valid;
55
56 /* Registers to be saved/restored for OFF-mode */
57 u16 dll;
58 u16 dlh;
59 u16 ier;
60 u16 sysc;
61 u16 scr;
62 u16 wer;
63 #endif
64 };
65
66 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
67 static LIST_HEAD(uart_list);
68
69 static struct plat_serial8250_port serial_platform_data[] = {
70 {
71 .membase = IO_ADDRESS(OMAP_UART1_BASE),
72 .mapbase = OMAP_UART1_BASE,
73 .irq = 72,
74 .flags = UPF_BOOT_AUTOCONF,
75 .iotype = UPIO_MEM,
76 .regshift = 2,
77 .uartclk = OMAP24XX_BASE_BAUD * 16,
78 }, {
79 .membase = IO_ADDRESS(OMAP_UART2_BASE),
80 .mapbase = OMAP_UART2_BASE,
81 .irq = 73,
82 .flags = UPF_BOOT_AUTOCONF,
83 .iotype = UPIO_MEM,
84 .regshift = 2,
85 .uartclk = OMAP24XX_BASE_BAUD * 16,
86 }, {
87 .membase = IO_ADDRESS(OMAP_UART3_BASE),
88 .mapbase = OMAP_UART3_BASE,
89 .irq = 74,
90 .flags = UPF_BOOT_AUTOCONF,
91 .iotype = UPIO_MEM,
92 .regshift = 2,
93 .uartclk = OMAP24XX_BASE_BAUD * 16,
94 }, {
95 .flags = 0
96 }
97 };
98
99 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
100 int offset)
101 {
102 offset <<= up->regshift;
103 return (unsigned int)__raw_readb(up->membase + offset);
104 }
105
106 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
107 int value)
108 {
109 offset <<= p->regshift;
110 __raw_writeb(value, p->membase + offset);
111 }
112
113 /*
114 * Internal UARTs need to be initialized for the 8250 autoconfig to work
115 * properly. Note that the TX watermark initialization may not be needed
116 * once the 8250.c watermark handling code is merged.
117 */
118 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
119 {
120 struct plat_serial8250_port *p = uart->p;
121
122 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
123 serial_write_reg(p, UART_OMAP_SCR, 0x08);
124 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
125 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
126 }
127
128 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
129 {
130 if (uart->clocked)
131 return;
132
133 clk_enable(uart->ick);
134 clk_enable(uart->fck);
135 uart->clocked = 1;
136 }
137
138 #ifdef CONFIG_PM
139 #ifdef CONFIG_ARCH_OMAP3
140
141 static int enable_off_mode; /* to be removed by full off-mode patches */
142
143 static void omap_uart_save_context(struct omap_uart_state *uart)
144 {
145 u16 lcr = 0;
146 struct plat_serial8250_port *p = uart->p;
147
148 if (!enable_off_mode)
149 return;
150
151 lcr = serial_read_reg(p, UART_LCR);
152 serial_write_reg(p, UART_LCR, 0xBF);
153 uart->dll = serial_read_reg(p, UART_DLL);
154 uart->dlh = serial_read_reg(p, UART_DLM);
155 serial_write_reg(p, UART_LCR, lcr);
156 uart->ier = serial_read_reg(p, UART_IER);
157 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
158 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
159 uart->wer = serial_read_reg(p, UART_OMAP_WER);
160
161 uart->context_valid = 1;
162 }
163
164 static void omap_uart_restore_context(struct omap_uart_state *uart)
165 {
166 u16 efr = 0;
167 struct plat_serial8250_port *p = uart->p;
168
169 if (!enable_off_mode)
170 return;
171
172 if (!uart->context_valid)
173 return;
174
175 uart->context_valid = 0;
176
177 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
178 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
179 efr = serial_read_reg(p, UART_EFR);
180 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
181 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
182 serial_write_reg(p, UART_IER, 0x0);
183 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
184 serial_write_reg(p, UART_DLL, uart->dll);
185 serial_write_reg(p, UART_DLM, uart->dlh);
186 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
187 serial_write_reg(p, UART_IER, uart->ier);
188 serial_write_reg(p, UART_FCR, 0xA1);
189 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
190 serial_write_reg(p, UART_EFR, efr);
191 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
192 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
193 serial_write_reg(p, UART_OMAP_WER, uart->wer);
194 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
195 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
196 }
197 #else
198 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
199 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
200 #endif /* CONFIG_ARCH_OMAP3 */
201
202 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
203 int enable)
204 {
205 struct plat_serial8250_port *p = uart->p;
206 u16 sysc;
207
208 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
209 if (enable)
210 sysc |= 0x2 << 3;
211 else
212 sysc |= 0x1 << 3;
213
214 serial_write_reg(p, UART_OMAP_SYSC, sysc);
215 }
216
217 static inline void omap_uart_restore(struct omap_uart_state *uart)
218 {
219 omap_uart_enable_clocks(uart);
220 omap_uart_restore_context(uart);
221 }
222
223 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
224 {
225 if (!uart->clocked)
226 return;
227
228 omap_uart_save_context(uart);
229 uart->clocked = 0;
230 clk_disable(uart->ick);
231 clk_disable(uart->fck);
232 }
233
234 static void omap_uart_block_sleep(struct omap_uart_state *uart)
235 {
236 omap_uart_restore(uart);
237
238 omap_uart_smart_idle_enable(uart, 0);
239 uart->can_sleep = 0;
240 mod_timer(&uart->timer, jiffies + uart->timeout);
241 }
242
243 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
244 {
245 if (!uart->clocked)
246 return;
247
248 omap_uart_smart_idle_enable(uart, 1);
249 uart->can_sleep = 1;
250 del_timer(&uart->timer);
251 }
252
253 static void omap_uart_idle_timer(unsigned long data)
254 {
255 struct omap_uart_state *uart = (struct omap_uart_state *)data;
256
257 omap_uart_allow_sleep(uart);
258 }
259
260 void omap_uart_prepare_idle(int num)
261 {
262 struct omap_uart_state *uart;
263
264 list_for_each_entry(uart, &uart_list, node) {
265 if (!clocks_off_while_idle)
266 continue;
267
268 if (num == uart->num && uart->can_sleep) {
269 omap_uart_disable_clocks(uart);
270 return;
271 }
272 }
273 }
274
275 void omap_uart_resume_idle(int num)
276 {
277 struct omap_uart_state *uart;
278
279 list_for_each_entry(uart, &uart_list, node) {
280 if (num == uart->num) {
281 omap_uart_restore(uart);
282
283 /* Check for IO pad wakeup */
284 if (cpu_is_omap34xx() && uart->padconf) {
285 u16 p = omap_ctrl_readw(uart->padconf);
286
287 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
288 omap_uart_block_sleep(uart);
289 }
290
291 /* Check for normal UART wakeup */
292 if (__raw_readl(uart->wk_st) & uart->wk_mask)
293 omap_uart_block_sleep(uart);
294
295 return;
296 }
297 }
298 }
299
300 void omap_uart_prepare_suspend(void)
301 {
302 struct omap_uart_state *uart;
303
304 list_for_each_entry(uart, &uart_list, node) {
305 omap_uart_allow_sleep(uart);
306 }
307 }
308
309 int omap_uart_can_sleep(void)
310 {
311 struct omap_uart_state *uart;
312 int can_sleep = 1;
313
314 list_for_each_entry(uart, &uart_list, node) {
315 if (!uart->clocked)
316 continue;
317
318 if (!uart->can_sleep) {
319 can_sleep = 0;
320 continue;
321 }
322
323 /* This UART can now safely sleep. */
324 omap_uart_allow_sleep(uart);
325 }
326
327 return can_sleep;
328 }
329
330 /**
331 * omap_uart_interrupt()
332 *
333 * This handler is used only to detect that *any* UART interrupt has
334 * occurred. It does _nothing_ to handle the interrupt. Rather,
335 * any UART interrupt will trigger the inactivity timer so the
336 * UART will not idle or sleep for its timeout period.
337 *
338 **/
339 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
340 {
341 struct omap_uart_state *uart = dev_id;
342
343 omap_uart_block_sleep(uart);
344
345 return IRQ_NONE;
346 }
347
348 static u32 sleep_timeout = DEFAULT_TIMEOUT;
349
350 static void omap_uart_idle_init(struct omap_uart_state *uart)
351 {
352 u32 v;
353 struct plat_serial8250_port *p = uart->p;
354 int ret;
355
356 uart->can_sleep = 0;
357 uart->timeout = sleep_timeout;
358 setup_timer(&uart->timer, omap_uart_idle_timer,
359 (unsigned long) uart);
360 mod_timer(&uart->timer, jiffies + uart->timeout);
361 omap_uart_smart_idle_enable(uart, 0);
362
363 if (cpu_is_omap34xx()) {
364 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
365 u32 wk_mask = 0;
366 u32 padconf = 0;
367
368 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
369 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
370 switch (uart->num) {
371 case 0:
372 wk_mask = OMAP3430_ST_UART1_MASK;
373 padconf = 0x182;
374 break;
375 case 1:
376 wk_mask = OMAP3430_ST_UART2_MASK;
377 padconf = 0x17a;
378 break;
379 case 2:
380 wk_mask = OMAP3430_ST_UART3_MASK;
381 padconf = 0x19e;
382 break;
383 }
384 uart->wk_mask = wk_mask;
385 uart->padconf = padconf;
386 } else if (cpu_is_omap24xx()) {
387 u32 wk_mask = 0;
388
389 if (cpu_is_omap2430()) {
390 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
391 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
392 } else if (cpu_is_omap2420()) {
393 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
394 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
395 }
396 switch (uart->num) {
397 case 0:
398 wk_mask = OMAP24XX_ST_UART1_MASK;
399 break;
400 case 1:
401 wk_mask = OMAP24XX_ST_UART2_MASK;
402 break;
403 case 2:
404 wk_mask = OMAP24XX_ST_UART3_MASK;
405 break;
406 }
407 uart->wk_mask = wk_mask;
408 } else {
409 uart->wk_en = 0;
410 uart->wk_st = 0;
411 uart->wk_mask = 0;
412 uart->padconf = 0;
413 }
414
415 /* Set wake-enable bit */
416 if (uart->wk_en && uart->wk_mask) {
417 v = __raw_readl(uart->wk_en);
418 v |= uart->wk_mask;
419 __raw_writel(v, uart->wk_en);
420 }
421
422 /* Ensure IOPAD wake-enables are set */
423 if (cpu_is_omap34xx() && uart->padconf) {
424 u16 v;
425
426 v = omap_ctrl_readw(uart->padconf);
427 v |= OMAP3_PADCONF_WAKEUPENABLE0;
428 omap_ctrl_writew(v, uart->padconf);
429 }
430
431 p->flags |= UPF_SHARE_IRQ;
432 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
433 "serial idle", (void *)uart);
434 WARN_ON(ret);
435 }
436
437 static ssize_t sleep_timeout_show(struct kobject *kobj,
438 struct kobj_attribute *attr,
439 char *buf)
440 {
441 return sprintf(buf, "%u\n", sleep_timeout / HZ);
442 }
443
444 static ssize_t sleep_timeout_store(struct kobject *kobj,
445 struct kobj_attribute *attr,
446 const char *buf, size_t n)
447 {
448 struct omap_uart_state *uart;
449 unsigned int value;
450
451 if (sscanf(buf, "%u", &value) != 1) {
452 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
453 return -EINVAL;
454 }
455 sleep_timeout = value * HZ;
456 list_for_each_entry(uart, &uart_list, node)
457 uart->timeout = sleep_timeout;
458 return n;
459 }
460
461 static struct kobj_attribute sleep_timeout_attr =
462 __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
463
464 #else
465 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
466 #endif /* CONFIG_PM */
467
468 void __init omap_serial_init(void)
469 {
470 int i;
471 const struct omap_uart_config *info;
472 char name[16];
473
474 /*
475 * Make sure the serial ports are muxed on at this point.
476 * You have to mux them off in device drivers later on
477 * if not needed.
478 */
479
480 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
481
482 if (info == NULL)
483 return;
484
485 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
486 struct plat_serial8250_port *p = serial_platform_data + i;
487 struct omap_uart_state *uart = &omap_uart[i];
488
489 if (!(info->enabled_uarts & (1 << i))) {
490 p->membase = NULL;
491 p->mapbase = 0;
492 continue;
493 }
494
495 sprintf(name, "uart%d_ick", i+1);
496 uart->ick = clk_get(NULL, name);
497 if (IS_ERR(uart->ick)) {
498 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
499 uart->ick = NULL;
500 }
501
502 sprintf(name, "uart%d_fck", i+1);
503 uart->fck = clk_get(NULL, name);
504 if (IS_ERR(uart->fck)) {
505 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
506 uart->fck = NULL;
507 }
508
509 if (!uart->ick || !uart->fck)
510 continue;
511
512 uart->num = i;
513 p->private_data = uart;
514 uart->p = p;
515 list_add(&uart->node, &uart_list);
516
517 omap_uart_enable_clocks(uart);
518 omap_uart_reset(uart);
519 omap_uart_idle_init(uart);
520 }
521 }
522
523 static struct platform_device serial_device = {
524 .name = "serial8250",
525 .id = PLAT8250_DEV_PLATFORM,
526 .dev = {
527 .platform_data = serial_platform_data,
528 },
529 };
530
531 static int __init omap_init(void)
532 {
533 int ret;
534
535 ret = platform_device_register(&serial_device);
536
537 #ifdef CONFIG_PM
538 if (!ret)
539 ret = sysfs_create_file(&serial_device.dev.kobj,
540 &sleep_timeout_attr.attr);
541 #endif
542 return ret;
543 }
544 arch_initcall(omap_init);
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