arch/arm/mach-omap2/timer-gp.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer-gp.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Update to use new clocksource/clockevent layers
   7  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *
  10  * Original driver:
  11  * Copyright (C) 2005 Nokia Corporation
  12  * Author: Paul Mundt <paul.mundt@nokia.com>
  13  *         Juha Yrjölä <juha.yrjola@nokia.com>
  14  * OMAP Dual-mode timer framework support by Timo Teras
  15  *
  16  * Some parts based off of TI's 24xx code:
  17  *
  18  *   Copyright (C) 2004 Texas Instruments, Inc.
  19  *
  20  * Roughly modelled after the OMAP1 MPU timer code.
  21  *
  22  * This file is subject to the terms and conditions of the GNU General Public
  23  * License. See the file "COPYING" in the main directory of this archive
  24  * for more details.
  25  */
  26 #include <linux/init.h>
  27 #include <linux/time.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/err.h>
  30 #include <linux/clk.h>
  31 #include <linux/delay.h>
  32 #include <linux/irq.h>
  33 #include <linux/clocksource.h>
  34 #include <linux/clockchips.h>
  35
  36 #include <asm/mach/time.h>
  37 #include <mach/dmtimer.h>
  38
  39 static struct omap_dm_timer *gptimer;
  40 static struct clock_event_device clockevent_gpt;
  41
  42 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  43 {
  44         struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
  45         struct clock_event_device *evt = &clockevent_gpt;
  46
  47         omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
  48
  49         evt->event_handler(evt);
  50         return IRQ_HANDLED;
  51 }
  52
  53 static struct irqaction omap2_gp_timer_irq = {
  54         .name           = "gp timer",
  55         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  56         .handler        = omap2_gp_timer_interrupt,
  57 };
  58
  59 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  60                                          struct clock_event_device *evt)
  61 {
  62         omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
  63
  64         return 0;
  65 }
  66
  67 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
  68                                     struct clock_event_device *evt)
  69 {
  70         u32 period;
  71
  72         omap_dm_timer_stop(gptimer);
  73
  74         switch (mode) {
  75         case CLOCK_EVT_MODE_PERIODIC:
  76                 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
  77                 period -= 1;
  78
  79                 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
  80                 break;
  81         case CLOCK_EVT_MODE_ONESHOT:
  82                 break;
  83         case CLOCK_EVT_MODE_UNUSED:
  84         case CLOCK_EVT_MODE_SHUTDOWN:
  85         case CLOCK_EVT_MODE_RESUME:
  86                 break;
  87         }
  88 }
  89
  90 static struct clock_event_device clockevent_gpt = {
  91         .name           = "gp timer",
  92         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  93         .shift          = 32,
  94         .set_next_event = omap2_gp_timer_set_next_event,
  95         .set_mode       = omap2_gp_timer_set_mode,
  96 };
  97
  98 static void __init omap2_gp_clockevent_init(void)
  99 {
 100         u32 tick_rate;
 101
 102         gptimer = omap_dm_timer_request_specific(CONFIG_OMAP_TICK_GPTIMER);
 103         BUG_ON(gptimer == NULL);
 104
 105 #if defined(CONFIG_OMAP_32K_TIMER)
 106         omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
 107 #else
 108         omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
 109 #endif
 110         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
 111
 112         pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
 113                 CONFIG_OMAP_TICK_GPTIMER, tick_rate);
 114
 115         omap2_gp_timer_irq.dev_id = (void *)gptimer;
 116         setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
 117         omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
 118
 119         clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
 120                                      clockevent_gpt.shift);
 121         clockevent_gpt.max_delta_ns =
 122                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 123         clockevent_gpt.min_delta_ns =
 124                 clockevent_delta2ns(3, &clockevent_gpt);
 125                 /* Timer internal resynch latency. */
 126
 127         clockevent_gpt.cpumask = cpumask_of(0);
 128         clockevents_register_device(&clockevent_gpt);
 129 }
 130
 131 #ifdef CONFIG_OMAP_32K_TIMER
 132 /*
 133  * When 32k-timer is enabled, don't use GPTimer for clocksource
 134  * instead, just leave default clocksource which uses the 32k
 135  * sync counter.  See clocksource setup in see plat-omap/common.c.
 136  */
 137
 138 static inline void __init omap2_gp_clocksource_init(void) {}
 139 #else
 140 /*
 141  * clocksource
 142  */
 143 static struct omap_dm_timer *gpt_clocksource;
 144 static cycle_t clocksource_read_cycles(void)
 145 {
 146         return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
 147 }
 148
 149 static struct clocksource clocksource_gpt = {
 150         .name           = "gp timer",
 151         .rating         = 300,
 152         .read           = clocksource_read_cycles,
 153         .mask           = CLOCKSOURCE_MASK(32),
 154         .shift          = 24,
 155         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 156 };
 157
 158 /* Setup free-running counter for clocksource */
 159 static void __init omap2_gp_clocksource_init(void)
 160 {
 161         static struct omap_dm_timer *gpt;
 162         u32 tick_rate, tick_period;
 163         static char err1[] __initdata = KERN_ERR
 164                 "%s: failed to request dm-timer\n";
 165         static char err2[] __initdata = KERN_ERR
 166                 "%s: can't register clocksource!\n";
 167
 168         gpt = omap_dm_timer_request();
 169         if (!gpt)
 170                 printk(err1, clocksource_gpt.name);
 171         gpt_clocksource = gpt;
 172
 173         omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
 174         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
 175         tick_period = (tick_rate / HZ) - 1;
 176
 177         omap_dm_timer_set_load_start(gpt, 1, 0);
 178
 179         clocksource_gpt.mult =
 180                 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
 181         if (clocksource_register(&clocksource_gpt))
 182                 printk(err2, clocksource_gpt.name);
 183 }
 184 #endif
 185
 186 static void __init omap2_gp_timer_init(void)
 187 {
 188         omap_dm_timer_init();
 189
 190         omap2_gp_clockevent_init();
 191         omap2_gp_clocksource_init();
 192 }
 193
 194 struct sys_timer omap_timer = {
 195         .init   = omap2_gp_timer_init,
 196 };