arch/arm/plat-omap/include/plat/control.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/control.h
   3  *
   4  * OMAP2/3/4 System Control Module definitions
   5  *
   6  * Copyright (C) 2007-2009 Texas Instruments, Inc.
   7  * Copyright (C) 2007-2008 Nokia Corporation
   8  *
   9  * Written by Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation.
  14  */
  15
  16 #ifndef __ASM_ARCH_CONTROL_H
  17 #define __ASM_ARCH_CONTROL_H
  18
  19 #include <mach/io.h>
  20
  21 #ifndef __ASSEMBLY__
  22 #define OMAP242X_CTRL_REGADDR(reg)                                      \
  23                 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
  24 #define OMAP243X_CTRL_REGADDR(reg)                                      \
  25                 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
  26 #define OMAP343X_CTRL_REGADDR(reg)                                      \
  27                 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
  28 #else
  29 #define OMAP242X_CTRL_REGADDR(reg)                                      \
  30                 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
  31 #define OMAP243X_CTRL_REGADDR(reg)                                      \
  32                 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
  33 #define OMAP343X_CTRL_REGADDR(reg)                                      \
  34                 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
  35 #endif /* __ASSEMBLY__ */
  36
  37 /*
  38  * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
  39  * OMAP24XX and OMAP34XX.
  40  */
  41
  42 /* Control submodule offsets */
  43
  44 #define OMAP2_CONTROL_INTERFACE         0x000
  45 #define OMAP2_CONTROL_PADCONFS          0x030
  46 #define OMAP2_CONTROL_GENERAL           0x270
  47 #define OMAP343X_CONTROL_MEM_WKUP       0x600
  48 #define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
  49 #define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
  50
  51 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
  52
  53 #define OMAP2_CONTROL_SYSCONFIG         (OMAP2_CONTROL_INTERFACE + 0x10)
  54
  55 /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
  56 #define OMAP2_CONTROL_DEVCONF0          (OMAP2_CONTROL_GENERAL + 0x0004)
  57 #define OMAP2_CONTROL_MSUSPENDMUX_0     (OMAP2_CONTROL_GENERAL + 0x0020)
  58 #define OMAP2_CONTROL_MSUSPENDMUX_1     (OMAP2_CONTROL_GENERAL + 0x0024)
  59 #define OMAP2_CONTROL_MSUSPENDMUX_2     (OMAP2_CONTROL_GENERAL + 0x0028)
  60 #define OMAP2_CONTROL_MSUSPENDMUX_3     (OMAP2_CONTROL_GENERAL + 0x002c)
  61 #define OMAP2_CONTROL_MSUSPENDMUX_4     (OMAP2_CONTROL_GENERAL + 0x0030)
  62 #define OMAP2_CONTROL_MSUSPENDMUX_5     (OMAP2_CONTROL_GENERAL + 0x0034)
  63 #define OMAP2_CONTROL_SEC_CTRL          (OMAP2_CONTROL_GENERAL + 0x0040)
  64 #define OMAP2_CONTROL_RPUB_KEY_H_0      (OMAP2_CONTROL_GENERAL + 0x0090)
  65 #define OMAP2_CONTROL_RPUB_KEY_H_1      (OMAP2_CONTROL_GENERAL + 0x0094)
  66 #define OMAP2_CONTROL_RPUB_KEY_H_2      (OMAP2_CONTROL_GENERAL + 0x0098)
  67 #define OMAP2_CONTROL_RPUB_KEY_H_3      (OMAP2_CONTROL_GENERAL + 0x009c)
  68
  69 /* 242x-only CONTROL_GENERAL register offsets */
  70 #define OMAP242X_CONTROL_DEVCONF        OMAP2_CONTROL_DEVCONF0 /* match TRM */
  71 #define OMAP242X_CONTROL_OCM_RAM_PERM   (OMAP2_CONTROL_GENERAL + 0x0068)
  72
  73 /* 243x-only CONTROL_GENERAL register offsets */
  74 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
  75 #define OMAP243X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0078)
  76 #define OMAP243X_CONTROL_CSIRXFE        (OMAP2_CONTROL_GENERAL + 0x007c)
  77 #define OMAP243X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
  78 #define OMAP243X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
  79 #define OMAP243X_CONTROL_IVA2_GEMCFG    (OMAP2_CONTROL_GENERAL + 0x0198)
  80 #define OMAP243X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x0230)
  81
  82 /* 24xx-only CONTROL_GENERAL register offsets */
  83 #define OMAP24XX_CONTROL_DEBOBS         (OMAP2_CONTROL_GENERAL + 0x0000)
  84 #define OMAP24XX_CONTROL_EMU_SUPPORT    (OMAP2_CONTROL_GENERAL + 0x0008)
  85 #define OMAP24XX_CONTROL_SEC_TEST       (OMAP2_CONTROL_GENERAL + 0x0044)
  86 #define OMAP24XX_CONTROL_PSA_CTRL       (OMAP2_CONTROL_GENERAL + 0x0048)
  87 #define OMAP24XX_CONTROL_PSA_CMD        (OMAP2_CONTROL_GENERAL + 0x004c)
  88 #define OMAP24XX_CONTROL_PSA_VALUE      (OMAP2_CONTROL_GENERAL + 0x0050)
  89 #define OMAP24XX_CONTROL_SEC_EMU        (OMAP2_CONTROL_GENERAL + 0x0060)
  90 #define OMAP24XX_CONTROL_SEC_TAP        (OMAP2_CONTROL_GENERAL + 0x0064)
  91 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD        (OMAP2_CONTROL_GENERAL + 0x006c)
  92 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
  93 #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074)
  94 #define OMAP24XX_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0080)
  95 #define OMAP24XX_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0084)
  96 #define OMAP24XX_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0088)
  97 #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
  98 #define OMAP24XX_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a0)
  99 #define OMAP24XX_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00a4)
 100 #define OMAP24XX_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00a8)
 101 #define OMAP24XX_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00ac)
 102 #define OMAP24XX_CONTROL_CUST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00b0)
 103 #define OMAP24XX_CONTROL_CUST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00b4)
 104 #define OMAP24XX_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c0)
 105 #define OMAP24XX_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00c4)
 106 #define OMAP24XX_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00c8)
 107 #define OMAP24XX_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00cc)
 108 #define OMAP24XX_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d0)
 109 #define OMAP24XX_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00d4)
 110 #define OMAP24XX_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00d8)
 111 #define OMAP24XX_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00dc)
 112 #define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
 113 #define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
 114
 115 #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
 116
 117 /* 34xx-only CONTROL_GENERAL register offsets */
 118 #define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
 119 #define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
 120 #define OMAP343X_CONTROL_MEM_DFTRW1     (OMAP2_CONTROL_GENERAL + 0x000c)
 121 #define OMAP343X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0068)
 122 #define OMAP343X_CONTROL_CSIRXFE                (OMAP2_CONTROL_GENERAL + 0x006c)
 123 #define OMAP343X_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0070)
 124 #define OMAP343X_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0074)
 125 #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG   (OMAP2_CONTROL_GENERAL + 0x0078)
 126 #define OMAP343X_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0080)
 127 #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
 128 #define OMAP343X_CONTROL_RPUB_KEY_H_4   (OMAP2_CONTROL_GENERAL + 0x00a0)
 129 #define OMAP343X_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a8)
 130 #define OMAP343X_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00ac)
 131 #define OMAP343X_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00b0)
 132 #define OMAP343X_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00b4)
 133 #define OMAP343X_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c8)
 134 #define OMAP343X_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00cc)
 135 #define OMAP343X_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00d0)
 136 #define OMAP343X_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00d4)
 137 #define OMAP343X_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d8)
 138 #define OMAP343X_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00dc)
 139 #define OMAP343X_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00e0)
 140 #define OMAP343X_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00e4)
 141 #define OMAP343X_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e8)
 142 #define OMAP343X_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00ec)
 143 #define OMAP343X_CONTROL_TEST_KEY_10    (OMAP2_CONTROL_GENERAL + 0x00f0)
 144 #define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
 145 #define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
 146 #define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
 147 #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
 148 #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
 149 #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
 150 #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
 151 #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
 152 #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
 153 #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
 154 #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
 155 #define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
 156 #define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
 157 #define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
 158 #define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
 159                                         + ((i) >> 1) * 4 + (!(i) & 1) * 2)
 160 #define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
 161 #define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
 162 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
 163 #define OMAP343X_CONTROL_CORE_DPLL_SPREADING    (OMAP2_CONTROL_GENERAL + 0x01E4)
 164 #define OMAP343X_CONTROL_PER_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E8)
 165 #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
 166 #define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02B0)
 167 #define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02B4)
 168 #define OMAP343X_CONTROL_SRAMLDO4       (OMAP2_CONTROL_GENERAL + 0x02B8)
 169 #define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
 170 #define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
 171
 172
 173 /* 34xx PADCONF register offsets */
 174 #define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
 175                                                 (i)*2)
 176 #define OMAP343X_PADCONF_ETK_CLK        OMAP343X_PADCONF_ETK(0)
 177 #define OMAP343X_PADCONF_ETK_CTL        OMAP343X_PADCONF_ETK(1)
 178 #define OMAP343X_PADCONF_ETK_D0         OMAP343X_PADCONF_ETK(2)
 179 #define OMAP343X_PADCONF_ETK_D1         OMAP343X_PADCONF_ETK(3)
 180 #define OMAP343X_PADCONF_ETK_D2         OMAP343X_PADCONF_ETK(4)
 181 #define OMAP343X_PADCONF_ETK_D3         OMAP343X_PADCONF_ETK(5)
 182 #define OMAP343X_PADCONF_ETK_D4         OMAP343X_PADCONF_ETK(6)
 183 #define OMAP343X_PADCONF_ETK_D5         OMAP343X_PADCONF_ETK(7)
 184 #define OMAP343X_PADCONF_ETK_D6         OMAP343X_PADCONF_ETK(8)
 185 #define OMAP343X_PADCONF_ETK_D7         OMAP343X_PADCONF_ETK(9)
 186 #define OMAP343X_PADCONF_ETK_D8         OMAP343X_PADCONF_ETK(10)
 187 #define OMAP343X_PADCONF_ETK_D9         OMAP343X_PADCONF_ETK(11)
 188 #define OMAP343X_PADCONF_ETK_D10        OMAP343X_PADCONF_ETK(12)
 189 #define OMAP343X_PADCONF_ETK_D11        OMAP343X_PADCONF_ETK(13)
 190 #define OMAP343X_PADCONF_ETK_D12        OMAP343X_PADCONF_ETK(14)
 191 #define OMAP343X_PADCONF_ETK_D13        OMAP343X_PADCONF_ETK(15)
 192 #define OMAP343X_PADCONF_ETK_D14        OMAP343X_PADCONF_ETK(16)
 193 #define OMAP343X_PADCONF_ETK_D15        OMAP343X_PADCONF_ETK(17)
 194
 195 /* 34xx GENERAL_WKUP regist offsets */
 196 #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
 197                                                 0x008 + (i))
 198 #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
 199 #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
 200 #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
 201 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
 202 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 203
 204 /* 34xx D2D idle-related pins, handled by PM core */
 205 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 206 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 207
 208 /*
 209  * REVISIT: This list of registers is not comprehensive - there are more
 210  * that should be added.
 211  */
 212
 213 /*
 214  * Control module register bit defines - these should eventually go into
 215  * their own regbits file.  Some of these will be complicated, depending
 216  * on the device type (general-purpose, emulator, test, secure, bad, other)
 217  * and the security mode (secure, non-secure, don't care)
 218  */
 219 /* CONTROL_DEVCONF0 bits */
 220 #define OMAP2_MMCSDIO1ADPCLKISEL        (1 << 24) /* MMC1 loop back clock */
 221 #define OMAP24XX_USBSTANDBYCTRL         (1 << 15)
 222 #define OMAP2_MCBSP2_CLKS_MASK          (1 << 6)
 223 #define OMAP2_MCBSP1_CLKS_MASK          (1 << 2)
 224
 225 /* CONTROL_DEVCONF1 bits */
 226 #define OMAP243X_MMC1_ACTIVE_OVERWRITE  (1 << 31)
 227 #define OMAP2_MMCSDIO2ADPCLKISEL        (1 << 6) /* MMC2 loop back clock */
 228 #define OMAP2_MCBSP5_CLKS_MASK          (1 << 4) /* > 242x */
 229 #define OMAP2_MCBSP4_CLKS_MASK          (1 << 2) /* > 242x */
 230 #define OMAP2_MCBSP3_CLKS_MASK          (1 << 0) /* > 242x */
 231
 232 /* CONTROL_STATUS bits */
 233 #define OMAP2_DEVICETYPE_MASK           (0x7 << 8)
 234 #define OMAP2_SYSBOOT_5_MASK            (1 << 5)
 235 #define OMAP2_SYSBOOT_4_MASK            (1 << 4)
 236 #define OMAP2_SYSBOOT_3_MASK            (1 << 3)
 237 #define OMAP2_SYSBOOT_2_MASK            (1 << 2)
 238 #define OMAP2_SYSBOOT_1_MASK            (1 << 1)
 239 #define OMAP2_SYSBOOT_0_MASK            (1 << 0)
 240 /* CONTROL_FUSE_SR bits */
 241 #define OMAP343X_SR2_SENNENABLE_MASK    (0x3 << 10)
 242 #define OMAP343X_SR2_SENNENABLE_SHIFT   10
 243 #define OMAP343X_SR2_SENPENABLE_MASK    (0x3 << 8)
 244 #define OMAP343X_SR2_SENPENABLE_SHIFT   8
 245 #define OMAP343X_SR1_SENNENABLE_MASK    (0x3 << 2)
 246 #define OMAP343X_SR1_SENNENABLE_SHIFT   2
 247 #define OMAP343X_SR1_SENPENABLE_MASK    (0x3 << 0)
 248 #define OMAP343X_SR1_SENPENABLE_SHIFT   0
 249
 250 /* CONTROL_PBIAS_LITE bits */
 251 #define OMAP343X_PBIASLITESUPPLY_HIGH1  (1 << 15)
 252 #define OMAP343X_PBIASLITEVMODEERROR1   (1 << 11)
 253 #define OMAP343X_PBIASSPEEDCTRL1        (1 << 10)
 254 #define OMAP343X_PBIASLITEPWRDNZ1       (1 << 9)
 255 #define OMAP343X_PBIASLITEVMODE1        (1 << 8)
 256 #define OMAP343X_PBIASLITESUPPLY_HIGH0  (1 << 7)
 257 #define OMAP343X_PBIASLITEVMODEERROR0   (1 << 3)
 258 #define OMAP2_PBIASSPEEDCTRL0           (1 << 2)
 259 #define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
 260 #define OMAP2_PBIASLITEVMODE0           (1 << 0)
 261
 262 /* CONTROL_IVA2_BOOTMOD bits */
 263 #define OMAP3_IVA2_BOOTMOD_SHIFT        0
 264 #define OMAP3_IVA2_BOOTMOD_MASK         (0xf << 0)
 265 #define OMAP3_IVA2_BOOTMOD_IDLE         (0x1 << 0)
 266
 267 /* CONTROL_PADCONF_X bits */
 268 #define OMAP3_PADCONF_WAKEUPEVENT0      (1 << 15)
 269 #define OMAP3_PADCONF_WAKEUPENABLE0     (1 << 14)
 270
 271 /*
 272  * CONTROL OMAP STATUS register to identify OMAP3 features
 273  */
 274 #define OMAP3_CONTROL_OMAP_STATUS       0x044c
 275
 276 #define OMAP3_SGX_SHIFT                 13
 277 #define OMAP3_SGX_MASK                  (3 << OMAP3_SGX_SHIFT)
 278 #define         FEAT_SGX_FULL           0
 279 #define         FEAT_SGX_HALF           1
 280 #define         FEAT_SGX_NONE           2
 281
 282 #define OMAP3_IVA_SHIFT                 12
 283 #define OMAP3_IVA_MASK                  (1 << OMAP3_SGX_SHIFT)
 284 #define         FEAT_IVA                0
 285 #define         FEAT_IVA_NONE           1
 286
 287 #define OMAP3_L2CACHE_SHIFT             10
 288 #define OMAP3_L2CACHE_MASK              (3 << OMAP3_L2CACHE_SHIFT)
 289 #define         FEAT_L2CACHE_NONE       0
 290 #define         FEAT_L2CACHE_64KB       1
 291 #define         FEAT_L2CACHE_128KB      2
 292 #define         FEAT_L2CACHE_256KB      3
 293
 294 #define OMAP3_ISP_SHIFT                 5
 295 #define OMAP3_ISP_MASK                  (1<< OMAP3_ISP_SHIFT)
 296 #define         FEAT_ISP                0
 297 #define         FEAT_ISP_NONE           1
 298
 299 #define OMAP3_NEON_SHIFT                4
 300 #define OMAP3_NEON_MASK                 (1<< OMAP3_NEON_SHIFT)
 301 #define         FEAT_NEON               0
 302 #define         FEAT_NEON_NONE          1
 303
 304 #define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
 305 #define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
 306 #define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
 307
 308 #ifndef __ASSEMBLY__
 309 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
 310                 defined(CONFIG_ARCH_OMAP4)
 311 extern void __iomem *omap_ctrl_base_get(void);
 312 extern u8 omap_ctrl_readb(u16 offset);
 313 extern u16 omap_ctrl_readw(u16 offset);
 314 extern u32 omap_ctrl_readl(u16 offset);
 315 extern void omap_ctrl_writeb(u8 val, u16 offset);
 316 extern void omap_ctrl_writew(u16 val, u16 offset);
 317 extern void omap_ctrl_writel(u32 val, u16 offset);
 318
 319 extern void omap3_save_scratchpad_contents(void);
 320 extern void omap3_clear_scratchpad_contents(void);
 321 extern u32 *get_restore_pointer(void);
 322 extern u32 *get_es3_restore_pointer(void);
 323 extern u32 omap3_arm_context[128];
 324 extern void omap3_control_save_context(void);
 325 extern void omap3_control_restore_context(void);
 326
 327 #else
 328 #define omap_ctrl_base_get()            0
 329 #define omap_ctrl_readb(x)              0
 330 #define omap_ctrl_readw(x)              0
 331 #define omap_ctrl_readl(x)              0
 332 #define omap_ctrl_writeb(x, y)          WARN_ON(1)
 333 #define omap_ctrl_writew(x, y)          WARN_ON(1)
 334 #define omap_ctrl_writel(x, y)          WARN_ON(1)
 335 #endif
 336 #endif  /* __ASSEMBLY__ */
 337
 338 #endif /* __ASM_ARCH_CONTROL_H */
 339