arch/arm/plat-omap/include/plat/gpmc.h

   1 /*
   2  * General-Purpose Memory Controller for OMAP2
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __OMAP2_GPMC_H
  12 #define __OMAP2_GPMC_H
  13
  14 /* Maximum Number of Chip Selects */
  15 #define GPMC_CS_NUM             8
  16
  17 #define GPMC_CS_CONFIG1         0x00
  18 #define GPMC_CS_CONFIG2         0x04
  19 #define GPMC_CS_CONFIG3         0x08
  20 #define GPMC_CS_CONFIG4         0x0c
  21 #define GPMC_CS_CONFIG5         0x10
  22 #define GPMC_CS_CONFIG6         0x14
  23 #define GPMC_CS_CONFIG7         0x18
  24 #define GPMC_CS_NAND_COMMAND    0x1c
  25 #define GPMC_CS_NAND_ADDRESS    0x20
  26 #define GPMC_CS_NAND_DATA       0x24
  27
  28 #define GPMC_CONFIG             0x50
  29 #define GPMC_STATUS             0x54
  30
  31 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
  32 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
  33 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
  34 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
  35 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
  36 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
  37 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
  38 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
  39 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
  40 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
  41 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
  42 #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
  43 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
  44 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
  45 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
  46 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
  47 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
  48 #define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(1)
  49 #define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
  50 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
  51 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
  52 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
  53 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
  54 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
  55 #define GPMC_CONFIG7_CSVALID            (1 << 6)
  56
  57 /*
  58  * Note that all values in this struct are in nanoseconds, while
  59  * the register values are in gpmc_fck cycles.
  60  */
  61 struct gpmc_timings {
  62         /* Minimum clock period for synchronous mode */
  63         u16 sync_clk;
  64
  65         /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
  66         u16 cs_on;              /* Assertion time */
  67         u16 cs_rd_off;          /* Read deassertion time */
  68         u16 cs_wr_off;          /* Write deassertion time */
  69
  70         /* ADV signal timings corresponding to GPMC_CONFIG3 */
  71         u16 adv_on;             /* Assertion time */
  72         u16 adv_rd_off;         /* Read deassertion time */
  73         u16 adv_wr_off;         /* Write deassertion time */
  74
  75         /* WE signals timings corresponding to GPMC_CONFIG4 */
  76         u16 we_on;              /* WE assertion time */
  77         u16 we_off;             /* WE deassertion time */
  78
  79         /* OE signals timings corresponding to GPMC_CONFIG4 */
  80         u16 oe_on;              /* OE assertion time */
  81         u16 oe_off;             /* OE deassertion time */
  82
  83         /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
  84         u16 page_burst_access;  /* Multiple access word delay */
  85         u16 access;             /* Start-cycle to first data valid delay */
  86         u16 rd_cycle;           /* Total read cycle time */
  87         u16 wr_cycle;           /* Total write cycle time */
  88
  89         /* The following are only on OMAP3430 */
  90         u16 wr_access;          /* WRACCESSTIME */
  91         u16 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
  92 };
  93
  94 extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
  95 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
  96 extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
  97 extern unsigned long gpmc_get_fclk_period(void);
  98
  99 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
 100 extern u32 gpmc_cs_read_reg(int cs, int idx);
 101 extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
 102 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
 103 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 104 extern void gpmc_cs_free(int cs);
 105 extern int gpmc_cs_set_reserved(int cs, int reserved);
 106 extern int gpmc_cs_reserved(int cs);
 107 extern int gpmc_prefetch_enable(int cs, int dma_mode,
 108                                         unsigned int u32_count, int is_write);
 109 extern void gpmc_prefetch_reset(void);
 110 extern int gpmc_prefetch_status(void);
 111 extern void omap3_gpmc_save_context(void);
 112 extern void omap3_gpmc_restore_context(void);
 113 extern void __init gpmc_init(void);
 114
 115 #endif