arch/arm/plat-s3c64xx/irq-eint.c

   1 /* arch/arm/plat-s3c64xx/irq-eint.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX - Interrupt handling for IRQ_EINT(x)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/sysdev.h>
  18 #include <linux/gpio.h>
  19 #include <linux/irq.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/hardware/vic.h>
  23
  24 #include <plat/regs-irqtype.h>
  25 #include <plat/regs-gpio.h>
  26 #include <plat/gpio-cfg.h>
  27
  28 #include <mach/map.h>
  29 #include <plat/cpu.h>
  30 #include <plat/pm.h>
  31
  32 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
  33 #define eint_irq_to_bit(irq)    (1 << eint_offset(irq))
  34
  35 static inline void s3c_irq_eint_mask(unsigned int irq)
  36 {
  37         u32 mask;
  38
  39         mask = __raw_readl(S3C64XX_EINT0MASK);
  40         mask |= eint_irq_to_bit(irq);
  41         __raw_writel(mask, S3C64XX_EINT0MASK);
  42 }
  43
  44 static void s3c_irq_eint_unmask(unsigned int irq)
  45 {
  46         u32 mask;
  47
  48         mask = __raw_readl(S3C64XX_EINT0MASK);
  49         mask &= ~eint_irq_to_bit(irq);
  50         __raw_writel(mask, S3C64XX_EINT0MASK);
  51 }
  52
  53 static inline void s3c_irq_eint_ack(unsigned int irq)
  54 {
  55         __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
  56 }
  57
  58 static void s3c_irq_eint_maskack(unsigned int irq)
  59 {
  60         /* compiler should in-line these */
  61         s3c_irq_eint_mask(irq);
  62         s3c_irq_eint_ack(irq);
  63 }
  64
  65 static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
  66 {
  67         int offs = eint_offset(irq);
  68         int pin;
  69         int shift;
  70         u32 ctrl, mask;
  71         u32 newvalue = 0;
  72         void __iomem *reg;
  73
  74         if (offs > 27)
  75                 return -EINVAL;
  76
  77         if (offs <= 15)
  78                 reg = S3C64XX_EINT0CON0;
  79         else
  80                 reg = S3C64XX_EINT0CON1;
  81
  82         switch (type) {
  83         case IRQ_TYPE_NONE:
  84                 printk(KERN_WARNING "No edge setting!\n");
  85                 break;
  86
  87         case IRQ_TYPE_EDGE_RISING:
  88                 newvalue = S3C2410_EXTINT_RISEEDGE;
  89                 break;
  90
  91         case IRQ_TYPE_EDGE_FALLING:
  92                 newvalue = S3C2410_EXTINT_FALLEDGE;
  93                 break;
  94
  95         case IRQ_TYPE_EDGE_BOTH:
  96                 newvalue = S3C2410_EXTINT_BOTHEDGE;
  97                 break;
  98
  99         case IRQ_TYPE_LEVEL_LOW:
 100                 newvalue = S3C2410_EXTINT_LOWLEV;
 101                 break;
 102
 103         case IRQ_TYPE_LEVEL_HIGH:
 104                 newvalue = S3C2410_EXTINT_HILEV;
 105                 break;
 106
 107         default:
 108                 printk(KERN_ERR "No such irq type %d", type);
 109                 return -1;
 110         }
 111
 112         shift = (offs / 2) * 4;
 113         mask = 0x7 << shift;
 114
 115         ctrl = __raw_readl(reg);
 116         ctrl &= ~mask;
 117         ctrl |= newvalue << shift;
 118         __raw_writel(ctrl, reg);
 119
 120         /* set the GPIO pin appropriately */
 121
 122         if (offs < 23)
 123                 pin = S3C64XX_GPN(offs);
 124         else
 125                 pin = S3C64XX_GPM(offs - 23);
 126
 127         s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
 128
 129         return 0;
 130 }
 131
 132 static struct irq_chip s3c_irq_eint = {
 133         .name           = "s3c-eint",
 134         .mask           = s3c_irq_eint_mask,
 135         .unmask         = s3c_irq_eint_unmask,
 136         .mask_ack       = s3c_irq_eint_maskack,
 137         .ack            = s3c_irq_eint_ack,
 138         .set_type       = s3c_irq_eint_set_type,
 139         .set_wake       = s3c_irqext_wake,
 140 };
 141
 142 /* s3c_irq_demux_eint
 143  *
 144  * This function demuxes the IRQ from the group0 external interrupts,
 145  * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 146  * the specific handlers s3c_irq_demux_eintX_Y.
 147  */
 148 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
 149 {
 150         u32 status = __raw_readl(S3C64XX_EINT0PEND);
 151         u32 mask = __raw_readl(S3C64XX_EINT0MASK);
 152         unsigned int irq;
 153
 154         status &= ~mask;
 155         status >>= start;
 156         status &= (1 << (end - start + 1)) - 1;
 157
 158         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 159                 if (status & 1)
 160                         generic_handle_irq(irq);
 161
 162                 status >>= 1;
 163         }
 164 }
 165
 166 static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 167 {
 168         s3c_irq_demux_eint(0, 3);
 169 }
 170
 171 static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 172 {
 173         s3c_irq_demux_eint(4, 11);
 174 }
 175
 176 static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
 177 {
 178         s3c_irq_demux_eint(12, 19);
 179 }
 180
 181 static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
 182 {
 183         s3c_irq_demux_eint(20, 27);
 184 }
 185
 186 static int __init s3c64xx_init_irq_eint(void)
 187 {
 188         int irq;
 189
 190         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
 191                 set_irq_chip(irq, &s3c_irq_eint);
 192                 set_irq_handler(irq, handle_level_irq);
 193                 set_irq_flags(irq, IRQF_VALID);
 194         }
 195
 196         set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
 197         set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
 198         set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
 199         set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
 200
 201         return 0;
 202 }
 203
 204 arch_initcall(s3c64xx_init_irq_eint);