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OMAP3 SRF: Generic shared resource f/w
[linux-ginger.git] / arch / arm / mach-omap2 / serial.c
blob2e17b57f5b23bb6703a2d621103585af1d8d729b
1 /*
2 * arch/arm/mach-omap2/serial.c
3 *
4 * OMAP2 serial support.
5 *
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * Major rework for PM support by Kevin Hilman
10 *
11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26
27 #include <plat/common.h>
28 #include <plat/board.h>
29 #include <plat/clock.h>
30 #include <plat/control.h>
31
32 #include "prm.h"
33 #include "pm.h"
34 #include "prm-regbits-34xx.h"
35
36 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
37
38 #define DEFAULT_TIMEOUT (5 * HZ)
39
40 struct omap_uart_state {
41 int num;
42 int can_sleep;
43 struct timer_list timer;
44 u32 timeout;
45
46 void __iomem *wk_st;
47 void __iomem *wk_en;
48 u32 wk_mask;
49 u32 padconf;
50
51 struct clk *ick;
52 struct clk *fck;
53 int clocked;
54
55 struct plat_serial8250_port *p;
56 struct list_head node;
57 struct platform_device pdev;
58
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
60 int context_valid;
61
62 /* Registers to be saved/restored for OFF-mode */
63 u16 dll;
64 u16 dlh;
65 u16 ier;
66 u16 sysc;
67 u16 scr;
68 u16 wer;
69 #endif
70 };
71
72 static LIST_HEAD(uart_list);
73
74 static struct plat_serial8250_port serial_platform_data0[] = {
75 {
76 .mapbase = OMAP_UART1_BASE,
77 .irq = 72,
78 .flags = UPF_BOOT_AUTOCONF,
79 .iotype = UPIO_MEM,
80 .regshift = 2,
81 .uartclk = OMAP24XX_BASE_BAUD * 16,
82 }, {
83 .flags = 0
84 }
85 };
86
87 static struct plat_serial8250_port serial_platform_data1[] = {
88 {
89 .mapbase = OMAP_UART2_BASE,
90 .irq = 73,
91 .flags = UPF_BOOT_AUTOCONF,
92 .iotype = UPIO_MEM,
93 .regshift = 2,
94 .uartclk = OMAP24XX_BASE_BAUD * 16,
95 }, {
96 .flags = 0
97 }
98 };
99
100 static struct plat_serial8250_port serial_platform_data2[] = {
101 {
102 .mapbase = OMAP_UART3_BASE,
103 .irq = 74,
104 .flags = UPF_BOOT_AUTOCONF,
105 .iotype = UPIO_MEM,
106 .regshift = 2,
107 .uartclk = OMAP24XX_BASE_BAUD * 16,
108 }, {
109 .flags = 0
110 }
111 };
112
113 #ifdef CONFIG_ARCH_OMAP4
114 static struct plat_serial8250_port serial_platform_data3[] = {
115 {
116 .mapbase = OMAP_UART4_BASE,
117 .irq = 70,
118 .flags = UPF_BOOT_AUTOCONF,
119 .iotype = UPIO_MEM,
120 .regshift = 2,
121 .uartclk = OMAP24XX_BASE_BAUD * 16,
122 }, {
123 .flags = 0
124 }
125 };
126 #endif
127 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
128 int offset)
129 {
130 offset <<= up->regshift;
131 return (unsigned int)__raw_readb(up->membase + offset);
132 }
133
134 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
135 int value)
136 {
137 offset <<= p->regshift;
138 __raw_writeb(value, p->membase + offset);
139 }
140
141 /*
142 * Internal UARTs need to be initialized for the 8250 autoconfig to work
143 * properly. Note that the TX watermark initialization may not be needed
144 * once the 8250.c watermark handling code is merged.
145 */
146 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
147 {
148 struct plat_serial8250_port *p = uart->p;
149
150 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
151 serial_write_reg(p, UART_OMAP_SCR, 0x08);
152 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
153 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
154 }
155
156 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
157
158 static void omap_uart_save_context(struct omap_uart_state *uart)
159 {
160 u16 lcr = 0;
161 struct plat_serial8250_port *p = uart->p;
162
163 if (!enable_off_mode)
164 return;
165
166 lcr = serial_read_reg(p, UART_LCR);
167 serial_write_reg(p, UART_LCR, 0xBF);
168 uart->dll = serial_read_reg(p, UART_DLL);
169 uart->dlh = serial_read_reg(p, UART_DLM);
170 serial_write_reg(p, UART_LCR, lcr);
171 uart->ier = serial_read_reg(p, UART_IER);
172 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
173 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
174 uart->wer = serial_read_reg(p, UART_OMAP_WER);
175
176 uart->context_valid = 1;
177 }
178
179 static void omap_uart_restore_context(struct omap_uart_state *uart)
180 {
181 u16 efr = 0;
182 struct plat_serial8250_port *p = uart->p;
183
184 if (!enable_off_mode)
185 return;
186
187 if (!uart->context_valid)
188 return;
189
190 uart->context_valid = 0;
191
192 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
193 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
194 efr = serial_read_reg(p, UART_EFR);
195 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
196 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
197 serial_write_reg(p, UART_IER, 0x0);
198 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
199 serial_write_reg(p, UART_DLL, uart->dll);
200 serial_write_reg(p, UART_DLM, uart->dlh);
201 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
202 serial_write_reg(p, UART_IER, uart->ier);
203 serial_write_reg(p, UART_FCR, 0xA1);
204 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
205 serial_write_reg(p, UART_EFR, efr);
206 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
207 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
208 serial_write_reg(p, UART_OMAP_WER, uart->wer);
209 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
210 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
211 }
212 #else
213 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
214 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
215 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
216
217 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
218 {
219 if (uart->clocked)
220 return;
221
222 clk_enable(uart->ick);
223 clk_enable(uart->fck);
224 uart->clocked = 1;
225 omap_uart_restore_context(uart);
226 }
227
228 #ifdef CONFIG_PM
229
230 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
231 {
232 if (!uart->clocked)
233 return;
234
235 omap_uart_save_context(uart);
236 uart->clocked = 0;
237 clk_disable(uart->ick);
238 clk_disable(uart->fck);
239 }
240
241 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
242 {
243 /* Set wake-enable bit */
244 if (uart->wk_en && uart->wk_mask) {
245 u32 v = __raw_readl(uart->wk_en);
246 v |= uart->wk_mask;
247 __raw_writel(v, uart->wk_en);
248 }
249
250 /* Ensure IOPAD wake-enables are set */
251 if (cpu_is_omap34xx() && uart->padconf) {
252 u16 v = omap_ctrl_readw(uart->padconf);
253 v |= OMAP3_PADCONF_WAKEUPENABLE0;
254 omap_ctrl_writew(v, uart->padconf);
255 }
256 }
257
258 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
259 {
260 /* Clear wake-enable bit */
261 if (uart->wk_en && uart->wk_mask) {
262 u32 v = __raw_readl(uart->wk_en);
263 v &= ~uart->wk_mask;
264 __raw_writel(v, uart->wk_en);
265 }
266
267 /* Ensure IOPAD wake-enables are cleared */
268 if (cpu_is_omap34xx() && uart->padconf) {
269 u16 v = omap_ctrl_readw(uart->padconf);
270 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
271 omap_ctrl_writew(v, uart->padconf);
272 }
273 }
274
275 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
276 int enable)
277 {
278 struct plat_serial8250_port *p = uart->p;
279 u16 sysc;
280
281 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
282 if (enable)
283 sysc |= 0x2 << 3;
284 else
285 sysc |= 0x1 << 3;
286
287 serial_write_reg(p, UART_OMAP_SYSC, sysc);
288 }
289
290 static void omap_uart_block_sleep(struct omap_uart_state *uart)
291 {
292 omap_uart_enable_clocks(uart);
293
294 omap_uart_smart_idle_enable(uart, 0);
295 uart->can_sleep = 0;
296 if (uart->timeout)
297 mod_timer(&uart->timer, jiffies + uart->timeout);
298 else
299 del_timer(&uart->timer);
300 }
301
302 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
303 {
304 if (device_may_wakeup(&uart->pdev.dev))
305 omap_uart_enable_wakeup(uart);
306 else
307 omap_uart_disable_wakeup(uart);
308
309 if (!uart->clocked)
310 return;
311
312 omap_uart_smart_idle_enable(uart, 1);
313 uart->can_sleep = 1;
314 del_timer(&uart->timer);
315 }
316
317 static void omap_uart_idle_timer(unsigned long data)
318 {
319 struct omap_uart_state *uart = (struct omap_uart_state *)data;
320
321 omap_uart_allow_sleep(uart);
322 }
323
324 void omap_uart_prepare_idle(int num)
325 {
326 struct omap_uart_state *uart;
327
328 list_for_each_entry(uart, &uart_list, node) {
329 if (num == uart->num && uart->can_sleep) {
330 omap_uart_disable_clocks(uart);
331 return;
332 }
333 }
334 }
335
336 void omap_uart_resume_idle(int num)
337 {
338 struct omap_uart_state *uart;
339
340 list_for_each_entry(uart, &uart_list, node) {
341 if (num == uart->num) {
342 omap_uart_enable_clocks(uart);
343
344 /* Check for IO pad wakeup */
345 if (cpu_is_omap34xx() && uart->padconf) {
346 u16 p = omap_ctrl_readw(uart->padconf);
347
348 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
349 omap_uart_block_sleep(uart);
350 }
351
352 /* Check for normal UART wakeup */
353 if (__raw_readl(uart->wk_st) & uart->wk_mask)
354 omap_uart_block_sleep(uart);
355 return;
356 }
357 }
358 }
359
360 void omap_uart_prepare_suspend(void)
361 {
362 struct omap_uart_state *uart;
363
364 list_for_each_entry(uart, &uart_list, node) {
365 omap_uart_allow_sleep(uart);
366 }
367 }
368
369 int omap_uart_can_sleep(void)
370 {
371 struct omap_uart_state *uart;
372 int can_sleep = 1;
373
374 list_for_each_entry(uart, &uart_list, node) {
375 if (!uart->clocked)
376 continue;
377
378 if (!uart->can_sleep) {
379 can_sleep = 0;
380 continue;
381 }
382
383 /* This UART can now safely sleep. */
384 omap_uart_allow_sleep(uart);
385 }
386
387 return can_sleep;
388 }
389
390 /**
391 * omap_uart_interrupt()
392 *
393 * This handler is used only to detect that *any* UART interrupt has
394 * occurred. It does _nothing_ to handle the interrupt. Rather,
395 * any UART interrupt will trigger the inactivity timer so the
396 * UART will not idle or sleep for its timeout period.
397 *
398 **/
399 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
400 {
401 struct omap_uart_state *uart = dev_id;
402
403 omap_uart_block_sleep(uart);
404
405 return IRQ_NONE;
406 }
407
408 static void omap_uart_idle_init(struct omap_uart_state *uart)
409 {
410 struct plat_serial8250_port *p = uart->p;
411 int ret;
412
413 uart->can_sleep = 0;
414 uart->timeout = DEFAULT_TIMEOUT;
415 setup_timer(&uart->timer, omap_uart_idle_timer,
416 (unsigned long) uart);
417 mod_timer(&uart->timer, jiffies + uart->timeout);
418 omap_uart_smart_idle_enable(uart, 0);
419
420 if (cpu_is_omap34xx()) {
421 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
422 u32 wk_mask = 0;
423 u32 padconf = 0;
424
425 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
426 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
427 switch (uart->num) {
428 case 0:
429 wk_mask = OMAP3430_ST_UART1_MASK;
430 padconf = 0x182;
431 break;
432 case 1:
433 wk_mask = OMAP3430_ST_UART2_MASK;
434 padconf = 0x17a;
435 break;
436 case 2:
437 wk_mask = OMAP3430_ST_UART3_MASK;
438 padconf = 0x19e;
439 break;
440 }
441 uart->wk_mask = wk_mask;
442 uart->padconf = padconf;
443 } else if (cpu_is_omap24xx()) {
444 u32 wk_mask = 0;
445
446 if (cpu_is_omap2430()) {
447 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
448 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
449 } else if (cpu_is_omap2420()) {
450 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
451 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
452 }
453 switch (uart->num) {
454 case 0:
455 wk_mask = OMAP24XX_ST_UART1_MASK;
456 break;
457 case 1:
458 wk_mask = OMAP24XX_ST_UART2_MASK;
459 break;
460 case 2:
461 wk_mask = OMAP24XX_ST_UART3_MASK;
462 break;
463 }
464 uart->wk_mask = wk_mask;
465 } else {
466 uart->wk_en = 0;
467 uart->wk_st = 0;
468 uart->wk_mask = 0;
469 uart->padconf = 0;
470 }
471
472 p->irqflags |= IRQF_SHARED;
473 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
474 "serial idle", (void *)uart);
475 WARN_ON(ret);
476 }
477
478 void omap_uart_enable_irqs(int enable)
479 {
480 int ret;
481 struct omap_uart_state *uart;
482
483 list_for_each_entry(uart, &uart_list, node) {
484 if (enable)
485 ret = request_irq(uart->p->irq, omap_uart_interrupt,
486 IRQF_SHARED, "serial idle", (void *)uart);
487 else
488 free_irq(uart->p->irq, (void *)uart);
489 }
490 }
491
492 static ssize_t sleep_timeout_show(struct device *dev,
493 struct device_attribute *attr,
494 char *buf)
495 {
496 struct platform_device *pdev = container_of(dev,
497 struct platform_device, dev);
498 struct omap_uart_state *uart = container_of(pdev,
499 struct omap_uart_state, pdev);
500
501 return sprintf(buf, "%u\n", uart->timeout / HZ);
502 }
503
504 static ssize_t sleep_timeout_store(struct device *dev,
505 struct device_attribute *attr,
506 const char *buf, size_t n)
507 {
508 struct platform_device *pdev = container_of(dev,
509 struct platform_device, dev);
510 struct omap_uart_state *uart = container_of(pdev,
511 struct omap_uart_state, pdev);
512 unsigned int value;
513
514 if (sscanf(buf, "%u", &value) != 1) {
515 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
516 return -EINVAL;
517 }
518
519 uart->timeout = value * HZ;
520 if (uart->timeout)
521 mod_timer(&uart->timer, jiffies + uart->timeout);
522 else
523 /* A zero value means disable timeout feature */
524 omap_uart_block_sleep(uart);
525
526 return n;
527 }
528
529 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
530 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
531 #else
532 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
533 #define DEV_CREATE_FILE(dev, attr)
534 #endif /* CONFIG_PM */
535
536 static struct omap_uart_state omap_uart[] = {
537 {
538 .pdev = {
539 .name = "serial8250",
540 .id = PLAT8250_DEV_PLATFORM,
541 .dev = {
542 .platform_data = serial_platform_data0,
543 },
544 },
545 }, {
546 .pdev = {
547 .name = "serial8250",
548 .id = PLAT8250_DEV_PLATFORM1,
549 .dev = {
550 .platform_data = serial_platform_data1,
551 },
552 },
553 }, {
554 .pdev = {
555 .name = "serial8250",
556 .id = PLAT8250_DEV_PLATFORM2,
557 .dev = {
558 .platform_data = serial_platform_data2,
559 },
560 },
561 },
562 #ifdef CONFIG_ARCH_OMAP4
563 {
564 .pdev = {
565 .name = "serial8250",
566 .id = 3,
567 .dev = {
568 .platform_data = serial_platform_data3,
569 },
570 },
571 },
572 #endif
573 };
574
575 void __init omap_serial_early_init(void)
576 {
577 int i;
578 char name[16];
579
580 /*
581 * Make sure the serial ports are muxed on at this point.
582 * You have to mux them off in device drivers later on
583 * if not needed.
584 */
585
586 for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
587 struct omap_uart_state *uart = &omap_uart[i];
588 struct platform_device *pdev = &uart->pdev;
589 struct device *dev = &pdev->dev;
590 struct plat_serial8250_port *p = dev->platform_data;
591
592 /*
593 * Module 4KB + L4 interconnect 4KB
594 * Static mapping, never released
595 */
596 p->membase = ioremap(p->mapbase, SZ_8K);
597 if (!p->membase) {
598 printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
599 continue;
600 }
601
602 sprintf(name, "uart%d_ick", i+1);
603 uart->ick = clk_get(NULL, name);
604 if (IS_ERR(uart->ick)) {
605 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
606 uart->ick = NULL;
607 }
608
609 sprintf(name, "uart%d_fck", i+1);
610 uart->fck = clk_get(NULL, name);
611 if (IS_ERR(uart->fck)) {
612 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
613 uart->fck = NULL;
614 }
615
616 /* FIXME: Remove this once the clkdev is ready */
617 if (!cpu_is_omap44xx()) {
618 if (!uart->ick || !uart->fck)
619 continue;
620 }
621
622 uart->num = i;
623 p->private_data = uart;
624 uart->p = p;
625 list_add_tail(&uart->node, &uart_list);
626
627 if (cpu_is_omap44xx())
628 p->irq += 32;
629
630 omap_uart_enable_clocks(uart);
631 }
632 }
633
634 void __init omap_serial_init(void)
635 {
636 int i;
637
638 for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
639 struct omap_uart_state *uart = &omap_uart[i];
640 struct platform_device *pdev = &uart->pdev;
641 struct device *dev = &pdev->dev;
642
643 omap_uart_reset(uart);
644 omap_uart_idle_init(uart);
645
646 if (WARN_ON(platform_device_register(pdev)))
647 continue;
648 if ((cpu_is_omap34xx() && uart->padconf) ||
649 (uart->wk_en && uart->wk_mask)) {
650 device_init_wakeup(dev, true);
651 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
652 }
653 }
654 }
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