arch/arm/mach-omap2/resource34xx.h

   1 /*
   2  * linux/arch/arm/mach-omap2/resource34xx.h
   3  *
   4  * OMAP3 resource definitions
   5  *
   6  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  14  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  15  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  16  *
  17  * History:
  18  *
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_RESOURCE_H
  22 #define __ARCH_ARM_MACH_OMAP2_RESOURCE_H
  23
  24 #include <linux/clk.h>
  25
  26 #include <plat/resource.h>
  27 #include <plat/powerdomain.h>
  28 #include <plat/resource.h>
  29 #include <plat/clock.h>
  30 #include <plat/omap-pm.h>
  31 #include <plat/omap34xx.h>
  32
  33 extern int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel);
  34
  35 /*
  36  * mpu_latency/core_latency are used to control the cpuidle C state.
  37  */
  38 void init_latency(struct shared_resource *resp);
  39 int set_latency(struct shared_resource *resp, u32 target_level);
  40
  41 static u8 mpu_qos_req_added;
  42 static u8 core_qos_req_added;
  43
  44 static struct shared_resource_ops lat_res_ops = {
  45         .init           = init_latency,
  46         .change_level   = set_latency,
  47 };
  48
  49 static struct shared_resource mpu_latency = {
  50         .name           = "mpu_latency",
  51         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  52         .resource_data  = &mpu_qos_req_added,
  53         .ops            = &lat_res_ops,
  54 };
  55
  56 static struct shared_resource core_latency = {
  57         .name           = "core_latency",
  58         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  59         .resource_data  = &core_qos_req_added,
  60         .ops            = &lat_res_ops,
  61 };
  62
  63 /*
  64  * Power domain Latencies are used to control the target Power
  65  * domain state once all clocks for the power domain
  66  * are released.
  67  */
  68 void init_pd_latency(struct shared_resource *resp);
  69 int set_pd_latency(struct shared_resource *resp, u32 target_level);
  70
  71 /* Power Domain Latency levels */
  72 #define PD_LATENCY_OFF          0x0
  73 #define PD_LATENCY_RET          0x1
  74 #define PD_LATENCY_INACT        0x2
  75 #define PD_LATENCY_ON           0x3
  76
  77 #define PD_LATENCY_MAXLEVEL     0x4
  78
  79 struct pd_latency_db {
  80         char *pwrdm_name;
  81         struct powerdomain *pd;
  82         /* Latencies for each state transition, stored in us */
  83         unsigned long latency[PD_LATENCY_MAXLEVEL];
  84 };
  85
  86 static struct shared_resource_ops pd_lat_res_ops = {
  87         .init           = init_pd_latency,
  88         .change_level   = set_pd_latency,
  89 };
  90
  91 static struct shared_resource core_pwrdm_latency = {
  92         .name           = "core_pwrdm_latency",
  93         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  94         .resource_data  = &core_qos_req_added,
  95         .ops            = &lat_res_ops,
  96 };
  97
  98 static struct pd_latency_db iva2_pwrdm_lat_db = {
  99         .pwrdm_name = "iva2_pwrdm",
 100         .latency[PD_LATENCY_OFF] = 1100,
 101         .latency[PD_LATENCY_RET] = 350,
 102         .latency[PD_LATENCY_INACT] = -1,
 103         .latency[PD_LATENCY_ON] = 0
 104 };
 105
 106 static struct shared_resource iva2_pwrdm_latency = {
 107         .name           = "iva2_pwrdm_latency",
 108         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 109         .resource_data  = &iva2_pwrdm_lat_db,
 110         .ops            = &pd_lat_res_ops,
 111 };
 112
 113 static struct pd_latency_db gfx_pwrdm_lat_db = {
 114         .pwrdm_name = "gfx_pwrdm",
 115         .latency[PD_LATENCY_OFF] = 1000,
 116         .latency[PD_LATENCY_RET] = 100,
 117         .latency[PD_LATENCY_INACT] = -1,
 118         .latency[PD_LATENCY_ON]  = 0
 119 };
 120
 121 static struct pd_latency_db sgx_pwrdm_lat_db = {
 122         .pwrdm_name = "sgx_pwrdm",
 123         .latency[PD_LATENCY_OFF] = 1000,
 124         .latency[PD_LATENCY_RET] = 100,
 125         .latency[PD_LATENCY_INACT] = -1,
 126         .latency[PD_LATENCY_ON]  = 0
 127 };
 128
 129 static struct shared_resource gfx_pwrdm_latency = {
 130         .name           = "gfx_pwrdm_latency",
 131         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 132         .resource_data  = &gfx_pwrdm_lat_db,
 133         .ops            = &pd_lat_res_ops,
 134 };
 135
 136 static struct shared_resource sgx_pwrdm_latency = {
 137         .name           = "sgx_pwrdm_latency",
 138         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 139         .resource_data  = &sgx_pwrdm_lat_db,
 140         .ops            = &pd_lat_res_ops,
 141 };
 142
 143 static struct pd_latency_db dss_pwrdm_lat_db = {
 144         .pwrdm_name = "dss_pwrdm",
 145         .latency[PD_LATENCY_OFF] = 70,
 146         .latency[PD_LATENCY_RET] = 20,
 147         .latency[PD_LATENCY_INACT] = -1,
 148         .latency[PD_LATENCY_ON]  = 0
 149 };
 150
 151 static struct shared_resource dss_pwrdm_latency = {
 152         .name           = "dss_pwrdm_latency",
 153         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 154         .resource_data  = &dss_pwrdm_lat_db,
 155         .ops            = &pd_lat_res_ops,
 156 };
 157
 158 static struct pd_latency_db cam_pwrdm_lat_db = {
 159         .pwrdm_name = "cam_pwrdm",
 160         .latency[PD_LATENCY_OFF] = 850,
 161         .latency[PD_LATENCY_RET] = 35,
 162         .latency[PD_LATENCY_INACT] = -1,
 163         .latency[PD_LATENCY_ON]  = 0
 164 };
 165
 166 static struct shared_resource cam_pwrdm_latency = {
 167         .name           = "cam_pwrdm_latency",
 168         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 169         .resource_data  = &cam_pwrdm_lat_db,
 170         .ops            = &pd_lat_res_ops,
 171 };
 172
 173 static struct pd_latency_db per_pwrdm_lat_db = {
 174         .pwrdm_name = "per_pwrdm",
 175         .latency[PD_LATENCY_OFF] = 200,
 176         .latency[PD_LATENCY_RET] = 110,
 177         .latency[PD_LATENCY_INACT] = -1,
 178         .latency[PD_LATENCY_ON]  = 0
 179 };
 180
 181 static struct shared_resource per_pwrdm_latency = {
 182         .name           = "per_pwrdm_latency",
 183         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 184         .resource_data  = &per_pwrdm_lat_db,
 185         .ops            = &pd_lat_res_ops,
 186 };
 187
 188 static struct pd_latency_db neon_pwrdm_lat_db = {
 189         .pwrdm_name = "neon_pwrdm",
 190         .latency[PD_LATENCY_OFF] = 200,
 191         .latency[PD_LATENCY_RET] = 35,
 192         .latency[PD_LATENCY_INACT] = -1,
 193         .latency[PD_LATENCY_ON]  = 0
 194 };
 195
 196 static struct shared_resource neon_pwrdm_latency = {
 197         .name           = "neon_pwrdm_latency",
 198         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 199         .resource_data  = &neon_pwrdm_lat_db,
 200         .ops            = &pd_lat_res_ops,
 201 };
 202
 203 static struct pd_latency_db usbhost_pwrdm_lat_db = {
 204         .pwrdm_name = "usbhost_pwrdm",
 205         .latency[PD_LATENCY_OFF] = 800,
 206         .latency[PD_LATENCY_RET] = 150,
 207         .latency[PD_LATENCY_INACT] = -1,
 208         .latency[PD_LATENCY_ON]  = 0
 209 };
 210
 211 static struct shared_resource usbhost_pwrdm_latency = {
 212         .name           = "usbhost_pwrdm_latency",
 213         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 214         .resource_data  = &usbhost_pwrdm_lat_db,
 215         .ops            = &pd_lat_res_ops,
 216 };
 217
 218 static struct pd_latency_db emu_pwrdm_lat_db = {
 219         .pwrdm_name = "emu_pwrdm",
 220         .latency[PD_LATENCY_OFF] = 1000,
 221         .latency[PD_LATENCY_RET] = 100,
 222         .latency[PD_LATENCY_INACT] = -1,
 223         .latency[PD_LATENCY_ON]  = 0
 224 };
 225
 226 static struct shared_resource emu_pwrdm_latency = {
 227         .name           = "emu_pwrdm",
 228         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 229         .resource_data  = &emu_pwrdm_lat_db,
 230         .ops            = &pd_lat_res_ops,
 231 };
 232
 233 void init_opp(struct shared_resource *resp);
 234 int set_opp(struct shared_resource *resp, u32 target_level);
 235 int validate_opp(struct shared_resource *resp, u32 target_level);
 236 void init_freq(struct shared_resource *resp);
 237 int set_freq(struct shared_resource *resp, u32 target_level);
 238 int validate_freq(struct shared_resource *resp, u32 target_level);
 239
 240 struct bus_throughput_db {
 241         /* Throughput for each OPP/Freq of the bus */
 242         unsigned long throughput[3];
 243 };
 244
 245 static struct shared_resource_ops opp_res_ops = {
 246         .init           = init_opp,
 247         .change_level   = set_opp,
 248         .validate_level = validate_opp,
 249 };
 250
 251 static struct shared_resource vdd1_opp = {
 252         .name           = "vdd1_opp",
 253         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 254         .ops            = &opp_res_ops,
 255 };
 256
 257 /* Throughput in KiB/s */
 258 static struct bus_throughput_db l3_throughput_db = {
 259         .throughput[0] = 0,
 260         .throughput[1] = 2656000,
 261         .throughput[2] = 5312000,
 262 };
 263
 264 static struct shared_resource vdd2_opp = {
 265         .name           = "vdd2_opp",
 266         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 267         .resource_data  = &l3_throughput_db,
 268         .ops            = &opp_res_ops,
 269 };
 270
 271 static char linked_res[] = "vdd1_opp";
 272
 273 static struct shared_resource_ops freq_res_ops = {
 274         .init           = init_freq,
 275         .change_level   = set_freq,
 276         .validate_level = validate_freq,
 277 };
 278
 279 static struct shared_resource mpu_freq = {
 280         .name           = "mpu_freq",
 281         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 282         .resource_data  = &linked_res,
 283         .ops            = &freq_res_ops,
 284 };
 285
 286 static struct shared_resource dsp_freq = {
 287         .name           = "dsp_freq",
 288         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 289         .resource_data  = &linked_res,
 290         .ops            = &freq_res_ops,
 291 };
 292
 293 struct shared_resource *resources_omap[] __initdata = {
 294         &mpu_latency,
 295         &core_latency,
 296         /* Power Domain Latency resources */
 297         &core_pwrdm_latency,
 298         &iva2_pwrdm_latency,
 299         &gfx_pwrdm_latency,
 300         &sgx_pwrdm_latency,
 301         &dss_pwrdm_latency,
 302         &cam_pwrdm_latency,
 303         &per_pwrdm_latency,
 304         &neon_pwrdm_latency,
 305         &usbhost_pwrdm_latency,
 306         &emu_pwrdm_latency,
 307         /* OPP/frequency resources */
 308         &vdd1_opp,
 309         &vdd2_opp,
 310         &mpu_freq,
 311         &dsp_freq,
 312         NULL
 313 };
 314
 315 #endif /* __ARCH_ARM_MACH_OMAP2_RESOURCE_H */