2 * Copyright (C) 2003, Axis Communications AB.
7 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/errno.h>
11 #include <linux/init.h>
12 #include <linux/profile.h>
13 #include <linux/proc_fs.h>
14 #include <linux/seq_file.h>
15 #include <linux/threads.h>
16 #include <linux/spinlock.h>
17 #include <linux/kernel_stat.h>
18 #include <hwregs/reg_map.h>
19 #include <hwregs/reg_rdwr.h>
20 #include <hwregs/intr_vect.h>
21 #include <hwregs/intr_vect_defs.h>
25 /* IRQ masks (refer to comment for crisv32_do_multiple) */
26 #if TIMER0_INTR_VECT - FIRST_IRQ < 32
27 #define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
30 #define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
33 #ifdef CONFIG_ETRAX_KGDB
34 #if defined(CONFIG_ETRAX_KGDB_PORT0)
35 #define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
36 #elif defined(CONFIG_ETRAX_KGDB_PORT1)
37 #define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
38 #elif defined(CONFIG_ETRAX_KGB_PORT2)
39 #define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
40 #elif defined(CONFIG_ETRAX_KGDB_PORT3)
41 #define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
45 DEFINE_SPINLOCK(irq_lock
);
47 struct cris_irq_allocation
49 int cpu
; /* The CPU to which the IRQ is currently allocated. */
50 cpumask_t mask
; /* The CPUs to which the IRQ may be allocated. */
53 struct cris_irq_allocation irq_allocations
[NR_REAL_IRQS
] =
54 { [0 ... NR_REAL_IRQS
- 1] = {0, CPU_MASK_ALL
} };
56 static unsigned long irq_regs
[NR_CPUS
] =
70 unsigned long cpu_irq_counters
[NR_CPUS
];
71 unsigned long irq_counters
[NR_REAL_IRQS
];
74 extern void weird_irq(void);
77 extern void system_call(void);
78 extern void nmi_interrupt(void);
79 extern void multiple_interrupt(void);
80 extern void gdb_handle_exception(void);
81 extern void i_mmu_refill(void);
82 extern void i_mmu_invalid(void);
83 extern void i_mmu_access(void);
84 extern void i_mmu_execute(void);
85 extern void d_mmu_refill(void);
86 extern void d_mmu_invalid(void);
87 extern void d_mmu_access(void);
88 extern void d_mmu_write(void);
91 extern void kgdb_init(void);
92 extern void breakpoint(void);
95 extern void breakh_BUG(void);
98 * Build the IRQ handler stubs using macros from irq.h.
167 /* Pointers to the low-level handlers. */
168 static void (*interrupt
[MACH_IRQS
])(void) = {
169 IRQ0x31_interrupt
, IRQ0x32_interrupt
, IRQ0x33_interrupt
,
170 IRQ0x34_interrupt
, IRQ0x35_interrupt
, IRQ0x36_interrupt
,
171 IRQ0x37_interrupt
, IRQ0x38_interrupt
, IRQ0x39_interrupt
,
172 IRQ0x3a_interrupt
, IRQ0x3b_interrupt
, IRQ0x3c_interrupt
,
173 IRQ0x3d_interrupt
, IRQ0x3e_interrupt
, IRQ0x3f_interrupt
,
174 IRQ0x40_interrupt
, IRQ0x41_interrupt
, IRQ0x42_interrupt
,
175 IRQ0x43_interrupt
, IRQ0x44_interrupt
, IRQ0x45_interrupt
,
176 IRQ0x46_interrupt
, IRQ0x47_interrupt
, IRQ0x48_interrupt
,
177 IRQ0x49_interrupt
, IRQ0x4a_interrupt
, IRQ0x4b_interrupt
,
178 IRQ0x4c_interrupt
, IRQ0x4d_interrupt
, IRQ0x4e_interrupt
,
179 IRQ0x4f_interrupt
, IRQ0x50_interrupt
,
181 IRQ0x51_interrupt
, IRQ0x52_interrupt
, IRQ0x53_interrupt
,
182 IRQ0x54_interrupt
, IRQ0x55_interrupt
, IRQ0x56_interrupt
,
183 IRQ0x57_interrupt
, IRQ0x58_interrupt
, IRQ0x59_interrupt
,
184 IRQ0x5a_interrupt
, IRQ0x5b_interrupt
, IRQ0x5c_interrupt
,
185 IRQ0x5d_interrupt
, IRQ0x5e_interrupt
, IRQ0x5f_interrupt
,
186 IRQ0x60_interrupt
, IRQ0x61_interrupt
, IRQ0x62_interrupt
,
187 IRQ0x63_interrupt
, IRQ0x64_interrupt
, IRQ0x65_interrupt
,
188 IRQ0x66_interrupt
, IRQ0x67_interrupt
, IRQ0x68_interrupt
,
189 IRQ0x69_interrupt
, IRQ0x6a_interrupt
, IRQ0x6b_interrupt
,
190 IRQ0x6c_interrupt
, IRQ0x6d_interrupt
, IRQ0x6e_interrupt
,
191 IRQ0x6f_interrupt
, IRQ0x70_interrupt
,
196 block_irq(int irq
, int cpu
)
201 spin_lock_irqsave(&irq_lock
, flags
);
202 if (irq
- FIRST_IRQ
< 32)
203 intr_mask
= REG_RD_INT_VECT(intr_vect
, irq_regs
[cpu
],
206 intr_mask
= REG_RD_INT_VECT(intr_vect
, irq_regs
[cpu
],
209 /* Remember; 1 let thru, 0 block. */
210 if (irq
- FIRST_IRQ
< 32)
211 intr_mask
&= ~(1 << (irq
- FIRST_IRQ
));
213 intr_mask
&= ~(1 << (irq
- FIRST_IRQ
- 32));
215 if (irq
- FIRST_IRQ
< 32)
216 REG_WR_INT_VECT(intr_vect
, irq_regs
[cpu
], rw_mask
,
219 REG_WR_INT_VECT(intr_vect
, irq_regs
[cpu
], rw_mask
,
221 spin_unlock_irqrestore(&irq_lock
, flags
);
225 unblock_irq(int irq
, int cpu
)
230 spin_lock_irqsave(&irq_lock
, flags
);
231 if (irq
- FIRST_IRQ
< 32)
232 intr_mask
= REG_RD_INT_VECT(intr_vect
, irq_regs
[cpu
],
235 intr_mask
= REG_RD_INT_VECT(intr_vect
, irq_regs
[cpu
],
238 /* Remember; 1 let thru, 0 block. */
239 if (irq
- FIRST_IRQ
< 32)
240 intr_mask
|= (1 << (irq
- FIRST_IRQ
));
242 intr_mask
|= (1 << (irq
- FIRST_IRQ
- 32));
244 if (irq
- FIRST_IRQ
< 32)
245 REG_WR_INT_VECT(intr_vect
, irq_regs
[cpu
], rw_mask
,
248 REG_WR_INT_VECT(intr_vect
, irq_regs
[cpu
], rw_mask
,
251 spin_unlock_irqrestore(&irq_lock
, flags
);
254 /* Find out which CPU the irq should be allocated to. */
255 static int irq_cpu(int irq
)
260 spin_lock_irqsave(&irq_lock
, flags
);
261 cpu
= irq_allocations
[irq
- FIRST_IRQ
].cpu
;
263 /* Fixed interrupts stay on the local CPU. */
264 if (cpu
== CPU_FIXED
)
266 spin_unlock_irqrestore(&irq_lock
, flags
);
267 return smp_processor_id();
271 /* Let the interrupt stay if possible */
272 if (cpu_isset(cpu
, irq_allocations
[irq
- FIRST_IRQ
].mask
))
275 /* IRQ must be moved to another CPU. */
276 cpu
= first_cpu(irq_allocations
[irq
- FIRST_IRQ
].mask
);
277 irq_allocations
[irq
- FIRST_IRQ
].cpu
= cpu
;
279 spin_unlock_irqrestore(&irq_lock
, flags
);
288 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
295 unblock_irq(irq
, irq_cpu(irq
));
299 static unsigned int startup_crisv32_irq(unsigned int irq
)
305 static void shutdown_crisv32_irq(unsigned int irq
)
310 static void enable_crisv32_irq(unsigned int irq
)
315 static void disable_crisv32_irq(unsigned int irq
)
320 static void ack_crisv32_irq(unsigned int irq
)
324 static void end_crisv32_irq(unsigned int irq
)
328 void set_affinity_crisv32_irq(unsigned int irq
, cpumask_t dest
)
331 spin_lock_irqsave(&irq_lock
, flags
);
332 irq_allocations
[irq
- FIRST_IRQ
].mask
= dest
;
333 spin_unlock_irqrestore(&irq_lock
, flags
);
336 static struct hw_interrupt_type crisv32_irq_type
= {
337 .typename
= "CRISv32",
338 .startup
= startup_crisv32_irq
,
339 .shutdown
= shutdown_crisv32_irq
,
340 .enable
= enable_crisv32_irq
,
341 .disable
= disable_crisv32_irq
,
342 .ack
= ack_crisv32_irq
,
343 .end
= end_crisv32_irq
,
344 .set_affinity
= set_affinity_crisv32_irq
348 set_exception_vector(int n
, irqvectptr addr
)
350 etrax_irv
->v
[n
] = (irqvectptr
) addr
;
353 extern void do_IRQ(int irq
, struct pt_regs
* regs
);
356 crisv32_do_IRQ(int irq
, int block
, struct pt_regs
* regs
)
358 /* Interrupts that may not be moved to another CPU and
359 * are IRQF_DISABLED may skip blocking. This is currently
360 * only valid for the timer IRQ and the IPI and is used
361 * for the timer interrupt to avoid watchdog starvation.
368 block_irq(irq
, smp_processor_id());
371 unblock_irq(irq
, irq_cpu(irq
));
374 /* If multiple interrupts occur simultaneously we get a multiple
375 * interrupt from the CPU and software has to sort out which
376 * interrupts that happened. There are two special cases here:
378 * 1. Timer interrupts may never be blocked because of the
379 * watchdog (refer to comment in include/asr/arch/irq.h)
380 * 2. GDB serial port IRQs are unhandled here and will be handled
381 * as a single IRQ when it strikes again because the GDB
382 * stubb wants to save the registers in its own fashion.
385 crisv32_do_multiple(struct pt_regs
* regs
)
389 int masked
[NBR_REGS
];
393 cpu
= smp_processor_id();
395 /* An extra irq_enter here to prevent softIRQs to run after
396 * each do_IRQ. This will decrease the interrupt latency.
400 for (i
= 0; i
< NBR_REGS
; i
++) {
401 /* Get which IRQs that happend. */
402 masked
[i
] = REG_RD_INT_VECT(intr_vect
, irq_regs
[cpu
],
405 /* Calculate new IRQ mask with these IRQs disabled. */
406 mask
= REG_RD_INT_VECT(intr_vect
, irq_regs
[cpu
], rw_mask
, i
);
409 /* Timer IRQ is never masked */
411 if ((i
== 1) && (masked
[0] & TIMER_MASK
))
414 if ((i
== 0) && (masked
[0] & TIMER_MASK
))
417 /* Block all the IRQs */
418 REG_WR_INT_VECT(intr_vect
, irq_regs
[cpu
], rw_mask
, i
, mask
);
420 /* Check for timer IRQ and handle it special. */
422 if ((i
== 1) && (masked
[i
] & TIMER_MASK
)) {
423 masked
[i
] &= ~TIMER_MASK
;
424 do_IRQ(TIMER0_INTR_VECT
, regs
);
427 if ((i
== 0) && (masked
[i
] & TIMER_MASK
)) {
428 masked
[i
] &= ~TIMER_MASK
;
429 do_IRQ(TIMER0_INTR_VECT
, regs
);
435 /* Remove IRQs that can't be handled as multiple. */
436 masked
[0] &= ~IGNORE_MASK
;
439 /* Handle the rest of the IRQs. */
440 for (i
= 0; i
< NBR_REGS
; i
++) {
441 for (bit
= 0; bit
< 32; bit
++) {
442 if (masked
[i
] & (1 << bit
))
443 do_IRQ(bit
+ FIRST_IRQ
+ i
*32, regs
);
447 /* Unblock all the IRQs. */
448 for (i
= 0; i
< NBR_REGS
; i
++) {
449 mask
= REG_RD_INT_VECT(intr_vect
, irq_regs
[cpu
], rw_mask
, i
);
451 REG_WR_INT_VECT(intr_vect
, irq_regs
[cpu
], rw_mask
, i
, mask
);
454 /* This irq_exit() will trigger the soft IRQs. */
459 * This is called by start_kernel. It fixes the IRQ masks and setup the
460 * interrupt vector table to point to bad_interrupt pointers.
467 reg_intr_vect_rw_mask vect_mask
= {0};
469 /* Clear all interrupts masks. */
470 for (i
= 0; i
< NBR_REGS
; i
++)
471 REG_WR_VECT(intr_vect
, regi_irq
, rw_mask
, i
, vect_mask
);
473 for (i
= 0; i
< 256; i
++)
474 etrax_irv
->v
[i
] = weird_irq
;
476 /* Point all IRQ's to bad handlers. */
477 for (i
= FIRST_IRQ
, j
= 0; j
< NR_IRQS
; i
++, j
++) {
478 irq_desc
[j
].chip
= &crisv32_irq_type
;
479 set_exception_vector(i
, interrupt
[j
]);
482 /* Mark Timer and IPI IRQs as CPU local */
483 irq_allocations
[TIMER0_INTR_VECT
- FIRST_IRQ
].cpu
= CPU_FIXED
;
484 irq_desc
[TIMER0_INTR_VECT
].status
|= IRQ_PER_CPU
;
485 irq_allocations
[IPI_INTR_VECT
- FIRST_IRQ
].cpu
= CPU_FIXED
;
486 irq_desc
[IPI_INTR_VECT
].status
|= IRQ_PER_CPU
;
488 set_exception_vector(0x00, nmi_interrupt
);
489 set_exception_vector(0x30, multiple_interrupt
);
491 /* Set up handler for various MMU bus faults. */
492 set_exception_vector(0x04, i_mmu_refill
);
493 set_exception_vector(0x05, i_mmu_invalid
);
494 set_exception_vector(0x06, i_mmu_access
);
495 set_exception_vector(0x07, i_mmu_execute
);
496 set_exception_vector(0x08, d_mmu_refill
);
497 set_exception_vector(0x09, d_mmu_invalid
);
498 set_exception_vector(0x0a, d_mmu_access
);
499 set_exception_vector(0x0b, d_mmu_write
);
502 /* Break 14 handler, used to implement cheap BUG(). */
503 set_exception_vector(0x1e, breakh_BUG
);
506 /* The system-call trap is reached by "break 13". */
507 set_exception_vector(0x1d, system_call
);
509 /* Exception handlers for debugging, both user-mode and kernel-mode. */
512 set_exception_vector(0x18, gdb_handle_exception
);
513 /* Hardware single step. */
514 set_exception_vector(0x3, gdb_handle_exception
);
515 /* Hardware breakpoint. */
516 set_exception_vector(0xc, gdb_handle_exception
);
518 #ifdef CONFIG_ETRAX_KGDB
520 /* Everything is set up; now trap the kernel. */