2 * arch/sh/kernel/cpu/sh4/probe.c
4 * CPU Subtype Probing for SH-4.
6 * Copyright (C) 2001 - 2007 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
18 int __init
detect_cpu_and_cache_system(void)
20 unsigned long pvr
, prr
, cvr
;
23 static unsigned long sizes
[16] = {
31 pvr
= (ctrl_inl(CCN_PVR
) >> 8) & 0xffffff;
32 prr
= (ctrl_inl(CCN_PRR
) >> 4) & 0xff;
33 cvr
= (ctrl_inl(CCN_CVR
));
36 * Setup some sane SH-4 defaults for the icache
38 boot_cpu_data
.icache
.way_incr
= (1 << 13);
39 boot_cpu_data
.icache
.entry_shift
= 5;
40 boot_cpu_data
.icache
.sets
= 256;
41 boot_cpu_data
.icache
.ways
= 1;
42 boot_cpu_data
.icache
.linesz
= L1_CACHE_BYTES
;
45 * And again for the dcache ..
47 boot_cpu_data
.dcache
.way_incr
= (1 << 14);
48 boot_cpu_data
.dcache
.entry_shift
= 5;
49 boot_cpu_data
.dcache
.sets
= 512;
50 boot_cpu_data
.dcache
.ways
= 1;
51 boot_cpu_data
.dcache
.linesz
= L1_CACHE_BYTES
;
54 * Setup some generic flags we can probe on SH-4A parts
56 if (((pvr
>> 16) & 0xff) == 0x10) {
57 if ((cvr
& 0x10000000) == 0)
58 boot_cpu_data
.flags
|= CPU_HAS_DSP
;
60 boot_cpu_data
.flags
|= CPU_HAS_LLSC
;
63 /* FPU detection works for everyone */
64 if ((cvr
& 0x20000000) == 1)
65 boot_cpu_data
.flags
|= CPU_HAS_FPU
;
67 /* Mask off the upper chip ID */
71 * Probe the underlying processor version/revision and
72 * adjust cpu_data setup accordingly.
76 boot_cpu_data
.type
= CPU_SH7750
;
77 boot_cpu_data
.flags
|= CPU_HAS_P2_FLUSH_BUG
| CPU_HAS_FPU
|
81 boot_cpu_data
.type
= CPU_SH7750S
;
82 boot_cpu_data
.flags
|= CPU_HAS_P2_FLUSH_BUG
| CPU_HAS_FPU
|
86 boot_cpu_data
.type
= CPU_SH7751
;
87 boot_cpu_data
.flags
|= CPU_HAS_FPU
;
91 boot_cpu_data
.type
= CPU_SH7770
;
92 boot_cpu_data
.icache
.ways
= 4;
93 boot_cpu_data
.dcache
.ways
= 4;
95 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_LLSC
;
100 boot_cpu_data
.type
= CPU_SH7781
;
101 else if (prr
== 0xa1)
102 boot_cpu_data
.type
= CPU_SH7763
;
104 boot_cpu_data
.type
= CPU_SH7780
;
106 boot_cpu_data
.icache
.ways
= 4;
107 boot_cpu_data
.dcache
.ways
= 4;
109 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_PERF_COUNTER
|
115 boot_cpu_data
.type
= CPU_SH7343
;
116 boot_cpu_data
.icache
.ways
= 4;
117 boot_cpu_data
.dcache
.ways
= 4;
118 boot_cpu_data
.flags
|= CPU_HAS_LLSC
;
122 boot_cpu_data
.type
= CPU_SH7785
;
123 boot_cpu_data
.icache
.ways
= 4;
124 boot_cpu_data
.dcache
.ways
= 4;
125 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_PERF_COUNTER
|
129 if (prr
== 0xa0 || prr
== 0xa1) {
130 boot_cpu_data
.type
= CPU_SH7722
;
131 boot_cpu_data
.icache
.ways
= 4;
132 boot_cpu_data
.dcache
.ways
= 4;
133 boot_cpu_data
.flags
|= CPU_HAS_LLSC
;
135 else if (prr
== 0x70) {
136 boot_cpu_data
.type
= CPU_SH7366
;
137 boot_cpu_data
.icache
.ways
= 4;
138 boot_cpu_data
.dcache
.ways
= 4;
139 boot_cpu_data
.flags
|= CPU_HAS_LLSC
;
142 case 0x4000: /* 1st cut */
143 case 0x4001: /* 2nd cut */
144 boot_cpu_data
.type
= CPU_SHX3
;
145 boot_cpu_data
.icache
.ways
= 4;
146 boot_cpu_data
.dcache
.ways
= 4;
147 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_PERF_COUNTER
|
151 boot_cpu_data
.type
= CPU_SH4_501
;
152 boot_cpu_data
.icache
.ways
= 2;
153 boot_cpu_data
.dcache
.ways
= 2;
156 boot_cpu_data
.type
= CPU_SH4_202
;
157 boot_cpu_data
.icache
.ways
= 2;
158 boot_cpu_data
.dcache
.ways
= 2;
159 boot_cpu_data
.flags
|= CPU_HAS_FPU
;
161 case 0x500 ... 0x501:
164 boot_cpu_data
.type
= CPU_SH7750R
;
167 boot_cpu_data
.type
= CPU_SH7751R
;
170 boot_cpu_data
.type
= CPU_SH7760
;
174 boot_cpu_data
.icache
.ways
= 2;
175 boot_cpu_data
.dcache
.ways
= 2;
177 boot_cpu_data
.flags
|= CPU_HAS_FPU
;
181 boot_cpu_data
.type
= CPU_SH_NONE
;
185 #ifdef CONFIG_SH_DIRECT_MAPPED
186 boot_cpu_data
.icache
.ways
= 1;
187 boot_cpu_data
.dcache
.ways
= 1;
190 #ifdef CONFIG_CPU_HAS_PTEA
191 boot_cpu_data
.flags
|= CPU_HAS_PTEA
;
195 * On anything that's not a direct-mapped cache, look to the CVR
196 * for I/D-cache specifics.
198 if (boot_cpu_data
.icache
.ways
> 1) {
199 size
= sizes
[(cvr
>> 20) & 0xf];
200 boot_cpu_data
.icache
.way_incr
= (size
>> 1);
201 boot_cpu_data
.icache
.sets
= (size
>> 6);
205 /* And the rest of the D-cache */
206 if (boot_cpu_data
.dcache
.ways
> 1) {
207 size
= sizes
[(cvr
>> 16) & 0xf];
208 boot_cpu_data
.dcache
.way_incr
= (size
>> 1);
209 boot_cpu_data
.dcache
.sets
= (size
>> 6);
213 * Setup the L2 cache desc
215 * SH-4A's have an optional PIPT L2.
217 if (boot_cpu_data
.flags
& CPU_HAS_L2_CACHE
) {
219 * Size calculation is much more sensible
220 * than it is for the L1.
222 * Sizes are 128KB, 258KB, 512KB, and 1MB.
224 size
= (cvr
& 0xf) << 17;
228 boot_cpu_data
.scache
.way_incr
= (1 << 16);
229 boot_cpu_data
.scache
.entry_shift
= 5;
230 boot_cpu_data
.scache
.ways
= 4;
231 boot_cpu_data
.scache
.linesz
= L1_CACHE_BYTES
;
233 boot_cpu_data
.scache
.entry_mask
=
234 (boot_cpu_data
.scache
.way_incr
-
235 boot_cpu_data
.scache
.linesz
);
237 boot_cpu_data
.scache
.sets
= size
/
238 (boot_cpu_data
.scache
.linesz
*
239 boot_cpu_data
.scache
.ways
);
241 boot_cpu_data
.scache
.way_size
=
242 (boot_cpu_data
.scache
.sets
*
243 boot_cpu_data
.scache
.linesz
);