drivers/scsi/3w-xxxx.h

   1 /*
   2    3w-xxxx.h -- 3ware Storage Controller device driver for Linux.
   3
   4    Written By: Adam Radford <linuxraid@amcc.com>
   5    Modifications By: Joel Jacobson <linux@3ware.com>
   6                      Arnaldo Carvalho de Melo <acme@conectiva.com.br>
   7                      Brad Strand <linux@3ware.com>
   8
   9    Copyright (C) 1999-2009 3ware Inc.
  10
  11    Kernel compatiblity By:      Andre Hedrick <andre@suse.com>
  12    Non-Copyright (C) 2000       Andre Hedrick <andre@suse.com>
  13
  14    This program is free software; you can redistribute it and/or modify
  15    it under the terms of the GNU General Public License as published by
  16    the Free Software Foundation; version 2 of the License.
  17
  18    This program is distributed in the hope that it will be useful,
  19    but WITHOUT ANY WARRANTY; without even the implied warranty of
  20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21    GNU General Public License for more details.
  22
  23    NO WARRANTY
  24    THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  25    CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  26    LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  27    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  28    solely responsible for determining the appropriateness of using and
  29    distributing the Program and assumes all risks associated with its
  30    exercise of rights under this Agreement, including but not limited to
  31    the risks and costs of program errors, damage to or loss of data,
  32    programs or equipment, and unavailability or interruption of operations.
  33
  34    DISCLAIMER OF LIABILITY
  35    NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  36    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  37    DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  38    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  39    TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  40    USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  41    HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  42
  43    You should have received a copy of the GNU General Public License
  44    along with this program; if not, write to the Free Software
  45    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  46
  47    Bugs/Comments/Suggestions should be mailed to:
  48    linuxraid@amcc.com
  49
  50    For more information, goto:
  51    http://www.amcc.com
  52 */
  53
  54 #ifndef _3W_XXXX_H
  55 #define _3W_XXXX_H
  56
  57 #include <linux/types.h>
  58
  59 /* AEN strings */
  60 static char *tw_aen_string[] = {
  61         [0x000] = "INFO: AEN queue empty",
  62         [0x001] = "INFO: Soft reset occurred",
  63         [0x002] = "ERROR: Unit degraded: Unit #",
  64         [0x003] = "ERROR: Controller error",
  65         [0x004] = "ERROR: Rebuild failed: Unit #",
  66         [0x005] = "INFO: Rebuild complete: Unit #",
  67         [0x006] = "ERROR: Incomplete unit detected: Unit #",
  68         [0x007] = "INFO: Initialization complete: Unit #",
  69         [0x008] = "WARNING: Unclean shutdown detected: Unit #",
  70         [0x009] = "WARNING: ATA port timeout: Port #",
  71         [0x00A] = "ERROR: Drive error: Port #",
  72         [0x00B] = "INFO: Rebuild started: Unit #",
  73         [0x00C] = "INFO: Initialization started: Unit #",
  74         [0x00D] = "ERROR: Logical unit deleted: Unit #",
  75         [0x00F] = "WARNING: SMART threshold exceeded: Port #",
  76         [0x021] = "WARNING: ATA UDMA downgrade: Port #",
  77         [0x022] = "WARNING: ATA UDMA upgrade: Port #",
  78         [0x023] = "WARNING: Sector repair occurred: Port #",
  79         [0x024] = "ERROR: SBUF integrity check failure",
  80         [0x025] = "ERROR: Lost cached write: Port #",
  81         [0x026] = "ERROR: Drive ECC error detected: Port #",
  82         [0x027] = "ERROR: DCB checksum error: Port #",
  83         [0x028] = "ERROR: DCB unsupported version: Port #",
  84         [0x029] = "INFO: Verify started: Unit #",
  85         [0x02A] = "ERROR: Verify failed: Port #",
  86         [0x02B] = "INFO: Verify complete: Unit #",
  87         [0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
  88         [0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
  89         [0x02E] = "ERROR: Replacement drive is too small: Port #",
  90         [0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
  91         [0x030] = "ERROR: Drive not supported: Port #"
  92 };
  93
  94 /*
  95    Sense key lookup table
  96    Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier
  97 */
  98 static unsigned char tw_sense_table[][4] =
  99 {
 100   /* Codes for newer firmware */
 101                             // ATA Error                    SCSI Error
 102   {0x01, 0x03, 0x13, 0x00}, // Address mark not found       Address mark not found for data field
 103   {0x04, 0x0b, 0x00, 0x00}, // Aborted command              Aborted command
 104   {0x10, 0x0b, 0x14, 0x00}, // ID not found                 Recorded entity not found
 105   {0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error      Unrecovered read error
 106   {0x61, 0x04, 0x00, 0x00}, // Device fault                 Hardware error
 107   {0x84, 0x0b, 0x47, 0x00}, // Data CRC error               SCSI parity error
 108   {0xd0, 0x0b, 0x00, 0x00}, // Device busy                  Aborted command
 109   {0xd1, 0x0b, 0x00, 0x00}, // Device busy                  Aborted command
 110   {0x37, 0x02, 0x04, 0x00}, // Unit offline                 Not ready
 111   {0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error       Not ready
 112
 113   /* Codes for older firmware */
 114                             // 3ware Error                  SCSI Error
 115   {0x51, 0x0b, 0x00, 0x00}  // Unspecified                  Aborted command
 116 };
 117
 118 /* Control register bit definitions */
 119 #define TW_CONTROL_CLEAR_HOST_INTERRUPT        0x00080000
 120 #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
 121 #define TW_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
 122 #define TW_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
 123 #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
 124 #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
 125 #define TW_CONTROL_CLEAR_ERROR_STATUS          0x00000200
 126 #define TW_CONTROL_ISSUE_SOFT_RESET            0x00000100
 127 #define TW_CONTROL_ENABLE_INTERRUPTS           0x00000080
 128 #define TW_CONTROL_DISABLE_INTERRUPTS          0x00000040
 129 #define TW_CONTROL_ISSUE_HOST_INTERRUPT        0x00000020
 130 #define TW_CONTROL_CLEAR_PARITY_ERROR          0x00800000
 131 #define TW_CONTROL_CLEAR_QUEUE_ERROR           0x00400000
 132 #define TW_CONTROL_CLEAR_PCI_ABORT             0x00100000
 133 #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR      0x00000008
 134
 135 /* Status register bit definitions */
 136 #define TW_STATUS_MAJOR_VERSION_MASK           0xF0000000
 137 #define TW_STATUS_MINOR_VERSION_MASK           0x0F000000
 138 #define TW_STATUS_PCI_PARITY_ERROR             0x00800000
 139 #define TW_STATUS_QUEUE_ERROR                  0x00400000
 140 #define TW_STATUS_MICROCONTROLLER_ERROR        0x00200000
 141 #define TW_STATUS_PCI_ABORT                    0x00100000
 142 #define TW_STATUS_HOST_INTERRUPT               0x00080000
 143 #define TW_STATUS_ATTENTION_INTERRUPT          0x00040000
 144 #define TW_STATUS_COMMAND_INTERRUPT            0x00020000
 145 #define TW_STATUS_RESPONSE_INTERRUPT           0x00010000
 146 #define TW_STATUS_COMMAND_QUEUE_FULL           0x00008000
 147 #define TW_STATUS_RESPONSE_QUEUE_EMPTY         0x00004000
 148 #define TW_STATUS_MICROCONTROLLER_READY        0x00002000
 149 #define TW_STATUS_COMMAND_QUEUE_EMPTY          0x00001000
 150 #define TW_STATUS_ALL_INTERRUPTS               0x000F0000
 151 #define TW_STATUS_CLEARABLE_BITS               0x00D00000
 152 #define TW_STATUS_EXPECTED_BITS                0x00002000
 153 #define TW_STATUS_UNEXPECTED_BITS              0x00F00008
 154 #define TW_STATUS_SBUF_WRITE_ERROR             0x00000008
 155 #define TW_STATUS_VALID_INTERRUPT              0x00DF0008
 156
 157 /* RESPONSE QUEUE BIT DEFINITIONS */
 158 #define TW_RESPONSE_ID_MASK                    0x00000FF0
 159
 160 /* PCI related defines */
 161 #define TW_IO_ADDRESS_RANGE                    0x10
 162 #define TW_DEVICE_NAME                         "3ware Storage Controller"
 163 #define TW_VENDOR_ID (0x13C1)   /* 3ware */
 164 #define TW_DEVICE_ID (0x1000)   /* Storage Controller */
 165 #define TW_DEVICE_ID2 (0x1001)  /* 7000 series controller */
 166 #define TW_NUMDEVICES 2
 167 #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
 168 #define TW_PCI_CLEAR_PCI_ABORT     0x2000
 169
 170 /* Command packet opcodes */
 171 #define TW_OP_NOP             0x0
 172 #define TW_OP_INIT_CONNECTION 0x1
 173 #define TW_OP_READ            0x2
 174 #define TW_OP_WRITE           0x3
 175 #define TW_OP_VERIFY          0x4
 176 #define TW_OP_GET_PARAM       0x12
 177 #define TW_OP_SET_PARAM       0x13
 178 #define TW_OP_SECTOR_INFO     0x1a
 179 #define TW_OP_AEN_LISTEN      0x1c
 180 #define TW_OP_FLUSH_CACHE     0x0e
 181 #define TW_CMD_PACKET         0x1d
 182 #define TW_CMD_PACKET_WITH_DATA 0x1f
 183
 184 /* Asynchronous Event Notification (AEN) Codes */
 185 #define TW_AEN_QUEUE_EMPTY       0x0000
 186 #define TW_AEN_SOFT_RESET        0x0001
 187 #define TW_AEN_DEGRADED_MIRROR   0x0002
 188 #define TW_AEN_CONTROLLER_ERROR  0x0003
 189 #define TW_AEN_REBUILD_FAIL      0x0004
 190 #define TW_AEN_REBUILD_DONE      0x0005
 191 #define TW_AEN_QUEUE_FULL        0x00ff
 192 #define TW_AEN_TABLE_UNDEFINED   0x15
 193 #define TW_AEN_APORT_TIMEOUT     0x0009
 194 #define TW_AEN_DRIVE_ERROR       0x000A
 195 #define TW_AEN_SMART_FAIL        0x000F
 196 #define TW_AEN_SBUF_FAIL         0x0024
 197
 198 /* Phase defines */
 199 #define TW_PHASE_INITIAL 0
 200 #define TW_PHASE_SINGLE 1
 201 #define TW_PHASE_SGLIST 2
 202
 203 /* Misc defines */
 204 #define TW_ALIGNMENT_6000                     64 /* 64 bytes */
 205 #define TW_ALIGNMENT_7000                     4  /* 4 bytes */
 206 #define TW_MAX_UNITS                          16
 207 #define TW_COMMAND_ALIGNMENT_MASK             0x1ff
 208 #define TW_INIT_MESSAGE_CREDITS               0x100
 209 #define TW_INIT_COMMAND_PACKET_SIZE           0x3
 210 #define TW_POLL_MAX_RETRIES                   20000
 211 #define TW_MAX_SGL_LENGTH                     62
 212 #define TW_ATA_PASS_SGL_MAX                   60
 213 #define TW_Q_LENGTH                           256
 214 #define TW_Q_START                            0
 215 #define TW_MAX_SLOT                           32
 216 #define TW_MAX_PCI_BUSES                      255
 217 #define TW_MAX_RESET_TRIES                    3
 218 #define TW_UNIT_INFORMATION_TABLE_BASE        0x300
 219 #define TW_MAX_CMDS_PER_LUN                   254 /* 254 for io, 1 for
 220                                                      chrdev ioctl, one for
 221                                                      internal aen post */
 222 #define TW_BLOCK_SIZE                         0x200 /* 512-byte blocks */
 223 #define TW_IOCTL                              0x80
 224 #define TW_UNIT_ONLINE                        1
 225 #define TW_IN_INTR                            1
 226 #define TW_IN_RESET                           2
 227 #define TW_IN_CHRDEV_IOCTL                    3
 228 #define TW_MAX_SECTORS                        256
 229 #define TW_MAX_IOCTL_SECTORS                  512
 230 #define TW_AEN_WAIT_TIME                      1000
 231 #define TW_IOCTL_WAIT_TIME                    (1 * HZ) /* 1 second */
 232 #define TW_ISR_DONT_COMPLETE                  2
 233 #define TW_ISR_DONT_RESULT                    3
 234 #define TW_IOCTL_TIMEOUT                      25 /* 25 seconds */
 235 #define TW_IOCTL_CHRDEV_TIMEOUT               60 /* 60 seconds */
 236 #define TW_IOCTL_CHRDEV_FREE                  -1
 237 #define TW_DMA_MASK                           DMA_BIT_MASK(32)
 238 #define TW_MAX_CDB_LEN                        16
 239
 240 /* Bitmask macros to eliminate bitfields */
 241
 242 /* opcode: 5, sgloffset: 3 */
 243 #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
 244 #define TW_SGL_OUT(x) ((x >> 5) & 0x7)
 245
 246 /* reserved_1: 4, response_id: 8, reserved_2: 20 */
 247 #define TW_RESID_OUT(x) ((x >> 4) & 0xff)
 248
 249 /* unit: 4, host_id: 4 */
 250 #define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
 251 #define TW_UNIT_OUT(x) (x & 0xf)
 252
 253 /* Macros */
 254 #define TW_CONTROL_REG_ADDR(x) (x->base_addr)
 255 #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
 256 #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
 257 #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
 258 #define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 259 #define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 260 #define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 261 #define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
 262 #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
 263 #define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 264 #define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 265 #define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
 266                         TW_CONTROL_CLEAR_HOST_INTERRUPT | \
 267                         TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
 268                         TW_CONTROL_MASK_COMMAND_INTERRUPT | \
 269                         TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
 270                         TW_CONTROL_CLEAR_ERROR_STATUS | \
 271                         TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
 272 #define TW_STATUS_ERRORS(x) \
 273         (((x & TW_STATUS_PCI_ABORT) || \
 274         (x & TW_STATUS_PCI_PARITY_ERROR) || \
 275         (x & TW_STATUS_QUEUE_ERROR) || \
 276         (x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
 277         (x & TW_STATUS_MICROCONTROLLER_READY))
 278
 279 #ifdef TW_DEBUG
 280 #define dprintk(msg...) printk(msg)
 281 #else
 282 #define dprintk(msg...) do { } while(0)
 283 #endif
 284
 285 #pragma pack(1)
 286
 287 /* Scatter Gather List Entry */
 288 typedef struct TAG_TW_SG_Entry {
 289         u32 address;
 290         u32 length;
 291 } TW_SG_Entry;
 292
 293 typedef unsigned char TW_Sector[512];
 294
 295 /* Command Packet */
 296 typedef struct TW_Command {
 297         unsigned char opcode__sgloffset;
 298         unsigned char size;
 299         unsigned char request_id;
 300         unsigned char unit__hostid;
 301         /* Second DWORD */
 302         unsigned char status;
 303         unsigned char flags;
 304         union {
 305                 unsigned short block_count;
 306                 unsigned short parameter_count;
 307                 unsigned short message_credits;
 308         } byte6;
 309         union {
 310                 struct {
 311                         u32 lba;
 312                         TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
 313                         u32 padding;    /* pad to 512 bytes */
 314                 } io;
 315                 struct {
 316                         TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
 317                         u32 padding[2];
 318                 } param;
 319                 struct {
 320                         u32 response_queue_pointer;
 321                         u32 padding[125];
 322                 } init_connection;
 323                 struct {
 324                         char version[504];
 325                 } ioctl_miniport_version;
 326         } byte8;
 327 } TW_Command;
 328
 329 #pragma pack()
 330
 331 typedef struct TAG_TW_Ioctl {
 332         unsigned char opcode;
 333         unsigned short table_id;
 334         unsigned char parameter_id;
 335         unsigned char parameter_size_bytes;
 336         unsigned char unit_index;
 337         unsigned char data[1];
 338 } TW_Ioctl;
 339
 340 #pragma pack(1)
 341
 342 /* Structure for new chardev ioctls */
 343 typedef struct TAG_TW_New_Ioctl {
 344         unsigned int data_buffer_length;
 345         unsigned char padding [508];
 346         TW_Command firmware_command;
 347         char data_buffer[1];
 348 } TW_New_Ioctl;
 349
 350 /* GetParam descriptor */
 351 typedef struct {
 352         unsigned short  table_id;
 353         unsigned char   parameter_id;
 354         unsigned char   parameter_size_bytes;
 355         unsigned char   data[1];
 356 } TW_Param, *PTW_Param;
 357
 358 /* Response queue */
 359 typedef union TAG_TW_Response_Queue {
 360         u32 response_id;
 361         u32 value;
 362 } TW_Response_Queue;
 363
 364 typedef int TW_Cmd_State;
 365
 366 #define TW_S_INITIAL   0x1  /* Initial state */
 367 #define TW_S_STARTED   0x2  /* Id in use */
 368 #define TW_S_POSTED    0x4  /* Posted to the controller */
 369 #define TW_S_PENDING   0x8  /* Waiting to be posted in isr */
 370 #define TW_S_COMPLETED 0x10 /* Completed by isr */
 371 #define TW_S_FINISHED  0x20 /* I/O completely done */
 372 #define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)
 373
 374 /* Command header for ATA pass-thru */
 375 typedef struct TAG_TW_Passthru
 376 {
 377         unsigned char opcode__sgloffset;
 378         unsigned char size;
 379         unsigned char request_id;
 380         unsigned char aport__hostid;
 381         unsigned char status;
 382         unsigned char flags;
 383         unsigned short param;
 384         unsigned short features;
 385         unsigned short sector_count;
 386         unsigned short sector_num;
 387         unsigned short cylinder_lo;
 388         unsigned short cylinder_hi;
 389         unsigned char drive_head;
 390         unsigned char command;
 391         TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
 392         unsigned char padding[12];
 393 } TW_Passthru;
 394
 395 typedef struct TAG_TW_Device_Extension {
 396         u32                     base_addr;
 397         unsigned long           *alignment_virtual_address[TW_Q_LENGTH];
 398         unsigned long           alignment_physical_address[TW_Q_LENGTH];
 399         int                     is_unit_present[TW_MAX_UNITS];
 400         unsigned long           *command_packet_virtual_address[TW_Q_LENGTH];
 401         unsigned long           command_packet_physical_address[TW_Q_LENGTH];
 402         struct pci_dev          *tw_pci_dev;
 403         struct scsi_cmnd        *srb[TW_Q_LENGTH];
 404         unsigned char           free_queue[TW_Q_LENGTH];
 405         unsigned char           free_head;
 406         unsigned char           free_tail;
 407         unsigned char           pending_queue[TW_Q_LENGTH];
 408         unsigned char           pending_head;
 409         unsigned char           pending_tail;
 410         TW_Cmd_State            state[TW_Q_LENGTH];
 411         u32                     posted_request_count;
 412         u32                     max_posted_request_count;
 413         u32                     request_count_marked_pending;
 414         u32                     pending_request_count;
 415         u32                     max_pending_request_count;
 416         u32                     max_sgl_entries;
 417         u32                     sgl_entries;
 418         u32                     num_resets;
 419         u32                     sector_count;
 420         u32                     max_sector_count;
 421         u32                     aen_count;
 422         struct Scsi_Host        *host;
 423         struct mutex            ioctl_lock;
 424         unsigned short          aen_queue[TW_Q_LENGTH];
 425         unsigned char           aen_head;
 426         unsigned char           aen_tail;
 427         volatile long           flags; /* long req'd for set_bit --RR */
 428         int                     reset_print;
 429         volatile int            chrdev_request_id;
 430         wait_queue_head_t       ioctl_wqueue;
 431 } TW_Device_Extension;
 432
 433 #pragma pack()
 434
 435 #endif /* _3W_XXXX_H */