drivers/ide/palm_bk3710.c

   1 /*
   2  * Palmchip bk3710 IDE controller
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * ----------------------------------------------------------------------------
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  * ----------------------------------------------------------------------------
  23  *
  24  */
  25
  26 #include <linux/types.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/ide.h>
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/clk.h>
  34 #include <linux/platform_device.h>
  35
  36 /* Offset of the primary interface registers */
  37 #define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0
  38
  39 /* Primary Control Offset */
  40 #define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
  41
  42 /*
  43  * PalmChip 3710 IDE Controller UDMA timing structure Definition
  44  */
  45 struct palm_bk3710_udmatiming {
  46         unsigned int rptime;    /* Ready to pause time  */
  47         unsigned int cycletime; /* Cycle Time           */
  48 };
  49
  50 #define BK3710_BMICP            0x00
  51 #define BK3710_BMISP            0x02
  52 #define BK3710_BMIDTP           0x04
  53 #define BK3710_BMICS            0x08
  54 #define BK3710_BMISS            0x0A
  55 #define BK3710_BMIDTS           0x0C
  56 #define BK3710_IDETIMP          0x40
  57 #define BK3710_IDETIMS          0x42
  58 #define BK3710_SIDETIM          0x44
  59 #define BK3710_SLEWCTL          0x45
  60 #define BK3710_IDESTATUS        0x47
  61 #define BK3710_UDMACTL          0x48
  62 #define BK3710_UDMATIM          0x4A
  63 #define BK3710_MISCCTL          0x50
  64 #define BK3710_REGSTB           0x54
  65 #define BK3710_REGRCVR          0x58
  66 #define BK3710_DATSTB           0x5C
  67 #define BK3710_DATRCVR          0x60
  68 #define BK3710_DMASTB           0x64
  69 #define BK3710_DMARCVR          0x68
  70 #define BK3710_UDMASTB          0x6C
  71 #define BK3710_UDMATRP          0x70
  72 #define BK3710_UDMAENV          0x74
  73 #define BK3710_IORDYTMP         0x78
  74 #define BK3710_IORDYTMS         0x7C
  75
  76 static unsigned ideclk_period; /* in nanoseconds */
  77
  78 static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
  79         {160, 240},             /* UDMA Mode 0 */
  80         {125, 160},             /* UDMA Mode 1 */
  81         {100, 120},             /* UDMA Mode 2 */
  82         {100, 90},              /* UDMA Mode 3 */
  83         {100, 60},              /* UDMA Mode 4 */
  84         {85,  40},              /* UDMA Mode 5 */
  85 };
  86
  87 static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
  88                                     unsigned int mode)
  89 {
  90         u8 tenv, trp, t0;
  91         u32 val32;
  92         u16 val16;
  93
  94         /* DMA Data Setup */
  95         t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime,
  96                           ideclk_period) - 1;
  97         tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
  98         trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
  99                            ideclk_period) - 1;
 100
 101         /* udmatim Register */
 102         val16 = readw(base + BK3710_UDMATIM) & (dev ? 0xFF0F : 0xFFF0);
 103         val16 |= (mode << (dev ? 4 : 0));
 104         writew(val16, base + BK3710_UDMATIM);
 105
 106         /* udmastb Ultra DMA Access Strobe Width */
 107         val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
 108         val32 |= (t0 << (dev ? 8 : 0));
 109         writel(val32, base + BK3710_UDMASTB);
 110
 111         /* udmatrp Ultra DMA Ready to Pause Time */
 112         val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
 113         val32 |= (trp << (dev ? 8 : 0));
 114         writel(val32, base + BK3710_UDMATRP);
 115
 116         /* udmaenv Ultra DMA envelop Time */
 117         val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
 118         val32 |= (tenv << (dev ? 8 : 0));
 119         writel(val32, base + BK3710_UDMAENV);
 120
 121         /* Enable UDMA for Device */
 122         val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
 123         writew(val16, base + BK3710_UDMACTL);
 124 }
 125
 126 static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
 127                                    unsigned short min_cycle,
 128                                    unsigned int mode)
 129 {
 130         u8 td, tkw, t0;
 131         u32 val32;
 132         u16 val16;
 133         struct ide_timing *t;
 134         int cycletime;
 135
 136         t = ide_timing_find_mode(mode);
 137         cycletime = max_t(int, t->cycle, min_cycle);
 138
 139         /* DMA Data Setup */
 140         t0 = DIV_ROUND_UP(cycletime, ideclk_period);
 141         td = DIV_ROUND_UP(t->active, ideclk_period);
 142         tkw = t0 - td - 1;
 143         td -= 1;
 144
 145         val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
 146         val32 |= (td << (dev ? 8 : 0));
 147         writel(val32, base + BK3710_DMASTB);
 148
 149         val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
 150         val32 |= (tkw << (dev ? 8 : 0));
 151         writel(val32, base + BK3710_DMARCVR);
 152
 153         /* Disable UDMA for Device */
 154         val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
 155         writew(val16, base + BK3710_UDMACTL);
 156 }
 157
 158 static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
 159                                    unsigned int dev, unsigned int cycletime,
 160                                    unsigned int mode)
 161 {
 162         u8 t2, t2i, t0;
 163         u32 val32;
 164         struct ide_timing *t;
 165
 166         /* PIO Data Setup */
 167         t0 = DIV_ROUND_UP(cycletime, ideclk_period);
 168         t2 = DIV_ROUND_UP(ide_timing_find_mode(XFER_PIO_0 + mode)->active,
 169                           ideclk_period);
 170
 171         t2i = t0 - t2 - 1;
 172         t2 -= 1;
 173
 174         val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
 175         val32 |= (t2 << (dev ? 8 : 0));
 176         writel(val32, base + BK3710_DATSTB);
 177
 178         val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
 179         val32 |= (t2i << (dev ? 8 : 0));
 180         writel(val32, base + BK3710_DATRCVR);
 181
 182         if (mate) {
 183                 u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);
 184
 185                 if (mode2 < mode)
 186                         mode = mode2;
 187         }
 188
 189         /* TASKFILE Setup */
 190         t = ide_timing_find_mode(XFER_PIO_0 + mode);
 191         t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
 192         t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
 193
 194         t2i = t0 - t2 - 1;
 195         t2 -= 1;
 196
 197         val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
 198         val32 |= (t2 << (dev ? 8 : 0));
 199         writel(val32, base + BK3710_REGSTB);
 200
 201         val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
 202         val32 |= (t2i << (dev ? 8 : 0));
 203         writel(val32, base + BK3710_REGRCVR);
 204 }
 205
 206 static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
 207 {
 208         int is_slave = drive->dn & 1;
 209         void __iomem *base = (void *)drive->hwif->dma_base;
 210
 211         if (xferspeed >= XFER_UDMA_0) {
 212                 palm_bk3710_setudmamode(base, is_slave,
 213                                         xferspeed - XFER_UDMA_0);
 214         } else {
 215                 palm_bk3710_setdmamode(base, is_slave,
 216                                        drive->id[ATA_ID_EIDE_DMA_MIN],
 217                                        xferspeed);
 218         }
 219 }
 220
 221 static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
 222 {
 223         unsigned int cycle_time;
 224         int is_slave = drive->dn & 1;
 225         ide_drive_t *mate;
 226         void __iomem *base = (void *)drive->hwif->dma_base;
 227
 228         /*
 229          * Obtain the drive PIO data for tuning the Palm Chip registers
 230          */
 231         cycle_time = ide_pio_cycle_time(drive, pio);
 232         mate = ide_get_pair_dev(drive);
 233         palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
 234 }
 235
 236 static void __devinit palm_bk3710_chipinit(void __iomem *base)
 237 {
 238         /*
 239          * enable the reset_en of ATA controller so that when ata signals
 240          * are brought out, by writing into device config. at that
 241          * time por_n signal should not be 'Z' and have a stable value.
 242          */
 243         writel(0x0300, base + BK3710_MISCCTL);
 244
 245         /* wait for some time and deassert the reset of ATA Device. */
 246         mdelay(100);
 247
 248         /* Deassert the Reset */
 249         writel(0x0200, base + BK3710_MISCCTL);
 250
 251         /*
 252          * Program the IDETIMP Register Value based on the following assumptions
 253          *
 254          * (ATA_IDETIMP_IDEEN           , ENABLE ) |
 255          * (ATA_IDETIMP_SLVTIMEN        , DISABLE) |
 256          * (ATA_IDETIMP_RDYSMPL         , 70NS)    |
 257          * (ATA_IDETIMP_RDYRCVRY        , 50NS)    |
 258          * (ATA_IDETIMP_DMAFTIM1        , PIOCOMP) |
 259          * (ATA_IDETIMP_PREPOST1        , DISABLE) |
 260          * (ATA_IDETIMP_RDYSEN1         , DISABLE) |
 261          * (ATA_IDETIMP_PIOFTIM1        , DISABLE) |
 262          * (ATA_IDETIMP_DMAFTIM0        , PIOCOMP) |
 263          * (ATA_IDETIMP_PREPOST0        , DISABLE) |
 264          * (ATA_IDETIMP_RDYSEN0         , DISABLE) |
 265          * (ATA_IDETIMP_PIOFTIM0        , DISABLE)
 266          */
 267         writew(0xB388, base + BK3710_IDETIMP);
 268
 269         /*
 270          * Configure  SIDETIM  Register
 271          * (ATA_SIDETIM_RDYSMPS1        ,120NS ) |
 272          * (ATA_SIDETIM_RDYRCYS1        ,120NS )
 273          */
 274         writeb(0, base + BK3710_SIDETIM);
 275
 276         /*
 277          * UDMACTL Ultra-ATA DMA Control
 278          * (ATA_UDMACTL_UDMAP1  , 0 ) |
 279          * (ATA_UDMACTL_UDMAP0  , 0 )
 280          *
 281          */
 282         writew(0, base + BK3710_UDMACTL);
 283
 284         /*
 285          * MISCCTL Miscellaneous Conrol Register
 286          * (ATA_MISCCTL_RSTMODEP        , 1) |
 287          * (ATA_MISCCTL_RESETP          , 0) |
 288          * (ATA_MISCCTL_TIMORIDE        , 1)
 289          */
 290         writel(0x201, base + BK3710_MISCCTL);
 291
 292         /*
 293          * IORDYTMP IORDY Timer for Primary Register
 294          * (ATA_IORDYTMP_IORDYTMP     , 0xffff  )
 295          */
 296         writel(0xFFFF, base + BK3710_IORDYTMP);
 297
 298         /*
 299          * Configure BMISP Register
 300          * (ATA_BMISP_DMAEN1    , DISABLE )     |
 301          * (ATA_BMISP_DMAEN0    , DISABLE )     |
 302          * (ATA_BMISP_IORDYINT  , CLEAR)        |
 303          * (ATA_BMISP_INTRSTAT  , CLEAR)        |
 304          * (ATA_BMISP_DMAERROR  , CLEAR)
 305          */
 306         writew(0, base + BK3710_BMISP);
 307
 308         palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
 309         palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
 310 }
 311
 312 static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif)
 313 {
 314         return ATA_CBL_PATA80;
 315 }
 316
 317 static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif,
 318                                           const struct ide_port_info *d)
 319 {
 320         printk(KERN_INFO "    %s: MMIO-DMA\n", hwif->name);
 321
 322         if (ide_allocate_dma_engine(hwif))
 323                 return -1;
 324
 325         hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
 326
 327         return 0;
 328 }
 329
 330 static const struct ide_port_ops palm_bk3710_ports_ops = {
 331         .set_pio_mode           = palm_bk3710_set_pio_mode,
 332         .set_dma_mode           = palm_bk3710_set_dma_mode,
 333         .cable_detect           = palm_bk3710_cable_detect,
 334 };
 335
 336 static struct ide_port_info __devinitdata palm_bk3710_port_info = {
 337         .init_dma               = palm_bk3710_init_dma,
 338         .port_ops               = &palm_bk3710_ports_ops,
 339         .dma_ops                = &sff_dma_ops,
 340         .host_flags             = IDE_HFLAG_MMIO,
 341         .pio_mask               = ATA_PIO4,
 342         .mwdma_mask             = ATA_MWDMA2,
 343 };
 344
 345 static int __init palm_bk3710_probe(struct platform_device *pdev)
 346 {
 347         struct clk *clk;
 348         struct resource *mem, *irq;
 349         unsigned long base, rate;
 350         int i, rc;
 351         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
 352
 353         clk = clk_get(&pdev->dev, "IDECLK");
 354         if (IS_ERR(clk))
 355                 return -ENODEV;
 356
 357         clk_enable(clk);
 358         rate = clk_get_rate(clk);
 359         ideclk_period = 1000000000UL / rate;
 360
 361         /* Register the IDE interface with Linux ATA Interface */
 362         memset(&hw, 0, sizeof(hw));
 363
 364         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 365         if (mem == NULL) {
 366                 printk(KERN_ERR "failed to get memory region resource\n");
 367                 return -ENODEV;
 368         }
 369
 370         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 371         if (irq == NULL) {
 372                 printk(KERN_ERR "failed to get IRQ resource\n");
 373                 return -ENODEV;
 374         }
 375
 376         if (request_mem_region(mem->start, mem->end - mem->start + 1,
 377                                "palm_bk3710") == NULL) {
 378                 printk(KERN_ERR "failed to request memory region\n");
 379                 return -EBUSY;
 380         }
 381
 382         base = IO_ADDRESS(mem->start);
 383
 384         /* Configure the Palm Chip controller */
 385         palm_bk3710_chipinit((void __iomem *)base);
 386
 387         for (i = 0; i < IDE_NR_PORTS - 2; i++)
 388                 hw.io_ports_array[i] = base + IDE_PALM_ATA_PRI_REG_OFFSET + i;
 389         hw.io_ports.ctl_addr = base + IDE_PALM_ATA_PRI_CTL_OFFSET;
 390         hw.irq = irq->start;
 391         hw.dev = &pdev->dev;
 392         hw.chipset = ide_palm3710;
 393
 394         palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
 395                                                              ATA_UDMA5;
 396
 397         rc = ide_host_add(&palm_bk3710_port_info, hws, NULL);
 398         if (rc)
 399                 goto out;
 400
 401         return 0;
 402 out:
 403         printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
 404         return rc;
 405 }
 406
 407 /* work with hotplug and coldplug */
 408 MODULE_ALIAS("platform:palm_bk3710");
 409
 410 static struct platform_driver platform_bk_driver = {
 411         .driver = {
 412                 .name = "palm_bk3710",
 413                 .owner = THIS_MODULE,
 414         },
 415 };
 416
 417 static int __init palm_bk3710_init(void)
 418 {
 419         return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe);
 420 }
 421
 422 module_init(palm_bk3710_init);
 423 MODULE_LICENSE("GPL");