OMAP3: SR: Reset voltage level on SR disable
[linux-ginger.git] / arch / arm / mach-footbridge / dc21285-timer.c
blobda35bc5c5ccc527a139852843fd3702efb8e116f
1 /*
2 * linux/arch/arm/mach-footbridge/dc21285-timer.c
4 * Copyright (C) 1998 Russell King.
5 * Copyright (C) 1998 Phil Blundell
6 */
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/spinlock.h>
12 #include <asm/irq.h>
14 #include <asm/hardware/dec21285.h>
15 #include <asm/mach/time.h>
17 #include "common.h"
20 * Footbridge timer 1 support.
22 static unsigned long timer1_latch;
24 static unsigned long timer1_gettimeoffset (void)
26 unsigned long value = timer1_latch - *CSR_TIMER1_VALUE;
28 return ((tick_nsec / 1000) * value) / timer1_latch;
31 static irqreturn_t
32 timer1_interrupt(int irq, void *dev_id)
34 *CSR_TIMER1_CLR = 0;
36 timer_tick();
38 return IRQ_HANDLED;
41 static struct irqaction footbridge_timer_irq = {
42 .name = "Timer1 timer tick",
43 .handler = timer1_interrupt,
44 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
48 * Set up timer interrupt.
50 static void __init footbridge_timer_init(void)
52 timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
54 *CSR_TIMER1_CLR = 0;
55 *CSR_TIMER1_LOAD = timer1_latch;
56 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16;
58 setup_irq(IRQ_TIMER1, &footbridge_timer_irq);
60 isa_rtc_init();
63 struct sys_timer footbridge_timer = {
64 .init = footbridge_timer_init,
65 .offset = timer1_gettimeoffset,