arch/arm/mach-loki/include/mach/loki.h

   1 /*
   2  * arch/arm/mach-loki/include/mach/loki.h
   3  *
   4  * Generic definitions for Marvell Loki (88RC8480) SoC flavors
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #ifndef __ASM_ARCH_LOKI_H
  12 #define __ASM_ARCH_LOKI_H
  13
  14 /*
  15  * Marvell Loki (88RC8480) address maps.
  16  *
  17  * phys
  18  * d0000000     on-chip peripheral registers
  19  * e0000000     PCIe 0 Memory space
  20  * e8000000     PCIe 1 Memory space
  21  * f0000000     PCIe 0 I/O space
  22  * f0100000     PCIe 1 I/O space
  23  *
  24  * virt         phys            size
  25  * fed00000     d0000000        1M      on-chip peripheral registers
  26  * fee00000     f0000000        64K     PCIe 0 I/O space
  27  * fef00000     f0100000        64K     PCIe 1 I/O space
  28  */
  29
  30 #define LOKI_REGS_PHYS_BASE             0xd0000000
  31 #define LOKI_REGS_VIRT_BASE             0xfed00000
  32 #define LOKI_REGS_SIZE                  SZ_1M
  33
  34 #define LOKI_PCIE0_IO_PHYS_BASE         0xf0000000
  35 #define LOKI_PCIE0_IO_VIRT_BASE         0xfee00000
  36 #define LOKI_PCIE0_IO_BUS_BASE          0x00000000
  37 #define LOKI_PCIE0_IO_SIZE              SZ_64K
  38
  39 #define LOKI_PCIE1_IO_PHYS_BASE         0xf0100000
  40 #define LOKI_PCIE1_IO_VIRT_BASE         0xfef00000
  41 #define LOKI_PCIE1_IO_BUS_BASE          0x00000000
  42 #define LOKI_PCIE1_IO_SIZE              SZ_64K
  43
  44 #define LOKI_PCIE0_MEM_PHYS_BASE        0xe0000000
  45 #define LOKI_PCIE0_MEM_SIZE             SZ_128M
  46
  47 #define LOKI_PCIE1_MEM_PHYS_BASE        0xe8000000
  48 #define LOKI_PCIE1_MEM_SIZE             SZ_128M
  49
  50 /*
  51  * Register Map
  52  */
  53 #define DEV_BUS_PHYS_BASE       (LOKI_REGS_PHYS_BASE | 0x10000)
  54 #define DEV_BUS_VIRT_BASE       (LOKI_REGS_VIRT_BASE | 0x10000)
  55 #define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
  56 #define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
  57 #define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
  58 #define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
  59
  60 #define BRIDGE_VIRT_BASE        (LOKI_REGS_VIRT_BASE | 0x20000)
  61
  62 #define PCIE0_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x30000)
  63
  64 #define PCIE1_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x40000)
  65
  66 #define SAS0_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x80000)
  67
  68 #define SAS1_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x90000)
  69
  70 #define GE0_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xa0000)
  71 #define GE0_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xa0000)
  72
  73 #define GE1_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xb0000)
  74 #define GE1_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xb0000)
  75
  76 #define DDR_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xf0000)
  77 #define DDR_REG(x)              (DDR_VIRT_BASE | (x))
  78
  79
  80 #define GPIO_MAX                8
  81
  82
  83 #endif