arch/arm/mach-omap2/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap2/irq.c
   3  *
   4  * Interrupt handler for OMAP2 boards.
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License. See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <mach/hardware.h>
  18 #include <asm/mach/irq.h>
  19
  20
  21 /* selected INTC register offsets */
  22
  23 #define INTC_REVISION           0x0000
  24 #define INTC_SYSCONFIG          0x0010
  25 #define INTC_SYSSTATUS          0x0014
  26 #define INTC_SIR                0x0040
  27 #define INTC_CONTROL            0x0048
  28 #define INTC_PROTECTION         0x004C
  29 #define INTC_IDLE               0x0050
  30 #define INTC_THRESHOLD          0x0068
  31 #define INTC_MIR0               0x0084
  32 #define INTC_MIR_CLEAR0         0x0088
  33 #define INTC_MIR_SET0           0x008c
  34 #define INTC_PENDING_IRQ0       0x0098
  35 /* Number of IRQ state bits in each MIR register */
  36 #define IRQ_BITS_PER_REG        32
  37
  38 /*
  39  * OMAP2 has a number of different interrupt controllers, each interrupt
  40  * controller is identified as its own "bank". Register definitions are
  41  * fairly consistent for each bank, but not all registers are implemented
  42  * for each bank.. when in doubt, consult the TRM.
  43  */
  44 static struct omap_irq_bank {
  45         void __iomem *base_reg;
  46         unsigned int nr_irqs;
  47 } __attribute__ ((aligned(4))) irq_banks[] = {
  48         {
  49                 /* MPU INTC */
  50                 .base_reg       = 0,
  51                 .nr_irqs        = 96,
  52         },
  53 };
  54
  55 /* Structure to save interrupt controller context */
  56 struct omap3_intc_regs {
  57         u32 sysconfig;
  58         u32 protection;
  59         u32 idle;
  60         u32 threshold;
  61         u32 ilr[INTCPS_NR_IRQS];
  62         u32 mir[INTCPS_NR_MIR_REGS];
  63 };
  64
  65 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
  66
  67 /* INTC bank register get/set */
  68
  69 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
  70 {
  71         __raw_writel(val, bank->base_reg + reg);
  72 }
  73
  74 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
  75 {
  76         return __raw_readl(bank->base_reg + reg);
  77 }
  78
  79 static int previous_irq;
  80
  81 /*
  82  * On 34xx we can get occasional spurious interrupts if the ack from
  83  * an interrupt handler does not get posted before we unmask. Warn about
  84  * the interrupt handlers that need to flush posted writes.
  85  */
  86 static int omap_check_spurious(unsigned int irq)
  87 {
  88         u32 sir, spurious;
  89
  90         sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
  91         spurious = sir >> 7;
  92
  93         if (spurious) {
  94                 printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
  95                                         "posted write for irq %i\n",
  96                                         irq, sir, previous_irq);
  97                 return spurious;
  98         }
  99
 100         return 0;
 101 }
 102
 103 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
 104 static void omap_ack_irq(unsigned int irq)
 105 {
 106         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
 107 }
 108
 109 static void omap_mask_irq(unsigned int irq)
 110 {
 111         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 112
 113         if (cpu_is_omap34xx()) {
 114                 int spurious = 0;
 115
 116                 /*
 117                  * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
 118                  * it is the highest irq number?
 119                  */
 120                 if (irq == INT_34XX_GPT12_IRQ)
 121                         spurious = omap_check_spurious(irq);
 122
 123                 if (!spurious)
 124                         previous_irq = irq;
 125         }
 126
 127         irq &= (IRQ_BITS_PER_REG - 1);
 128
 129         intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
 130 }
 131
 132 static void omap_unmask_irq(unsigned int irq)
 133 {
 134         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 135
 136         irq &= (IRQ_BITS_PER_REG - 1);
 137
 138         intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
 139 }
 140
 141 static void omap_mask_ack_irq(unsigned int irq)
 142 {
 143         omap_mask_irq(irq);
 144         omap_ack_irq(irq);
 145 }
 146
 147 static struct irq_chip omap_irq_chip = {
 148         .name   = "INTC",
 149         .ack    = omap_mask_ack_irq,
 150         .mask   = omap_mask_irq,
 151         .unmask = omap_unmask_irq,
 152 };
 153
 154 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 155 {
 156         unsigned long tmp;
 157
 158         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
 159         printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
 160                          "(revision %ld.%ld) with %d interrupts\n",
 161                          bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 162
 163         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
 164         tmp |= 1 << 1;  /* soft reset */
 165         intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
 166
 167         while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
 168                 /* Wait for reset to complete */;
 169
 170         /* Enable autoidle */
 171         intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
 172 }
 173
 174 int omap_irq_pending(void)
 175 {
 176         int i;
 177
 178         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 179                 struct omap_irq_bank *bank = irq_banks + i;
 180                 int irq;
 181
 182                 for (irq = 0; irq < bank->nr_irqs; irq += 32)
 183                         if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
 184                                                ((irq >> 5) << 5)))
 185                                 return 1;
 186         }
 187         return 0;
 188 }
 189
 190 void __init omap_init_irq(void)
 191 {
 192         unsigned long nr_of_irqs = 0;
 193         unsigned int nr_banks = 0;
 194         int i;
 195
 196         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 197                 unsigned long base;
 198                 struct omap_irq_bank *bank = irq_banks + i;
 199
 200                 if (cpu_is_omap24xx())
 201                         base = OMAP24XX_IC_BASE;
 202                 else if (cpu_is_omap34xx())
 203                         base = OMAP34XX_IC_BASE;
 204
 205                 /* Static mapping, never released */
 206                 bank->base_reg = ioremap(base, SZ_4K);
 207                 if (!bank->base_reg) {
 208                         printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
 209                         continue;
 210                 }
 211
 212                 omap_irq_bank_init_one(bank);
 213
 214                 nr_of_irqs += bank->nr_irqs;
 215                 nr_banks++;
 216         }
 217
 218         printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
 219                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 220
 221         for (i = 0; i < nr_of_irqs; i++) {
 222                 set_irq_chip(i, &omap_irq_chip);
 223                 set_irq_handler(i, handle_level_irq);
 224                 set_irq_flags(i, IRQF_VALID);
 225         }
 226 }
 227
 228 #ifdef CONFIG_ARCH_OMAP3
 229 void omap_intc_save_context(void)
 230 {
 231         int ind = 0, i = 0;
 232         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
 233                 struct omap_irq_bank *bank = irq_banks + ind;
 234                 intc_context[ind].sysconfig =
 235                         intc_bank_read_reg(bank, INTC_SYSCONFIG);
 236                 intc_context[ind].protection =
 237                         intc_bank_read_reg(bank, INTC_PROTECTION);
 238                 intc_context[ind].idle =
 239                         intc_bank_read_reg(bank, INTC_IDLE);
 240                 intc_context[ind].threshold =
 241                         intc_bank_read_reg(bank, INTC_THRESHOLD);
 242                 for (i = 0; i < INTCPS_NR_IRQS; i++)
 243                         intc_context[ind].ilr[i] =
 244                                 intc_bank_read_reg(bank, (0x100 + 0x4*i));
 245                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 246                         intc_context[ind].mir[i] =
 247                                 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
 248                                 (0x20 * i));
 249         }
 250 }
 251
 252 void omap_intc_restore_context(void)
 253 {
 254         int ind = 0, i = 0;
 255
 256         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
 257                 struct omap_irq_bank *bank = irq_banks + ind;
 258                 intc_bank_write_reg(intc_context[ind].sysconfig,
 259                                         bank, INTC_SYSCONFIG);
 260                 intc_bank_write_reg(intc_context[ind].sysconfig,
 261                                         bank, INTC_SYSCONFIG);
 262                 intc_bank_write_reg(intc_context[ind].protection,
 263                                         bank, INTC_PROTECTION);
 264                 intc_bank_write_reg(intc_context[ind].idle,
 265                                         bank, INTC_IDLE);
 266                 intc_bank_write_reg(intc_context[ind].threshold,
 267                                         bank, INTC_THRESHOLD);
 268                 for (i = 0; i < INTCPS_NR_IRQS; i++)
 269                         intc_bank_write_reg(intc_context[ind].ilr[i],
 270                                 bank, (0x100 + 0x4*i));
 271                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 272                         intc_bank_write_reg(intc_context[ind].mir[i],
 273                                  &irq_banks[0], INTC_MIR0 + (0x20 * i));
 274         }
 275         /* MIRs are saved and restore with other PRCM registers */
 276 }
 277 #endif /* CONFIG_ARCH_OMAP3 */