arch/arm/mach-omap2/smartreflex.h

   1 #ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
   2 #define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
   3 /*
   4  * linux/arch/arm/mach-omap2/smartreflex.h
   5  *
   6  * Copyright (C) 2008 Nokia Corporation
   7  * Kalle Jokiniemi
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Lesly A M <x0080970@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #define PHY_TO_OFF_PM_MASTER(p)         (p - 0x36)
  18 #define PHY_TO_OFF_PM_RECIEVER(p)       (p - 0x5b)
  19 #define PHY_TO_OFF_PM_INT(p)            (p - 0x2e)
  20
  21 /* SMART REFLEX REG ADDRESS OFFSET */
  22 #define SRCONFIG        0x00
  23 #define SRSTATUS        0x04
  24 #define SENVAL          0x08
  25 #define SENMIN          0x0C
  26 #define SENMAX          0x10
  27 #define SENAVG          0x14
  28 #define AVGWEIGHT       0x18
  29 #define NVALUERECIPROCAL        0x1C
  30 #define SENERROR        0x20
  31 #define ERRCONFIG       0x24
  32
  33 /* SR Modules */
  34 #define SR1             1
  35 #define SR2             2
  36
  37 #define SR_FAIL         1
  38 #define SR_PASS         0
  39
  40 #define SR_TRUE         1
  41 #define SR_FALSE        0
  42
  43 #define GAIN_MAXLIMIT   16
  44 #define R_MAXLIMIT      256
  45
  46 #define SR1_CLK_ENABLE  (0x1 << 6)
  47 #define SR2_CLK_ENABLE  (0x1 << 7)
  48
  49 /* PRM_VP1_CONFIG */
  50 #define PRM_VP1_CONFIG_ERROROFFSET      (0x00 << 24)
  51 #define PRM_VP1_CONFIG_ERRORGAIN        (0x20 << 16)
  52
  53 #define PRM_VP1_CONFIG_INITVOLTAGE      (0x30 << 8) /* 1.2 volt */
  54 #define PRM_VP1_CONFIG_TIMEOUTEN        (0x1 << 3)
  55 #define PRM_VP1_CONFIG_INITVDD          (0x1 << 2)
  56 #define PRM_VP1_CONFIG_FORCEUPDATE      (0x1 << 1)
  57 #define PRM_VP1_CONFIG_VPENABLE         (0x1 << 0)
  58
  59 /* PRM_VP1_VSTEPMIN */
  60 #define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN        (0x01F4 << 8)
  61 #define PRM_VP1_VSTEPMIN_VSTEPMIN               (0x01 << 0)
  62
  63 /* PRM_VP1_VSTEPMAX */
  64 #define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX        (0x01F4 << 8)
  65 #define PRM_VP1_VSTEPMAX_VSTEPMAX               (0x04 << 0)
  66
  67 /* PRM_VP1_VLIMITTO */
  68 #define PRM_VP1_VLIMITTO_VDDMAX         (0x3C << 24)
  69 #define PRM_VP1_VLIMITTO_VDDMIN         (0x0 << 16)
  70 #define PRM_VP1_VLIMITTO_TIMEOUT        (0xFFFF << 0)
  71
  72 /* PRM_VP2_CONFIG */
  73 #define PRM_VP2_CONFIG_ERROROFFSET      (0x00 << 24)
  74 #define PRM_VP2_CONFIG_ERRORGAIN        (0x20 << 16)
  75
  76 #define PRM_VP2_CONFIG_INITVOLTAGE      (0x30 << 8) /* 1.2 volt */
  77 #define PRM_VP2_CONFIG_TIMEOUTEN        (0x1 << 3)
  78 #define PRM_VP2_CONFIG_INITVDD          (0x1 << 2)
  79 #define PRM_VP2_CONFIG_FORCEUPDATE      (0x1 << 1)
  80 #define PRM_VP2_CONFIG_VPENABLE         (0x1 << 0)
  81
  82 /* PRM_VP2_VSTEPMIN */
  83 #define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN        (0x01F4 << 8)
  84 #define PRM_VP2_VSTEPMIN_VSTEPMIN               (0x01 << 0)
  85
  86 /* PRM_VP2_VSTEPMAX */
  87 #define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX        (0x01F4 << 8)
  88 #define PRM_VP2_VSTEPMAX_VSTEPMAX               (0x04 << 0)
  89
  90 /* PRM_VP2_VLIMITTO */
  91 #define PRM_VP2_VLIMITTO_VDDMAX         (0x2C << 24)
  92 #define PRM_VP2_VLIMITTO_VDDMIN         (0x0 << 16)
  93 #define PRM_VP2_VLIMITTO_TIMEOUT        (0xFFFF << 0)
  94
  95 /* SRCONFIG */
  96 #define SR1_SRCONFIG_ACCUMDATA          (0x1F4 << 22)
  97 #define SR2_SRCONFIG_ACCUMDATA          (0x1F4 << 22)
  98
  99 #define SRCLKLENGTH_12MHZ_SYSCLK        0x3C
 100 #define SRCLKLENGTH_13MHZ_SYSCLK        0x41
 101 #define SRCLKLENGTH_19MHZ_SYSCLK        0x60
 102 #define SRCLKLENGTH_26MHZ_SYSCLK        0x82
 103 #define SRCLKLENGTH_38MHZ_SYSCLK        0xC0
 104
 105 #define SRCONFIG_SRCLKLENGTH_SHIFT      12
 106 #define SRCONFIG_SENNENABLE_SHIFT       5
 107 #define SRCONFIG_SENPENABLE_SHIFT       3
 108
 109 #define SRCONFIG_SRENABLE               (0x01 << 11)
 110 #define SRCONFIG_SENENABLE              (0x01 << 10)
 111 #define SRCONFIG_ERRGEN_EN              (0x01 << 9)
 112 #define SRCONFIG_MINMAXAVG_EN           (0x01 << 8)
 113
 114 #define SRCONFIG_DELAYCTRL              (0x01 << 2)
 115 #define SRCONFIG_CLKCTRL                (0x00 << 0)
 116
 117 /* AVGWEIGHT */
 118 #define SR1_AVGWEIGHT_SENPAVGWEIGHT     (0x03 << 2)
 119 #define SR1_AVGWEIGHT_SENNAVGWEIGHT     (0x03 << 0)
 120
 121 #define SR2_AVGWEIGHT_SENPAVGWEIGHT     (0x01 << 2)
 122 #define SR2_AVGWEIGHT_SENNAVGWEIGHT     (0x01 << 0)
 123
 124 /* NVALUERECIPROCAL */
 125 #define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
 126 #define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
 127 #define NVALUERECIPROCAL_RNSENP_SHIFT   8
 128 #define NVALUERECIPROCAL_RNSENN_SHIFT   0
 129
 130 /* ERRCONFIG */
 131 #define SR_CLKACTIVITY_MASK             (0x03 << 20)
 132 #define SR_ERRWEIGHT_MASK               (0x07 << 16)
 133 #define SR_ERRMAXLIMIT_MASK             (0xFF << 8)
 134 #define SR_ERRMINLIMIT_MASK             (0xFF << 0)
 135
 136 #define SR_CLKACTIVITY_IOFF_FOFF        (0x00 << 20)
 137 #define SR_CLKACTIVITY_IOFF_FON         (0x02 << 20)
 138
 139 #define ERRCONFIG_VPBOUNDINTEN          (0x1 << 31)
 140 #define ERRCONFIG_VPBOUNDINTST          (0x1 << 30)
 141
 142 #define SR1_ERRWEIGHT                   (0x07 << 16)
 143 #define SR1_ERRMAXLIMIT                 (0x02 << 8)
 144 #define SR1_ERRMINLIMIT                 (0xFA << 0)
 145
 146 #define SR2_ERRWEIGHT                   (0x07 << 16)
 147 #define SR2_ERRMAXLIMIT                 (0x02 << 8)
 148 #define SR2_ERRMINLIMIT                 (0xF9 << 0)
 149
 150 /* T2 SMART REFLEX */
 151 #define R_SRI2C_SLAVE_ADDR              0x12
 152 #define R_VDD1_SR_CONTROL               0x00
 153 #define R_VDD2_SR_CONTROL               0x01
 154 #define T2_SMPS_UPDATE_DELAY            360     /* In uSec */
 155
 156 /* Vmode control */
 157 #define R_DCDC_GLOBAL_CFG       PHY_TO_OFF_PM_RECIEVER(0x61)
 158
 159 #define R_VDD1_VSEL             PHY_TO_OFF_PM_RECIEVER(0xb9)
 160 #define R_VDD1_VMODE_CFG        PHY_TO_OFF_PM_RECIEVER(0xba)
 161 #define R_VDD1_VFLOOR           PHY_TO_OFF_PM_RECIEVER(0xbb)
 162 #define R_VDD1_VROOF            PHY_TO_OFF_PM_RECIEVER(0xbc)
 163 #define R_VDD1_STEP             PHY_TO_OFF_PM_RECIEVER(0xbd)
 164
 165 #define R_VDD2_VSEL             PHY_TO_OFF_PM_RECIEVER(0xc7)
 166 #define R_VDD2_VMODE_CFG        PHY_TO_OFF_PM_RECIEVER(0xc8)
 167 #define R_VDD2_VFLOOR           PHY_TO_OFF_PM_RECIEVER(0xc9)
 168 #define R_VDD2_VROOF            PHY_TO_OFF_PM_RECIEVER(0xca)
 169 #define R_VDD2_STEP             PHY_TO_OFF_PM_RECIEVER(0xcb)
 170
 171 /* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE values */
 172 #define DCDC_GLOBAL_CFG_ENABLE_SRFLX    0x08
 173
 174 /* VDDs*/
 175 #define PRCM_VDD1       1
 176 #define PRCM_VDD2       2
 177 #define PRCM_MAX_SYSC_REGS 30
 178
 179 /*
 180  * XXX: These should be removed/moved from here once we have a working DVFS
 181  * implementation in place
 182  */
 183 #define AT_3430         1       /*3430 ES 1.0 */
 184 #define AT_3430_ES2     2       /*3430 ES 2.0 */
 185
 186 #define ID_OPP                  0xE2    /*OPP*/
 187
 188 /* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
 189 #define OMAP_TYPE_SHIFT         28
 190 #define OMAP_TYPE_MASK          0xF
 191 /* OPP ID: bits: 0-4 for OPP number */
 192 #define OPP_NO_POS              0
 193 #define OPP_NO_MASK             0x1F
 194 /* OPP ID: bits: 5-6 for VDD */
 195 #define VDD_NO_POS              5
 196 #define VDD_NO_MASK             0x3
 197 /* Other IDs: bits 20-27 for ID type */
 198 /* These IDs have bits 25,26,27 as 1 */
 199 #define OTHER_ID_TYPE_SHIFT             20
 200 #define OTHER_ID_TYPE_MASK              0xFF
 201
 202 #define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
 203 #define ID_OPP_NO(X)     ((X & OPP_NO_MASK) << OPP_NO_POS)
 204 #define ID_VDD(X)        ((X & VDD_NO_MASK) << VDD_NO_POS)
 205 #define OMAP(X)          ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
 206 #define get_opp_no(X)    ((X >> OPP_NO_POS) & OPP_NO_MASK)
 207 #define get_vdd(X)       ((X >> VDD_NO_POS) & VDD_NO_MASK)
 208
 209 /* VDD1 OPPs */
 210 #define PRCM_VDD1_OPP1          (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 211                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
 212 #define PRCM_VDD1_OPP2          (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 213                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
 214 #define PRCM_VDD1_OPP3          (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 215                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
 216 #define PRCM_VDD1_OPP4          (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 217                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
 218 #define PRCM_VDD1_OPP5          (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 219                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
 220 #define PRCM_NO_VDD1_OPPS       5
 221
 222
 223 /* VDD2 OPPs */
 224 #define PRCM_VDD2_OPP1          (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 225                                         ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
 226 #define PRCM_VDD2_OPP2          (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 227                                         ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
 228 #define PRCM_VDD2_OPP3          (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 229                                         ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
 230 #define PRCM_NO_VDD2_OPPS       3
 231 /* XXX: end remove/move */
 232
 233 /* XXX: find more appropriate place for these once DVFS is in place */
 234 extern u32 current_vdd1_opp;
 235 extern u32 current_vdd2_opp;
 236
 237 #ifdef CONFIG_OMAP_SMARTREFLEX_TESTING
 238 #define SR_TESTING_NVALUES      1
 239 #else
 240 #define SR_TESTING_NVALUES      0
 241 #endif
 242
 243 /*
 244  * Smartreflex module enable/disable interface.
 245  * NOTE: if smartreflex is not enabled from sysfs, these functions will not
 246  * do anything.
 247  */
 248 #ifdef CONFIG_OMAP_SMARTREFLEX
 249 void enable_smartreflex(int srid);
 250 void disable_smartreflex(int srid);
 251 int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel);
 252 void sr_start_vddautocomap(int srid, u32 target_opp_no);
 253 int sr_stop_vddautocomap(int srid);
 254 #else
 255 static inline void enable_smartreflex(int srid) {}
 256 static inline void disable_smartreflex(int srid) {}
 257 #endif
 258
 259 #endif