arch/arm/mach-omap2/timer-gp.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer-gp.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38
  39 #include <asm/mach/time.h>
  40 #include <plat/dmtimer.h>
  41 #include <asm/localtimer.h>
  42
  43 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  44 #define MAX_GPTIMER_ID          12
  45
  46 static struct omap_dm_timer *gptimer;
  47 static struct clock_event_device clockevent_gpt;
  48 static u8 __initdata gptimer_id = 1;
  49 static u8 __initdata inited;
  50 struct omap_dm_timer *gptimer_wakeup;
  51
  52 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  53 {
  54         struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
  55         struct clock_event_device *evt = &clockevent_gpt;
  56
  57         omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
  58
  59         evt->event_handler(evt);
  60         return IRQ_HANDLED;
  61 }
  62
  63 static struct irqaction omap2_gp_timer_irq = {
  64         .name           = "gp timer",
  65         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  66         .handler        = omap2_gp_timer_interrupt,
  67 };
  68
  69 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  70                                          struct clock_event_device *evt)
  71 {
  72         omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
  73
  74         return 0;
  75 }
  76
  77 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
  78                                     struct clock_event_device *evt)
  79 {
  80         u32 period;
  81
  82         omap_dm_timer_stop(gptimer);
  83
  84         switch (mode) {
  85         case CLOCK_EVT_MODE_PERIODIC:
  86                 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
  87                 period -= 1;
  88                 if (cpu_is_omap44xx())
  89                         period = 0xff;  /* FIXME: */
  90                 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
  91                 break;
  92         case CLOCK_EVT_MODE_ONESHOT:
  93                 break;
  94         case CLOCK_EVT_MODE_UNUSED:
  95         case CLOCK_EVT_MODE_SHUTDOWN:
  96         case CLOCK_EVT_MODE_RESUME:
  97                 break;
  98         }
  99 }
 100
 101 static struct clock_event_device clockevent_gpt = {
 102         .name           = "gp timer",
 103         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 104         .shift          = 32,
 105         .set_next_event = omap2_gp_timer_set_next_event,
 106         .set_mode       = omap2_gp_timer_set_mode,
 107 };
 108
 109 /**
 110  * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
 111  * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
 112  *
 113  * Define the GPTIMER that the system should use for the tick timer.
 114  * Meant to be called from board-*.c files in the event that GPTIMER1, the
 115  * default, is unsuitable.  Returns -EINVAL on error or 0 on success.
 116  */
 117 int __init omap2_gp_clockevent_set_gptimer(u8 id)
 118 {
 119         if (id < 1 || id > MAX_GPTIMER_ID)
 120                 return -EINVAL;
 121
 122         BUG_ON(inited);
 123
 124         gptimer_id = id;
 125
 126         return 0;
 127 }
 128
 129 static void __init omap2_gp_clockevent_init(void)
 130 {
 131         u32 tick_rate;
 132         int src;
 133
 134         inited = 1;
 135
 136         gptimer = omap_dm_timer_request_specific(gptimer_id);
 137         BUG_ON(gptimer == NULL);
 138         gptimer_wakeup = gptimer;
 139
 140 #if defined(CONFIG_OMAP_32K_TIMER)
 141         src = OMAP_TIMER_SRC_32_KHZ;
 142 #else
 143         src = OMAP_TIMER_SRC_SYS_CLK;
 144         WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
 145              "secure 32KiHz clock source\n");
 146 #endif
 147
 148         if (gptimer_id != 12)
 149                 WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
 150                      "timer-gp: omap_dm_timer_set_source() failed\n");
 151
 152         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
 153         if (cpu_is_omap44xx())
 154                 /* Assuming 32kHz clk is driving GPT1 */
 155                 tick_rate = 32768;      /* FIXME: */
 156
 157         pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
 158                 gptimer_id, tick_rate);
 159
 160         omap2_gp_timer_irq.dev_id = (void *)gptimer;
 161         setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
 162         omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
 163
 164         clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
 165                                      clockevent_gpt.shift);
 166         clockevent_gpt.max_delta_ns =
 167                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 168         clockevent_gpt.min_delta_ns =
 169                 clockevent_delta2ns(3, &clockevent_gpt);
 170                 /* Timer internal resynch latency. */
 171
 172         clockevent_gpt.cpumask = cpumask_of(0);
 173         clockevents_register_device(&clockevent_gpt);
 174 }
 175
 176 /* Clocksource code */
 177
 178 #ifdef CONFIG_OMAP_32K_TIMER
 179 /*
 180  * When 32k-timer is enabled, don't use GPTimer for clocksource
 181  * instead, just leave default clocksource which uses the 32k
 182  * sync counter.  See clocksource setup in see plat-omap/common.c.
 183  */
 184
 185 static inline void __init omap2_gp_clocksource_init(void) {}
 186 #else
 187 /*
 188  * clocksource
 189  */
 190 static struct omap_dm_timer *gpt_clocksource;
 191 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 192 {
 193         return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
 194 }
 195
 196 static struct clocksource clocksource_gpt = {
 197         .name           = "gp timer",
 198         .rating         = 300,
 199         .read           = clocksource_read_cycles,
 200         .mask           = CLOCKSOURCE_MASK(32),
 201         .shift          = 24,
 202         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 203 };
 204
 205 /* Setup free-running counter for clocksource */
 206 static void __init omap2_gp_clocksource_init(void)
 207 {
 208         static struct omap_dm_timer *gpt;
 209         u32 tick_rate, tick_period;
 210         static char err1[] __initdata = KERN_ERR
 211                 "%s: failed to request dm-timer\n";
 212         static char err2[] __initdata = KERN_ERR
 213                 "%s: can't register clocksource!\n";
 214
 215         gpt = omap_dm_timer_request();
 216         if (!gpt)
 217                 printk(err1, clocksource_gpt.name);
 218         gpt_clocksource = gpt;
 219
 220         omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
 221         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
 222         tick_period = (tick_rate / HZ) - 1;
 223
 224         omap_dm_timer_set_load_start(gpt, 1, 0);
 225
 226         clocksource_gpt.mult =
 227                 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
 228         if (clocksource_register(&clocksource_gpt))
 229                 printk(err2, clocksource_gpt.name);
 230 }
 231 #endif
 232
 233 static void __init omap2_gp_timer_init(void)
 234 {
 235 #ifdef CONFIG_LOCAL_TIMERS
 236         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
 237         BUG_ON(!twd_base);
 238 #endif
 239         omap_dm_timer_init();
 240
 241         omap2_gp_clockevent_init();
 242         omap2_gp_clocksource_init();
 243 }
 244
 245 struct sys_timer omap_timer = {
 246         .init   = omap2_gp_timer_init,
 247 };