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[ARM] Merge most of the PXA work for initial merge
[linux-ginger.git] / drivers / ata / pata_icside.c
blobcf9e9848f8b5a06f55180ddb3ff780fd4968ce1f
1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/init.h>
4 #include <linux/blkdev.h>
5 #include <scsi/scsi_host.h>
6 #include <linux/ata.h>
7 #include <linux/libata.h>
8
9 #include <asm/dma.h>
10 #include <asm/ecard.h>
11
12 #define DRV_NAME "pata_icside"
13
14 #define ICS_IDENT_OFFSET 0x2280
15
16 #define ICS_ARCIN_V5_INTRSTAT 0x0000
17 #define ICS_ARCIN_V5_INTROFFSET 0x0004
18
19 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
20 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
21 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
22 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
23
24 struct portinfo {
25 unsigned int dataoffset;
26 unsigned int ctrloffset;
27 unsigned int stepping;
28 };
29
30 static const struct portinfo pata_icside_portinfo_v5 = {
31 .dataoffset = 0x2800,
32 .ctrloffset = 0x2b80,
33 .stepping = 6,
34 };
35
36 static const struct portinfo pata_icside_portinfo_v6_1 = {
37 .dataoffset = 0x2000,
38 .ctrloffset = 0x2380,
39 .stepping = 6,
40 };
41
42 static const struct portinfo pata_icside_portinfo_v6_2 = {
43 .dataoffset = 0x3000,
44 .ctrloffset = 0x3380,
45 .stepping = 6,
46 };
47
48 #define PATA_ICSIDE_MAX_SG 128
49
50 struct pata_icside_state {
51 void __iomem *irq_port;
52 void __iomem *ioc_base;
53 unsigned int type;
54 unsigned int dma;
55 struct {
56 u8 port_sel;
57 u8 disabled;
58 unsigned int speed[ATA_MAX_DEVICES];
59 } port[2];
60 struct scatterlist sg[PATA_ICSIDE_MAX_SG];
61 };
62
63 struct pata_icside_info {
64 struct pata_icside_state *state;
65 struct expansion_card *ec;
66 void __iomem *base;
67 void __iomem *irqaddr;
68 unsigned int irqmask;
69 const expansioncard_ops_t *irqops;
70 unsigned int mwdma_mask;
71 unsigned int nr_ports;
72 const struct portinfo *port[2];
73 unsigned long raw_base;
74 unsigned long raw_ioc_base;
75 };
76
77 #define ICS_TYPE_A3IN 0
78 #define ICS_TYPE_A3USER 1
79 #define ICS_TYPE_V6 3
80 #define ICS_TYPE_V5 15
81 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
82
83 /* ---------------- Version 5 PCB Support Functions --------------------- */
84 /* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
85 * Purpose : enable interrupts from card
86 */
87 static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
88 {
89 struct pata_icside_state *state = ec->irq_data;
90
91 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
92 }
93
94 /* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
95 * Purpose : disable interrupts from card
96 */
97 static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
98 {
99 struct pata_icside_state *state = ec->irq_data;
100
101 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
102 }
103
104 static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
105 .irqenable = pata_icside_irqenable_arcin_v5,
106 .irqdisable = pata_icside_irqdisable_arcin_v5,
107 };
108
109
110 /* ---------------- Version 6 PCB Support Functions --------------------- */
111 /* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
112 * Purpose : enable interrupts from card
113 */
114 static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
115 {
116 struct pata_icside_state *state = ec->irq_data;
117 void __iomem *base = state->irq_port;
118
119 if (!state->port[0].disabled)
120 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
121 if (!state->port[1].disabled)
122 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
123 }
124
125 /* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
126 * Purpose : disable interrupts from card
127 */
128 static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
129 {
130 struct pata_icside_state *state = ec->irq_data;
131
132 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
133 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
134 }
135
136 /* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
137 * Purpose : detect an active interrupt from card
138 */
139 static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
140 {
141 struct pata_icside_state *state = ec->irq_data;
142
143 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
144 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
145 }
146
147 static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
148 .irqenable = pata_icside_irqenable_arcin_v6,
149 .irqdisable = pata_icside_irqdisable_arcin_v6,
150 .irqpending = pata_icside_irqpending_arcin_v6,
151 };
152
153
154 /*
155 * SG-DMA support.
156 *
157 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
158 * There is only one DMA controller per card, which means that only
159 * one drive can be accessed at one time. NOTE! We do not enforce that
160 * here, but we rely on the main IDE driver spotting that both
161 * interfaces use the same IRQ, which should guarantee this.
162 */
163
164 /*
165 * Configure the IOMD to give the appropriate timings for the transfer
166 * mode being requested. We take the advice of the ATA standards, and
167 * calculate the cycle time based on the transfer mode, and the EIDE
168 * MW DMA specs that the drive provides in the IDENTIFY command.
169 *
170 * We have the following IOMD DMA modes to choose from:
171 *
172 * Type Active Recovery Cycle
173 * A 250 (250) 312 (550) 562 (800)
174 * B 187 (200) 250 (550) 437 (750)
175 * C 125 (125) 125 (375) 250 (500)
176 * D 62 (50) 125 (375) 187 (425)
177 *
178 * (figures in brackets are actual measured timings on DIOR/DIOW)
179 *
180 * However, we also need to take care of the read/write active and
181 * recovery timings:
182 *
183 * Read Write
184 * Mode Active -- Recovery -- Cycle IOMD type
185 * MW0 215 50 215 480 A
186 * MW1 80 50 50 150 C
187 * MW2 70 25 25 120 C
188 */
189 static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
190 {
191 struct pata_icside_state *state = ap->host->private_data;
192 struct ata_timing t;
193 unsigned int cycle;
194 char iomd_type;
195
196 /*
197 * DMA is based on a 16MHz clock
198 */
199 if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
200 return;
201
202 /*
203 * Choose the IOMD cycle timing which ensure that the interface
204 * satisfies the measured active, recovery and cycle times.
205 */
206 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
207 iomd_type = 'D', cycle = 187;
208 else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
209 iomd_type = 'C', cycle = 250;
210 else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
211 iomd_type = 'B', cycle = 437;
212 else
213 iomd_type = 'A', cycle = 562;
214
215 ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n",
216 t.active, t.recover, t.cycle, iomd_type);
217
218 state->port[ap->port_no].speed[adev->devno] = cycle;
219 }
220
221 static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
222 {
223 struct ata_port *ap = qc->ap;
224 struct pata_icside_state *state = ap->host->private_data;
225 struct scatterlist *sg, *rsg = state->sg;
226 unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
227 unsigned int si;
228
229 /*
230 * We are simplex; BUG if we try to fiddle with DMA
231 * while it's active.
232 */
233 BUG_ON(dma_channel_active(state->dma));
234
235 /*
236 * Copy ATAs scattered sg list into a contiguous array of sg
237 */
238 for_each_sg(qc->sg, sg, qc->n_elem, si) {
239 memcpy(rsg, sg, sizeof(*sg));
240 rsg++;
241 }
242
243 /*
244 * Route the DMA signals to the correct interface
245 */
246 writeb(state->port[ap->port_no].port_sel, state->ioc_base);
247
248 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
249 set_dma_sg(state->dma, state->sg, rsg - state->sg);
250 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
251
252 /* issue r/w command */
253 ap->ops->sff_exec_command(ap, &qc->tf);
254 }
255
256 static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
257 {
258 struct ata_port *ap = qc->ap;
259 struct pata_icside_state *state = ap->host->private_data;
260
261 BUG_ON(dma_channel_active(state->dma));
262 enable_dma(state->dma);
263 }
264
265 static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
266 {
267 struct ata_port *ap = qc->ap;
268 struct pata_icside_state *state = ap->host->private_data;
269
270 disable_dma(state->dma);
271
272 /* see ata_bmdma_stop */
273 ata_sff_dma_pause(ap);
274 }
275
276 static u8 pata_icside_bmdma_status(struct ata_port *ap)
277 {
278 struct pata_icside_state *state = ap->host->private_data;
279 void __iomem *irq_port;
280
281 irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
282 ICS_ARCIN_V6_INTRSTAT_1);
283
284 return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
285 }
286
287 static int icside_dma_init(struct pata_icside_info *info)
288 {
289 struct pata_icside_state *state = info->state;
290 struct expansion_card *ec = info->ec;
291 int i;
292
293 for (i = 0; i < ATA_MAX_DEVICES; i++) {
294 state->port[0].speed[i] = 480;
295 state->port[1].speed[i] = 480;
296 }
297
298 if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
299 state->dma = ec->dma;
300 info->mwdma_mask = 0x07; /* MW0..2 */
301 }
302
303 return 0;
304 }
305
306
307 static struct scsi_host_template pata_icside_sht = {
308 ATA_BASE_SHT(DRV_NAME),
309 .sg_tablesize = PATA_ICSIDE_MAX_SG,
310 .dma_boundary = ~0, /* no dma boundaries */
311 };
312
313 static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
314 {
315 struct ata_port *ap = link->ap;
316 struct pata_icside_state *state = ap->host->private_data;
317
318 if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
319 return ata_sff_postreset(link, classes);
320
321 state->port[ap->port_no].disabled = 1;
322
323 if (state->type == ICS_TYPE_V6) {
324 /*
325 * Disable interrupts from this port, otherwise we
326 * receive spurious interrupts from the floating
327 * interrupt line.
328 */
329 void __iomem *irq_port = state->irq_port +
330 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
331 readb(irq_port);
332 }
333 }
334
335 static struct ata_port_operations pata_icside_port_ops = {
336 .inherits = &ata_sff_port_ops,
337 /* no need to build any PRD tables for DMA */
338 .qc_prep = ata_noop_qc_prep,
339 .sff_data_xfer = ata_sff_data_xfer_noirq,
340 .bmdma_setup = pata_icside_bmdma_setup,
341 .bmdma_start = pata_icside_bmdma_start,
342 .bmdma_stop = pata_icside_bmdma_stop,
343 .bmdma_status = pata_icside_bmdma_status,
344
345 .cable_detect = ata_cable_40wire,
346 .set_dmamode = pata_icside_set_dmamode,
347 .postreset = pata_icside_postreset,
348 .post_internal_cmd = pata_icside_bmdma_stop,
349 };
350
351 static void __devinit
352 pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base,
353 struct pata_icside_info *info,
354 const struct portinfo *port)
355 {
356 struct ata_ioports *ioaddr = &ap->ioaddr;
357 void __iomem *cmd = base + port->dataoffset;
358
359 ioaddr->cmd_addr = cmd;
360 ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping);
361 ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping);
362 ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping);
363 ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping);
364 ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping);
365 ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping);
366 ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping);
367 ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping);
368 ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping);
369 ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping);
370
371 ioaddr->ctl_addr = base + port->ctrloffset;
372 ioaddr->altstatus_addr = ioaddr->ctl_addr;
373
374 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
375 info->raw_base + port->dataoffset,
376 info->raw_base + port->ctrloffset);
377
378 if (info->raw_ioc_base)
379 ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
380 }
381
382 static int __devinit pata_icside_register_v5(struct pata_icside_info *info)
383 {
384 struct pata_icside_state *state = info->state;
385 void __iomem *base;
386
387 base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
388 if (!base)
389 return -ENOMEM;
390
391 state->irq_port = base;
392
393 info->base = base;
394 info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
395 info->irqmask = 1;
396 info->irqops = &pata_icside_ops_arcin_v5;
397 info->nr_ports = 1;
398 info->port[0] = &pata_icside_portinfo_v5;
399
400 info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);
401
402 return 0;
403 }
404
405 static int __devinit pata_icside_register_v6(struct pata_icside_info *info)
406 {
407 struct pata_icside_state *state = info->state;
408 struct expansion_card *ec = info->ec;
409 void __iomem *ioc_base, *easi_base;
410 unsigned int sel = 0;
411
412 ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
413 if (!ioc_base)
414 return -ENOMEM;
415
416 easi_base = ioc_base;
417
418 if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
419 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
420 if (!easi_base)
421 return -ENOMEM;
422
423 /*
424 * Enable access to the EASI region.
425 */
426 sel = 1 << 5;
427 }
428
429 writeb(sel, ioc_base);
430
431 state->irq_port = easi_base;
432 state->ioc_base = ioc_base;
433 state->port[0].port_sel = sel;
434 state->port[1].port_sel = sel | 1;
435
436 info->base = easi_base;
437 info->irqops = &pata_icside_ops_arcin_v6;
438 info->nr_ports = 2;
439 info->port[0] = &pata_icside_portinfo_v6_1;
440 info->port[1] = &pata_icside_portinfo_v6_2;
441
442 info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
443 info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);
444
445 return icside_dma_init(info);
446 }
447
448 static int __devinit pata_icside_add_ports(struct pata_icside_info *info)
449 {
450 struct expansion_card *ec = info->ec;
451 struct ata_host *host;
452 int i;
453
454 if (info->irqaddr) {
455 ec->irqaddr = info->irqaddr;
456 ec->irqmask = info->irqmask;
457 }
458 if (info->irqops)
459 ecard_setirq(ec, info->irqops, info->state);
460
461 /*
462 * Be on the safe side - disable interrupts
463 */
464 ec->ops->irqdisable(ec, ec->irq);
465
466 host = ata_host_alloc(&ec->dev, info->nr_ports);
467 if (!host)
468 return -ENOMEM;
469
470 host->private_data = info->state;
471 host->flags = ATA_HOST_SIMPLEX;
472
473 for (i = 0; i < info->nr_ports; i++) {
474 struct ata_port *ap = host->ports[i];
475
476 ap->pio_mask = 0x1f;
477 ap->mwdma_mask = info->mwdma_mask;
478 ap->flags |= ATA_FLAG_SLAVE_POSS;
479 ap->ops = &pata_icside_port_ops;
480
481 pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
482 }
483
484 return ata_host_activate(host, ec->irq, ata_sff_interrupt, 0,
485 &pata_icside_sht);
486 }
487
488 static int __devinit
489 pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id)
490 {
491 struct pata_icside_state *state;
492 struct pata_icside_info info;
493 void __iomem *idmem;
494 int ret;
495
496 ret = ecard_request_resources(ec);
497 if (ret)
498 goto out;
499
500 state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
501 if (!state) {
502 ret = -ENOMEM;
503 goto release;
504 }
505
506 state->type = ICS_TYPE_NOTYPE;
507 state->dma = NO_DMA;
508
509 idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
510 if (idmem) {
511 unsigned int type;
512
513 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
514 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
515 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
516 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
517 ecardm_iounmap(ec, idmem);
518
519 state->type = type;
520 }
521
522 memset(&info, 0, sizeof(info));
523 info.state = state;
524 info.ec = ec;
525
526 switch (state->type) {
527 case ICS_TYPE_A3IN:
528 dev_warn(&ec->dev, "A3IN unsupported\n");
529 ret = -ENODEV;
530 break;
531
532 case ICS_TYPE_A3USER:
533 dev_warn(&ec->dev, "A3USER unsupported\n");
534 ret = -ENODEV;
535 break;
536
537 case ICS_TYPE_V5:
538 ret = pata_icside_register_v5(&info);
539 break;
540
541 case ICS_TYPE_V6:
542 ret = pata_icside_register_v6(&info);
543 break;
544
545 default:
546 dev_warn(&ec->dev, "unknown interface type\n");
547 ret = -ENODEV;
548 break;
549 }
550
551 if (ret == 0)
552 ret = pata_icside_add_ports(&info);
553
554 if (ret == 0)
555 goto out;
556
557 release:
558 ecard_release_resources(ec);
559 out:
560 return ret;
561 }
562
563 static void pata_icside_shutdown(struct expansion_card *ec)
564 {
565 struct ata_host *host = ecard_get_drvdata(ec);
566 unsigned long flags;
567
568 /*
569 * Disable interrupts from this card. We need to do
570 * this before disabling EASI since we may be accessing
571 * this register via that region.
572 */
573 local_irq_save(flags);
574 ec->ops->irqdisable(ec, ec->irq);
575 local_irq_restore(flags);
576
577 /*
578 * Reset the ROM pointer so that we can read the ROM
579 * after a soft reboot. This also disables access to
580 * the IDE taskfile via the EASI region.
581 */
582 if (host) {
583 struct pata_icside_state *state = host->private_data;
584 if (state->ioc_base)
585 writeb(0, state->ioc_base);
586 }
587 }
588
589 static void __devexit pata_icside_remove(struct expansion_card *ec)
590 {
591 struct ata_host *host = ecard_get_drvdata(ec);
592 struct pata_icside_state *state = host->private_data;
593
594 ata_host_detach(host);
595
596 pata_icside_shutdown(ec);
597
598 /*
599 * don't NULL out the drvdata - devres/libata wants it
600 * to free the ata_host structure.
601 */
602 if (state->dma != NO_DMA)
603 free_dma(state->dma);
604
605 ecard_release_resources(ec);
606 }
607
608 static const struct ecard_id pata_icside_ids[] = {
609 { MANU_ICS, PROD_ICS_IDE },
610 { MANU_ICS2, PROD_ICS2_IDE },
611 { 0xffff, 0xffff }
612 };
613
614 static struct ecard_driver pata_icside_driver = {
615 .probe = pata_icside_probe,
616 .remove = __devexit_p(pata_icside_remove),
617 .shutdown = pata_icside_shutdown,
618 .id_table = pata_icside_ids,
619 .drv = {
620 .name = DRV_NAME,
621 },
622 };
623
624 static int __init pata_icside_init(void)
625 {
626 return ecard_register_driver(&pata_icside_driver);
627 }
628
629 static void __exit pata_icside_exit(void)
630 {
631 ecard_remove_driver(&pata_icside_driver);
632 }
633
634 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
635 MODULE_LICENSE("GPL");
636 MODULE_DESCRIPTION("ICS PATA driver");
637
638 module_init(pata_icside_init);
639 module_exit(pata_icside_exit);
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