arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/arch/common.h>
  20 #include <asm/arch/control.h>
  21 #include <asm/arch/cpu.h>
  22
  23 static u32 class;
  24 static void __iomem *tap_base;
  25 static u16 tap_prod_id;
  26
  27 #define OMAP_TAP_IDCODE         0x0204
  28 #define OMAP_TAP_DIE_ID_0       0x0218
  29 #define OMAP_TAP_DIE_ID_1       0x021C
  30 #define OMAP_TAP_DIE_ID_2       0x0220
  31 #define OMAP_TAP_DIE_ID_3       0x0224
  32
  33 /* system_rev fields for OMAP2 processors:
  34  *   CPU id bits     [31:16],
  35  *   CPU device type [15:12], (unprg,normal,POP)
  36  *   CPU revision    [11:08]
  37  *   CPU class bits  [07:00]
  38  */
  39
  40 struct omap_id {
  41         u16     hawkeye;        /* Silicon type (Hawkeye id) */
  42         u8      dev;            /* Device type from production_id reg */
  43         u32     type;           /* combined type id copied to system_rev */
  44 };
  45
  46 /* Register values to detect the OMAP version */
  47 static struct omap_id omap_ids[] __initdata = {
  48         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
  49         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
  50         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
  51         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
  52         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
  53         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
  54 };
  55
  56 static struct omap_chip_id omap_chip;
  57
  58 /**
  59  * omap_chip_is - test whether currently running OMAP matches a chip type
  60  * @oc: omap_chip_t to test against
  61  *
  62  * Test whether the currently-running OMAP chip matches the supplied
  63  * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
  64  */
  65 int omap_chip_is(struct omap_chip_id oci)
  66 {
  67         return (oci.oc & omap_chip.oc) ? 1 : 0;
  68 }
  69 EXPORT_SYMBOL(omap_chip_is);
  70
  71 static u32 __init read_tap_reg(int reg)
  72 {
  73         unsigned int regval = 0;
  74         u32 cpuid;
  75
  76         /* Reading the IDCODE register on 3430 ES1 results in a
  77          * data abort as the register is not exposed on the OCP
  78          * Hence reading the Cortex Rev
  79          */
  80         cpuid = read_cpuid(CPUID_ID);
  81
  82         /* If the processor type is Cortex-A8 and the revision is 0x0
  83          * it means its Cortex r0p0 which is 3430 ES1
  84          */
  85         if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
  86
  87                 if (reg == tap_prod_id) {
  88                         regval = 0x000F00F0;
  89                         goto out;
  90                 }
  91
  92                 switch (reg) {
  93                 case OMAP_TAP_IDCODE  : regval = 0x0B7AE02F; break;
  94                 /* Making DevType as 0xF in ES1 to differ from ES2 */
  95                 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
  96                 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
  97                 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
  98                 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
  99                 }
 100         } else
 101                 regval = __raw_readl(tap_base + reg);
 102
 103 out:
 104         return regval;
 105
 106 }
 107
 108 /*
 109  * _set_system_rev - set the system_rev global based on current OMAP chip type
 110  *
 111  * Set the system_rev global.  This is primarily used by the cpu_is_omapxxxx()
 112  * macros.
 113  */
 114 static void __init _set_system_rev(u32 type, u8 rev)
 115 {
 116         u32 i, ctrl_status;
 117
 118         /*
 119          * system_rev encoding is as follows
 120          * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
 121          * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
 122          * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
 123          * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
 124          * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
 125          * system_rev & 0x000000c0 -> IDCODE revision[6:7]
 126          * system_rev & 0x0000003f -> sys_boot[0:5]
 127          */
 128         /* Embedding the ES revision info in type field */
 129         system_rev = type;
 130         /* Also add IDCODE revision info only two lower bits */
 131         system_rev |= ((rev & 0x3) << 6);
 132
 133         /* Add in the device type and sys_boot fields (see above) */
 134         if (cpu_is_omap24xx()) {
 135                 i = OMAP24XX_CONTROL_STATUS;
 136         } else if (cpu_is_omap343x()) {
 137                 i = OMAP343X_CONTROL_STATUS;
 138         } else {
 139                 printk(KERN_ERR "id: unknown CPU type\n");
 140                 BUG();
 141         }
 142         ctrl_status = omap_ctrl_readl(i);
 143         system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
 144                                       OMAP2_SYSBOOT_4_MASK |
 145                                       OMAP2_SYSBOOT_3_MASK |
 146                                       OMAP2_SYSBOOT_2_MASK |
 147                                       OMAP2_SYSBOOT_1_MASK |
 148                                       OMAP2_SYSBOOT_0_MASK));
 149         system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
 150 }
 151
 152
 153 /*
 154  * _set_omap_chip - set the omap_chip global based on OMAP chip type
 155  *
 156  * Build the omap_chip bits.  This variable is used by powerdomain and
 157  * clockdomain code to indicate whether structures are applicable for
 158  * the current OMAP chip type by ANDing it against a 'platform' bitfield
 159  * in the structure.
 160  */
 161 static void __init _set_omap_chip(void)
 162 {
 163         if (cpu_is_omap343x()) {
 164
 165                 omap_chip.oc = CHIP_IS_OMAP3430;
 166                 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
 167                         omap_chip.oc |= CHIP_IS_OMAP3430ES1;
 168                 else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
 169                         omap_chip.oc |= CHIP_IS_OMAP3430ES2;
 170
 171         } else if (cpu_is_omap243x()) {
 172
 173                 /* Currently only supports 2430ES2.1 and 2430-all */
 174                 omap_chip.oc |= CHIP_IS_OMAP2430;
 175
 176         } else if (cpu_is_omap242x()) {
 177
 178                 /* Currently only supports 2420ES2.1.1 and 2420-all */
 179                 omap_chip.oc |= CHIP_IS_OMAP2420;
 180
 181         } else {
 182
 183                 /* Current CPU not supported by this code. */
 184                 printk(KERN_WARNING "OMAP chip type code does not yet support "
 185                        "this CPU type.\n");
 186                 WARN_ON(1);
 187
 188         }
 189
 190 }
 191
 192 void __init omap2_check_revision(void)
 193 {
 194         int i, j;
 195         u32 idcode;
 196         u32 prod_id;
 197         u16 hawkeye;
 198         u8  dev_type;
 199         u8  rev;
 200
 201         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 202         prod_id = read_tap_reg(tap_prod_id);
 203         hawkeye = (idcode >> 12) & 0xffff;
 204         rev = (idcode >> 28) & 0x0f;
 205         dev_type = (prod_id >> 16) & 0x0f;
 206
 207         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 208                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 209         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
 210                  read_tap_reg(OMAP_TAP_DIE_ID_0));
 211         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 212                  read_tap_reg(OMAP_TAP_DIE_ID_1),
 213                  (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
 214         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
 215                  read_tap_reg(OMAP_TAP_DIE_ID_2));
 216         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
 217                  read_tap_reg(OMAP_TAP_DIE_ID_3));
 218         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 219                  prod_id, dev_type);
 220
 221         /*
 222          * Detection for 34xx ES2.0 and above can be done with just
 223          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 224          * Note that rev cannot be used directly as ES1.0 uses value 0.
 225          */
 226         if (hawkeye == 0xb7ae) {
 227                 system_rev = 0x34300000 | ((1 + rev) << 12);
 228                 pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
 229                 _set_omap_chip();
 230                 return;
 231         }
 232
 233         /* Check hawkeye ids */
 234         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 235                 if (hawkeye == omap_ids[i].hawkeye)
 236                         break;
 237         }
 238
 239         if (i == ARRAY_SIZE(omap_ids)) {
 240                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 241                 return;
 242         }
 243
 244         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 245                 if (dev_type == omap_ids[j].dev)
 246                         break;
 247         }
 248
 249         if (j == ARRAY_SIZE(omap_ids)) {
 250                 printk(KERN_ERR "Unknown OMAP device type. "
 251                                 "Handling it as OMAP%04x\n",
 252                                 omap_ids[i].type >> 16);
 253                 j = i;
 254         }
 255
 256         _set_system_rev(omap_ids[j].type, rev);
 257
 258         _set_omap_chip();
 259
 260         pr_info("OMAP%04x", system_rev >> 16);
 261         if ((system_rev >> 8) & 0x0f)
 262                 pr_info("ES%x", (system_rev >> 12) & 0xf);
 263         pr_info("\n");
 264
 265 }
 266
 267 #ifdef CONFIG_ARCH_OMAP3
 268 /*
 269  * OMAP3 has L2 cache which has to be enabled by bootloader.
 270  */
 271 static int __init omap3_check_l2cache(void)
 272 {
 273         u32 val;
 274
 275         if (class < OMAP3430_REV_ES1_0)
 276                 return -ENODEV;
 277
 278         /* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
 279         asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
 280
 281         if ((val & 0x2) == 0)
 282                 printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
 283                        "your bootloader. L2 off results in performance loss\n");
 284         else
 285                 pr_info("OMAP3 L2 cache enabled\n");
 286
 287         return 0;
 288 }
 289
 290 arch_initcall(omap3_check_l2cache);
 291 #endif /* CONFIG_ARCH_OMAP3 */
 292
 293 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
 294 {
 295         class = omap2_globals->class;
 296         tap_base = omap2_globals->tap;
 297
 298         if (class == 0x3430)
 299                 tap_prod_id = 0x0210;
 300         else
 301                 tap_prod_id = 0x0208;
 302 }