arch/arm/mach-omap2/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap2/irq.c
   3  *
   4  * Interrupt handler for OMAP2 boards.
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License. See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <asm/hardware.h>
  17 #include <asm/mach/irq.h>
  18 #include <linux/irq.h>
  19 #include <linux/io.h>
  20
  21 /* selected INTC register offsets */
  22
  23 #define INTC_REVISION           0x0000
  24 #define INTC_SYSCONFIG          0x0010
  25 #define INTC_SYSSTATUS          0x0014
  26 #define INTC_CONTROL            0x0048
  27 #define INTC_MIR_CLEAR0         0x0088
  28 #define INTC_MIR_SET0           0x008c
  29 #define INTC_PENDING_IRQ0       0x0098
  30
  31 /* Number of IRQ state bits in each MIR register */
  32 #define IRQ_BITS_PER_REG        32
  33
  34 /*
  35  * OMAP2 has a number of different interrupt controllers, each interrupt
  36  * controller is identified as its own "bank". Register definitions are
  37  * fairly consistent for each bank, but not all registers are implemented
  38  * for each bank.. when in doubt, consult the TRM.
  39  */
  40 static struct omap_irq_bank {
  41         unsigned long base_reg;
  42         unsigned int nr_irqs;
  43 } __attribute__ ((aligned(4))) irq_banks[] = {
  44         {
  45                 /* MPU INTC */
  46                 .base_reg       = 0,
  47                 .nr_irqs        = 96,
  48         },
  49 };
  50
  51 /* INTC bank register get/set */
  52
  53 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
  54 {
  55         __raw_writel(val, bank->base_reg + reg);
  56 }
  57
  58 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
  59 {
  60         return __raw_readl(bank->base_reg + reg);
  61 }
  62
  63 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
  64 static void omap_ack_irq(unsigned int irq)
  65 {
  66         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
  67 }
  68
  69 static void omap_mask_irq(unsigned int irq)
  70 {
  71         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
  72
  73         irq &= (IRQ_BITS_PER_REG - 1);
  74
  75         intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
  76 }
  77
  78 static void omap_unmask_irq(unsigned int irq)
  79 {
  80         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
  81
  82         irq &= (IRQ_BITS_PER_REG - 1);
  83
  84         intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
  85 }
  86
  87 static void omap_mask_ack_irq(unsigned int irq)
  88 {
  89         omap_mask_irq(irq);
  90         omap_ack_irq(irq);
  91 }
  92
  93 static struct irq_chip omap_irq_chip = {
  94         .name   = "INTC",
  95         .ack    = omap_mask_ack_irq,
  96         .mask   = omap_mask_irq,
  97         .unmask = omap_unmask_irq,
  98 };
  99
 100 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 101 {
 102         unsigned long tmp;
 103
 104         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
 105         printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
 106                          "(revision %ld.%ld) with %d interrupts\n",
 107                          bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 108
 109         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
 110         tmp |= 1 << 1;  /* soft reset */
 111         intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
 112
 113         while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
 114                 /* Wait for reset to complete */;
 115
 116         /* Enable autoidle */
 117         intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
 118 }
 119
 120 int omap_irq_pending(void)
 121 {
 122         int i;
 123
 124         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 125                 struct omap_irq_bank *bank = irq_banks + i;
 126                 int irq;
 127
 128                 for (irq = 0; irq < bank->nr_irqs; irq += IRQ_BITS_PER_REG) {
 129                         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 130
 131                         if (intc_bank_read_reg(bank, (INTC_PENDING_IRQ0 +
 132                                                       offset)))
 133                                 return 1;
 134                 }
 135         }
 136
 137         return 0;
 138 }
 139
 140 void __init omap_init_irq(void)
 141 {
 142         unsigned long nr_irqs = 0;
 143         unsigned int nr_banks = 0;
 144         int i;
 145
 146         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 147                 struct omap_irq_bank *bank = irq_banks + i;
 148
 149                 if (cpu_is_omap24xx())
 150                         bank->base_reg = io_p2v(OMAP24XX_IC_BASE);
 151                 else if (cpu_is_omap34xx())
 152                         bank->base_reg = io_p2v(OMAP34XX_IC_BASE);
 153
 154                 omap_irq_bank_init_one(bank);
 155
 156                 nr_irqs += bank->nr_irqs;
 157                 nr_banks++;
 158         }
 159
 160         printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
 161                nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 162
 163         for (i = 0; i < nr_irqs; i++) {
 164                 set_irq_chip(i, &omap_irq_chip);
 165                 set_irq_handler(i, handle_level_irq);
 166                 set_irq_flags(i, IRQF_VALID);
 167         }
 168 }
 169