arch/arm/mach-omap2/memory.c

   1 /*
   2  * linux/arch/arm/mach-omap2/memory.c
   3  *
   4  * Memory timing related functions for OMAP24XX
   5  *
   6  * Copyright (C) 2005 Texas Instruments Inc.
   7  * Richard Woodruff <r-woodruff2@ti.com>
   8  *
   9  * Copyright (C) 2005 Nokia Corporation
  10  * Tony Lindgren <tony@atomide.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/device.h>
  20 #include <linux/list.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/io.h>
  26
  27 #include <asm/arch/common.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sram.h>
  30
  31 #include "prm.h"
  32
  33 #include "memory.h"
  34 #include "sdrc.h"
  35
  36 void __iomem *omap2_sdrc_base;
  37 void __iomem *omap2_sms_base;
  38
  39 static struct memory_timings mem_timings;
  40 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
  41
  42 u32 omap2_memory_get_slow_dll_ctrl(void)
  43 {
  44         return mem_timings.slow_dll_ctrl;
  45 }
  46
  47 u32 omap2_memory_get_fast_dll_ctrl(void)
  48 {
  49         return mem_timings.fast_dll_ctrl;
  50 }
  51
  52 u32 omap2_memory_get_type(void)
  53 {
  54         return mem_timings.m_type;
  55 }
  56
  57 /*
  58  * Check the DLL lock state, and return tue if running in unlock mode.
  59  * This is needed to compensate for the shifted DLL value in unlock mode.
  60  */
  61 u32 omap2_dll_force_needed(void)
  62 {
  63         /* dlla and dllb are a set */
  64         u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
  65
  66         if ((dll_state & (1 << 2)) == (1 << 2))
  67                 return 1;
  68         else
  69                 return 0;
  70 }
  71
  72 /*
  73  * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
  74  * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
  75  * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
  76  */
  77 u32 omap2_reprogram_sdrc(u32 level, u32 force)
  78 {
  79         u32 dll_ctrl, m_type;
  80         u32 prev = curr_perf_level;
  81         unsigned long flags;
  82
  83         if ((curr_perf_level == level) && !force)
  84                 return prev;
  85
  86         if (level == CORE_CLK_SRC_DPLL) {
  87                 dll_ctrl = omap2_memory_get_slow_dll_ctrl();
  88         } else if (level == CORE_CLK_SRC_DPLL_X2) {
  89                 dll_ctrl = omap2_memory_get_fast_dll_ctrl();
  90         } else {
  91                 return prev;
  92         }
  93
  94         m_type = omap2_memory_get_type();
  95
  96         local_irq_save(flags);
  97         prm_write_mod_reg(0xffff, OMAP24XX_GR_MOD,
  98                                         OMAP24XX_PRCM_VOLTSETUP_OFFSET);
  99         omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
 100         curr_perf_level = level;
 101         local_irq_restore(flags);
 102
 103         return prev;
 104 }
 105
 106 void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
 107 {
 108         unsigned long dll_cnt;
 109         u32 fast_dll = 0;
 110
 111         mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
 112
 113         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
 114          * In the case of 2422, its ok to use CS1 instead of CS0.
 115          */
 116         if (cpu_is_omap2422())
 117                 mem_timings.base_cs = 1;
 118         else
 119                 mem_timings.base_cs = 0;
 120
 121         if (mem_timings.m_type != M_DDR)
 122                 return;
 123
 124         /* With DDR we need to determine the low frequency DLL value */
 125         if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
 126                 mem_timings.dll_mode = M_UNLOCK;
 127         else
 128                 mem_timings.dll_mode = M_LOCK;
 129
 130         if (mem_timings.base_cs == 0) {
 131                 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
 132                 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
 133         } else {
 134                 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
 135                 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
 136         }
 137         if (force_lock_to_unlock_mode) {
 138                 fast_dll &= ~0xff00;
 139                 fast_dll |= dll_cnt;            /* Current lock mode */
 140         }
 141         /* set fast timings with DLL filter disabled */
 142         mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
 143
 144         /* No disruptions, DDR will be offline & C-ABI not followed */
 145         omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
 146                             mem_timings.fast_dll_ctrl,
 147                             mem_timings.base_cs,
 148                             force_lock_to_unlock_mode);
 149         mem_timings.slow_dll_ctrl &= 0xff00;    /* Keep lock value */
 150
 151         /* Turn status into unlock ctrl */
 152         mem_timings.slow_dll_ctrl |=
 153                 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
 154
 155         /* 90 degree phase for anything below 133Mhz + disable DLL filter */
 156         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 157 }
 158
 159 void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
 160 {
 161         omap2_sdrc_base = omap2_globals->sdrc;
 162         omap2_sms_base = omap2_globals->sms;
 163 }
 164
 165 /* turn on smart idle modes for SDRAM scheduler and controller */
 166 void __init omap2_init_memory(void)
 167 {
 168         u32 l;
 169
 170         l = sms_read_reg(SMS_SYSCONFIG);
 171         l &= ~(0x3 << 3);
 172         l |= (0x2 << 3);
 173         sms_write_reg(l, SMS_SYSCONFIG);
 174
 175         l = sdrc_read_reg(SDRC_SYSCONFIG);
 176         l &= ~(0x3 << 3);
 177         l |= (0x2 << 3);
 178         sdrc_write_reg(l, SDRC_SYSCONFIG);
 179 }