arch/arm/mach-omap2/sram34xx.S

   1 /*
   2  * linux/arch/arm/mach-omap3/sram.S
   3  *
   4  * Omap3 specific functions that need to be run in internal SRAM
   5  *
   6  * (C) Copyright 2007
   7  * Texas Instruments Inc.
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * (C) Copyright 2004
  11  * Texas Instruments, <www.ti.com>
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29 #include <linux/linkage.h>
  30 #include <asm/assembler.h>
  31 #include <asm/hardware.h>
  32
  33 #include <asm/arch/io.h>
  34
  35 #include "sdrc.h"
  36 #include "cm.h"
  37
  38         .text
  39
  40 ENTRY(omap34xx_sram_ddr_init)
  41         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
  42         ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
  43 ENTRY(omap34xx_sram_ddr_init_sz)
  44         .word   . - omap34xx_sram_ddr_init
  45
  46 ENTRY(omap34xx_sram_reprogram_sdrc)
  47         stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
  48         ldmfd   sp!, {r0 - r10, pc}     @ restore regs and return
  49 ENTRY(omap34xx_sram_reprogram_sdrc_sz)
  50         .word   . - omap34xx_sram_reprogram_sdrc
  51
  52 /*
  53  * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
  54  */
  55 ENTRY(omap34xx_sram_set_prcm)
  56         stmfd   sp!, {r0-r12, lr}       @ regs to stack
  57 ENTRY(omap34xx_sram_set_prcm_sz)
  58         .word   . - omap34xx_sram_set_prcm
  59
  60 /*
  61  * Change frequency of core dpll
  62  * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
  63  */
  64 ENTRY(omap34xx_sram_configure_core_dpll)
  65         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
  66         cmp     r3, #0x2
  67         blne    configure_sdrc
  68         cmp     r3, #0x2
  69         blne    lock_dll
  70         cmp     r3, #0x1
  71         blne    unlock_dll
  72         bl      sdram_in_selfrefresh    @ put the SDRAM in self refresh
  73         bl      configure_core_dpll
  74         bl      enable_sdrc
  75         cmp     r3, #0x1
  76         blne    wait_dll_unlock
  77         cmp     r3, #0x2
  78         blne    wait_dll_lock
  79         cmp     r3, #0x1
  80         blne    configure_sdrc
  81         mov     r0, #0                  @ return value
  82         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
  83 unlock_dll:
  84         ldr     r4, omap34xx_sdrc_dlla_ctrl
  85         ldr     r5, [r4]
  86         orr     r5, r5, #0x4
  87         str     r5, [r4]
  88         bx      lr
  89 lock_dll:
  90         ldr     r4, omap34xx_sdrc_dlla_ctrl
  91         ldr     r5, [r4]
  92         bic     r5, r5, #0x4
  93         str     r5, [r4]
  94         bx      lr
  95 sdram_in_selfrefresh:
  96         mov     r5, #0x0                @ Move 0 to R5
  97         mcr     p15, 0, r5, c7, c10, 5  @ memory barrier
  98         ldr     r4, omap34xx_sdrc_power @ read the SDRC_POWER register
  99         ldr     r5, [r4]                @ read the contents of SDRC_POWER
 100         orr     r5, r5, #0x40           @ enable self refresh on idle req
 101         str     r5, [r4]                @ write back to SDRC_POWER register
 102         ldr     r4, omap34xx_cm_iclken1_core    @ read the CM_ICLKEN1_CORE reg
 103         ldr     r5, [r4]
 104         bic     r5, r5, #0x2            @ disable iclk bit for SRDC
 105         str     r5, [r4]
 106 wait_sdrc_idle:
 107         ldr     r4, omap34xx_cm_idlest1_core
 108         ldr     r5, [r4]
 109         and     r5, r5, #0x2            @ check for SDRC idle
 110         cmp     r5, #2
 111         bne     wait_sdrc_idle
 112         bx      lr
 113 configure_core_dpll:
 114         ldr     r4, omap34xx_cm_clksel1_pll
 115         ldr     r5, [r4]
 116         ldr     r6, core_m2_mask_val    @ modify m2 for core dpll
 117         and     r5, r5, r6
 118         orr     r5, r5, r3, lsl #0x1B   @ r3 contains the M2 val
 119         str     r5, [r4]
 120         mov     r5, #0x800              @ wait for the clock to stabilise
 121         cmp     r3, #2
 122         bne     wait_clk_stable
 123         bx      lr
 124 wait_clk_stable:
 125         subs    r5, r5, #1
 126         bne     wait_clk_stable
 127         nop
 128         nop
 129         nop
 130         nop
 131         nop
 132         nop
 133         nop
 134         nop
 135         nop
 136         nop
 137         bx      lr
 138 enable_sdrc:
 139         ldr     r4, omap34xx_cm_iclken1_core
 140         ldr     r5, [r4]
 141         orr     r5, r5, #0x2            @ enable iclk bit for SDRC
 142         str     r5, [r4]
 143 wait_sdrc_idle1:
 144         ldr     r4, omap34xx_cm_idlest1_core
 145         ldr     r5, [r4]
 146         and     r5, r5, #0x2
 147         cmp     r5, #0
 148         bne     wait_sdrc_idle1
 149         ldr     r4, omap34xx_sdrc_power
 150         ldr     r5, [r4]
 151         bic     r5, r5, #0x40
 152         str     r5, [r4]
 153         bx      lr
 154 wait_dll_lock:
 155         ldr     r4, omap34xx_sdrc_dlla_status
 156         ldr     r5, [r4]
 157         and     r5, r5, #0x4
 158         cmp     r5, #0x4
 159         bne     wait_dll_lock
 160         bx      lr
 161 wait_dll_unlock:
 162         ldr     r4, omap34xx_sdrc_dlla_status
 163         ldr     r5, [r4]
 164         and     r5, r5, #0x4
 165         cmp     r5, #0x0
 166         bne     wait_dll_unlock
 167         bx      lr
 168 configure_sdrc:
 169         ldr     r4, omap34xx_sdrc_rfr_ctrl
 170         str     r0, [r4]
 171         ldr     r4, omap34xx_sdrc_actim_ctrla
 172         str     r1, [r4]
 173         ldr     r4, omap34xx_sdrc_actim_ctrlb
 174         str     r2, [r4]
 175         bx      lr
 176
 177 omap34xx_sdrc_power:
 178         .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 179 omap34xx_cm_clksel1_pll:
 180         .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
 181 omap34xx_cm_idlest1_core:
 182         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 183 omap34xx_cm_iclken1_core:
 184         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
 185 omap34xx_sdrc_rfr_ctrl:
 186         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 187 omap34xx_sdrc_actim_ctrla:
 188         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A)
 189 omap34xx_sdrc_actim_ctrlb:
 190         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B)
 191 omap34xx_sdrc_dlla_status:
 192         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 193 omap34xx_sdrc_dlla_ctrl:
 194         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 195 core_m2_mask_val:
 196         .word 0xE7FFFFFF
 197
 198 ENTRY(omap34xx_sram_configure_core_dpll_sz)
 199         .word   . - omap34xx_sram_configure_core_dpll
 200
 201 /*
 202  * Reprogram GPMC
 203  */
 204 ENTRY(omap34xx_sram_reprogram_gpmc)
 205         stmfd   sp!, {r0-r12, lr}       @ regs to stack
 206         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 207
 208 ENTRY(omap34xx_sram_reprogram_gpmc_sz)
 209         .word   . - omap34xx_sram_reprogram_gpmc