4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
37 #include <asm/hardware.h>
40 #include <asm/arch/i2c.h>
41 #include <asm/arch/pxa-regs.h>
42 #include <asm/arch/pxa2xx-gpio.h>
46 wait_queue_head_t wait
;
51 unsigned int slave_addr
;
53 struct i2c_adapter adap
;
55 #ifdef CONFIG_I2C_PXA_SLAVE
56 struct i2c_slave_client
*slave
;
59 unsigned int irqlogidx
;
63 void __iomem
*reg_base
;
72 #define _IBMR(i2c) ((i2c)->reg_base + 0)
73 #define _IDBR(i2c) ((i2c)->reg_base + 8)
74 #define _ICR(i2c) ((i2c)->reg_base + 0x10)
75 #define _ISR(i2c) ((i2c)->reg_base + 0x18)
76 #define _ISAR(i2c) ((i2c)->reg_base + 0x20)
79 * I2C Slave mode address
81 #define I2C_PXA_SLAVE_ADDR 0x1
90 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
93 decode_bits(const char *prefix
, const struct bits
*bits
, int num
, u32 val
)
95 printk("%s %08x: ", prefix
, val
);
97 const char *str
= val
& bits
->mask
? bits
->set
: bits
->unset
;
104 static const struct bits isr_bits
[] = {
105 PXA_BIT(ISR_RWM
, "RX", "TX"),
106 PXA_BIT(ISR_ACKNAK
, "NAK", "ACK"),
107 PXA_BIT(ISR_UB
, "Bsy", "Rdy"),
108 PXA_BIT(ISR_IBB
, "BusBsy", "BusRdy"),
109 PXA_BIT(ISR_SSD
, "SlaveStop", NULL
),
110 PXA_BIT(ISR_ALD
, "ALD", NULL
),
111 PXA_BIT(ISR_ITE
, "TxEmpty", NULL
),
112 PXA_BIT(ISR_IRF
, "RxFull", NULL
),
113 PXA_BIT(ISR_GCAD
, "GenCall", NULL
),
114 PXA_BIT(ISR_SAD
, "SlaveAddr", NULL
),
115 PXA_BIT(ISR_BED
, "BusErr", NULL
),
118 static void decode_ISR(unsigned int val
)
120 decode_bits(KERN_DEBUG
"ISR", isr_bits
, ARRAY_SIZE(isr_bits
), val
);
124 static const struct bits icr_bits
[] = {
125 PXA_BIT(ICR_START
, "START", NULL
),
126 PXA_BIT(ICR_STOP
, "STOP", NULL
),
127 PXA_BIT(ICR_ACKNAK
, "ACKNAK", NULL
),
128 PXA_BIT(ICR_TB
, "TB", NULL
),
129 PXA_BIT(ICR_MA
, "MA", NULL
),
130 PXA_BIT(ICR_SCLE
, "SCLE", "scle"),
131 PXA_BIT(ICR_IUE
, "IUE", "iue"),
132 PXA_BIT(ICR_GCD
, "GCD", NULL
),
133 PXA_BIT(ICR_ITEIE
, "ITEIE", NULL
),
134 PXA_BIT(ICR_IRFIE
, "IRFIE", NULL
),
135 PXA_BIT(ICR_BEIE
, "BEIE", NULL
),
136 PXA_BIT(ICR_SSDIE
, "SSDIE", NULL
),
137 PXA_BIT(ICR_ALDIE
, "ALDIE", NULL
),
138 PXA_BIT(ICR_SADIE
, "SADIE", NULL
),
139 PXA_BIT(ICR_UR
, "UR", "ur"),
142 #ifdef CONFIG_I2C_PXA_SLAVE
143 static void decode_ICR(unsigned int val
)
145 decode_bits(KERN_DEBUG
"ICR", icr_bits
, ARRAY_SIZE(icr_bits
), val
);
150 static unsigned int i2c_debug
= DEBUG
;
152 static void i2c_pxa_show_state(struct pxa_i2c
*i2c
, int lno
, const char *fname
)
154 dev_dbg(&i2c
->adap
.dev
, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname
, lno
,
155 readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
158 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
162 #define show_state(i2c) do { } while (0)
163 #define decode_ISR(val) do { } while (0)
164 #define decode_ICR(val) do { } while (0)
167 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
169 static void i2c_pxa_master_complete(struct pxa_i2c
*i2c
, int ret
);
170 static irqreturn_t
i2c_pxa_handler(int this_irq
, void *dev_id
);
172 static void i2c_pxa_scream_blue_murder(struct pxa_i2c
*i2c
, const char *why
)
175 printk("i2c: error: %s\n", why
);
176 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
177 i2c
->msg_num
, i2c
->msg_idx
, i2c
->msg_ptr
);
178 printk("i2c: ICR: %08x ISR: %08x\n"
179 "i2c: log: ", readl(_ICR(i2c
)), readl(_ISR(i2c
)));
180 for (i
= 0; i
< i2c
->irqlogidx
; i
++)
181 printk("[%08x:%08x] ", i2c
->isrlog
[i
], i2c
->icrlog
[i
]);
185 static inline int i2c_pxa_is_slavemode(struct pxa_i2c
*i2c
)
187 return !(readl(_ICR(i2c
)) & ICR_SCLE
);
190 static void i2c_pxa_abort(struct pxa_i2c
*i2c
)
192 unsigned long timeout
= jiffies
+ HZ
/4;
194 if (i2c_pxa_is_slavemode(i2c
)) {
195 dev_dbg(&i2c
->adap
.dev
, "%s: called in slave mode\n", __func__
);
199 while (time_before(jiffies
, timeout
) && (readl(_IBMR(i2c
)) & 0x1) == 0) {
200 unsigned long icr
= readl(_ICR(i2c
));
203 icr
|= ICR_ACKNAK
| ICR_STOP
| ICR_TB
;
205 writel(icr
, _ICR(i2c
));
212 writel(readl(_ICR(i2c
)) & ~(ICR_MA
| ICR_START
| ICR_STOP
),
216 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c
*i2c
)
218 int timeout
= DEF_TIMEOUT
;
220 while (timeout
-- && readl(_ISR(i2c
)) & (ISR_IBB
| ISR_UB
)) {
221 if ((readl(_ISR(i2c
)) & ISR_SAD
) != 0)
231 return timeout
<= 0 ? I2C_RETRY
: 0;
234 static int i2c_pxa_wait_master(struct pxa_i2c
*i2c
)
236 unsigned long timeout
= jiffies
+ HZ
*4;
238 while (time_before(jiffies
, timeout
)) {
240 dev_dbg(&i2c
->adap
.dev
, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
241 __func__
, (long)jiffies
, readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
243 if (readl(_ISR(i2c
)) & ISR_SAD
) {
245 dev_dbg(&i2c
->adap
.dev
, "%s: Slave detected\n", __func__
);
249 /* wait for unit and bus being not busy, and we also do a
250 * quick check of the i2c lines themselves to ensure they've
253 if ((readl(_ISR(i2c
)) & (ISR_UB
| ISR_IBB
)) == 0 && readl(_IBMR(i2c
)) == 3) {
255 dev_dbg(&i2c
->adap
.dev
, "%s: done\n", __func__
);
263 dev_dbg(&i2c
->adap
.dev
, "%s: did not free\n", __func__
);
268 static int i2c_pxa_set_master(struct pxa_i2c
*i2c
)
271 dev_dbg(&i2c
->adap
.dev
, "setting to bus master\n");
273 if ((readl(_ISR(i2c
)) & (ISR_UB
| ISR_IBB
)) != 0) {
274 dev_dbg(&i2c
->adap
.dev
, "%s: unit is busy\n", __func__
);
275 if (!i2c_pxa_wait_master(i2c
)) {
276 dev_dbg(&i2c
->adap
.dev
, "%s: error: unit busy\n", __func__
);
281 writel(readl(_ICR(i2c
)) | ICR_SCLE
, _ICR(i2c
));
285 #ifdef CONFIG_I2C_PXA_SLAVE
286 static int i2c_pxa_wait_slave(struct pxa_i2c
*i2c
)
288 unsigned long timeout
= jiffies
+ HZ
*1;
294 while (time_before(jiffies
, timeout
)) {
296 dev_dbg(&i2c
->adap
.dev
, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
297 __func__
, (long)jiffies
, readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
299 if ((readl(_ISR(i2c
)) & (ISR_UB
|ISR_IBB
)) == 0 ||
300 (readl(_ISR(i2c
)) & ISR_SAD
) != 0 ||
301 (readl(_ICR(i2c
)) & ICR_SCLE
) == 0) {
303 dev_dbg(&i2c
->adap
.dev
, "%s: done\n", __func__
);
311 dev_dbg(&i2c
->adap
.dev
, "%s: did not free\n", __func__
);
316 * clear the hold on the bus, and take of anything else
317 * that has been configured
319 static void i2c_pxa_set_slave(struct pxa_i2c
*i2c
, int errcode
)
324 udelay(100); /* simple delay */
326 /* we need to wait for the stop condition to end */
328 /* if we where in stop, then clear... */
329 if (readl(_ICR(i2c
)) & ICR_STOP
) {
331 writel(readl(_ICR(i2c
)) & ~ICR_STOP
, _ICR(i2c
));
334 if (!i2c_pxa_wait_slave(i2c
)) {
335 dev_err(&i2c
->adap
.dev
, "%s: wait timedout\n",
341 writel(readl(_ICR(i2c
)) & ~(ICR_STOP
|ICR_ACKNAK
|ICR_MA
), _ICR(i2c
));
342 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
345 dev_dbg(&i2c
->adap
.dev
, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c
)), readl(_ISR(i2c
)));
346 decode_ICR(readl(_ICR(i2c
)));
350 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
353 static void i2c_pxa_reset(struct pxa_i2c
*i2c
)
355 pr_debug("Resetting I2C Controller Unit\n");
357 /* abort any transfer currently under way */
360 /* reset according to 9.8 */
361 writel(ICR_UR
, _ICR(i2c
));
362 writel(I2C_ISR_INIT
, _ISR(i2c
));
363 writel(readl(_ICR(i2c
)) & ~ICR_UR
, _ICR(i2c
));
365 writel(i2c
->slave_addr
, _ISAR(i2c
));
367 /* set control register values */
368 writel(I2C_ICR_INIT
, _ICR(i2c
));
370 #ifdef CONFIG_I2C_PXA_SLAVE
371 dev_info(&i2c
->adap
.dev
, "Enabling slave mode\n");
372 writel(readl(_ICR(i2c
)) | ICR_SADIE
| ICR_ALDIE
| ICR_SSDIE
, _ICR(i2c
));
375 i2c_pxa_set_slave(i2c
, 0);
378 writel(readl(_ICR(i2c
)) | ICR_IUE
, _ICR(i2c
));
383 #ifdef CONFIG_I2C_PXA_SLAVE
388 static void i2c_pxa_slave_txempty(struct pxa_i2c
*i2c
, u32 isr
)
391 /* what should we do here? */
395 if (i2c
->slave
!= NULL
)
396 ret
= i2c
->slave
->read(i2c
->slave
->data
);
398 writel(ret
, _IDBR(i2c
));
399 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
)); /* allow next byte */
403 static void i2c_pxa_slave_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
405 unsigned int byte
= readl(_IDBR(i2c
));
407 if (i2c
->slave
!= NULL
)
408 i2c
->slave
->write(i2c
->slave
->data
, byte
);
410 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
413 static void i2c_pxa_slave_start(struct pxa_i2c
*i2c
, u32 isr
)
418 dev_dbg(&i2c
->adap
.dev
, "SAD, mode is slave-%cx\n",
419 (isr
& ISR_RWM
) ? 'r' : 't');
421 if (i2c
->slave
!= NULL
)
422 i2c
->slave
->event(i2c
->slave
->data
,
423 (isr
& ISR_RWM
) ? I2C_SLAVE_EVENT_START_READ
: I2C_SLAVE_EVENT_START_WRITE
);
426 * slave could interrupt in the middle of us generating a
427 * start condition... if this happens, we'd better back off
428 * and stop holding the poor thing up
430 writel(readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
), _ICR(i2c
));
431 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
436 if ((readl(_IBMR(i2c
)) & 2) == 2)
442 dev_err(&i2c
->adap
.dev
, "timeout waiting for SCL high\n");
447 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
450 static void i2c_pxa_slave_stop(struct pxa_i2c
*i2c
)
453 dev_dbg(&i2c
->adap
.dev
, "ISR: SSD (Slave Stop)\n");
455 if (i2c
->slave
!= NULL
)
456 i2c
->slave
->event(i2c
->slave
->data
, I2C_SLAVE_EVENT_STOP
);
459 dev_dbg(&i2c
->adap
.dev
, "ISR: SSD (Slave Stop) acked\n");
462 * If we have a master-mode message waiting,
463 * kick it off now that the slave has completed.
466 i2c_pxa_master_complete(i2c
, I2C_RETRY
);
469 static void i2c_pxa_slave_txempty(struct pxa_i2c
*i2c
, u32 isr
)
472 /* what should we do here? */
474 writel(0, _IDBR(i2c
));
475 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
479 static void i2c_pxa_slave_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
481 writel(readl(_ICR(i2c
)) | ICR_TB
| ICR_ACKNAK
, _ICR(i2c
));
484 static void i2c_pxa_slave_start(struct pxa_i2c
*i2c
, u32 isr
)
489 * slave could interrupt in the middle of us generating a
490 * start condition... if this happens, we'd better back off
491 * and stop holding the poor thing up
493 writel(readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
), _ICR(i2c
));
494 writel(readl(_ICR(i2c
)) | ICR_TB
| ICR_ACKNAK
, _ICR(i2c
));
499 if ((readl(_IBMR(i2c
)) & 2) == 2)
505 dev_err(&i2c
->adap
.dev
, "timeout waiting for SCL high\n");
510 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
513 static void i2c_pxa_slave_stop(struct pxa_i2c
*i2c
)
516 i2c_pxa_master_complete(i2c
, I2C_RETRY
);
521 * PXA I2C Master mode
524 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg
*msg
)
526 unsigned int addr
= (msg
->addr
& 0x7f) << 1;
528 if (msg
->flags
& I2C_M_RD
)
534 static inline void i2c_pxa_start_message(struct pxa_i2c
*i2c
)
539 * Step 1: target slave address into IDBR
541 writel(i2c_pxa_addr_byte(i2c
->msg
), _IDBR(i2c
));
544 * Step 2: initiate the write.
546 icr
= readl(_ICR(i2c
)) & ~(ICR_STOP
| ICR_ALDIE
);
547 writel(icr
| ICR_START
| ICR_TB
, _ICR(i2c
));
550 static inline void i2c_pxa_stop_message(struct pxa_i2c
*i2c
)
555 * Clear the STOP and ACK flags
557 icr
= readl(_ICR(i2c
));
558 icr
&= ~(ICR_STOP
| ICR_ACKNAK
);
559 writel(icr
, _ICR(i2c
));
562 static int i2c_pxa_pio_set_master(struct pxa_i2c
*i2c
)
564 /* make timeout the same as for interrupt based functions */
565 long timeout
= 2 * DEF_TIMEOUT
;
568 * Wait for the bus to become free.
570 while (timeout
-- && readl(_ISR(i2c
)) & (ISR_IBB
| ISR_UB
)) {
577 dev_err(&i2c
->adap
.dev
,
578 "i2c_pxa: timeout waiting for bus free\n");
585 writel(readl(_ICR(i2c
)) | ICR_SCLE
, _ICR(i2c
));
590 static int i2c_pxa_do_pio_xfer(struct pxa_i2c
*i2c
,
591 struct i2c_msg
*msg
, int num
)
593 unsigned long timeout
= 500000; /* 5 seconds */
596 ret
= i2c_pxa_pio_set_master(i2c
);
606 i2c_pxa_start_message(i2c
);
608 while (timeout
-- && i2c
->msg_num
> 0) {
609 i2c_pxa_handler(0, i2c
);
613 i2c_pxa_stop_message(i2c
);
616 * We place the return code in i2c->msg_idx.
622 i2c_pxa_scream_blue_murder(i2c
, "timeout");
628 * We are protected by the adapter bus mutex.
630 static int i2c_pxa_do_xfer(struct pxa_i2c
*i2c
, struct i2c_msg
*msg
, int num
)
636 * Wait for the bus to become free.
638 ret
= i2c_pxa_wait_bus_not_busy(i2c
);
640 dev_err(&i2c
->adap
.dev
, "i2c_pxa: timeout waiting for bus free\n");
647 ret
= i2c_pxa_set_master(i2c
);
649 dev_err(&i2c
->adap
.dev
, "i2c_pxa_set_master: error %d\n", ret
);
653 spin_lock_irq(&i2c
->lock
);
661 i2c_pxa_start_message(i2c
);
663 spin_unlock_irq(&i2c
->lock
);
666 * The rest of the processing occurs in the interrupt handler.
668 timeout
= wait_event_timeout(i2c
->wait
, i2c
->msg_num
== 0, HZ
* 5);
669 i2c_pxa_stop_message(i2c
);
672 * We place the return code in i2c->msg_idx.
677 i2c_pxa_scream_blue_murder(i2c
, "timeout");
683 static int i2c_pxa_pio_xfer(struct i2c_adapter
*adap
,
684 struct i2c_msg msgs
[], int num
)
686 struct pxa_i2c
*i2c
= adap
->algo_data
;
689 /* If the I2C controller is disabled we need to reset it
690 (probably due to a suspend/resume destroying state). We do
691 this here as we can then avoid worrying about resuming the
692 controller before its users. */
693 if (!(readl(_ICR(i2c
)) & ICR_IUE
))
696 for (i
= adap
->retries
; i
>= 0; i
--) {
697 ret
= i2c_pxa_do_pio_xfer(i2c
, msgs
, num
);
698 if (ret
!= I2C_RETRY
)
702 dev_dbg(&adap
->dev
, "Retrying transmission\n");
705 i2c_pxa_scream_blue_murder(i2c
, "exhausted retries");
708 i2c_pxa_set_slave(i2c
, ret
);
713 * i2c_pxa_master_complete - complete the message and wake up.
715 static void i2c_pxa_master_complete(struct pxa_i2c
*i2c
, int ret
)
727 static void i2c_pxa_irq_txempty(struct pxa_i2c
*i2c
, u32 isr
)
729 u32 icr
= readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
|ICR_ACKNAK
|ICR_TB
);
733 * If ISR_ALD is set, we lost arbitration.
737 * Do we need to do anything here? The PXA docs
738 * are vague about what happens.
740 i2c_pxa_scream_blue_murder(i2c
, "ALD set");
743 * We ignore this error. We seem to see spurious ALDs
744 * for seemingly no reason. If we handle them as I think
745 * they should, we end up causing an I2C error, which
746 * is painful for some systems.
755 * I2C bus error - either the device NAK'd us, or
756 * something more serious happened. If we were NAK'd
757 * on the initial address phase, we can retry.
759 if (isr
& ISR_ACKNAK
) {
760 if (i2c
->msg_ptr
== 0 && i2c
->msg_idx
== 0)
765 i2c_pxa_master_complete(i2c
, ret
);
766 } else if (isr
& ISR_RWM
) {
768 * Read mode. We have just sent the address byte, and
769 * now we must initiate the transfer.
771 if (i2c
->msg_ptr
== i2c
->msg
->len
- 1 &&
772 i2c
->msg_idx
== i2c
->msg_num
- 1)
773 icr
|= ICR_STOP
| ICR_ACKNAK
;
775 icr
|= ICR_ALDIE
| ICR_TB
;
776 } else if (i2c
->msg_ptr
< i2c
->msg
->len
) {
778 * Write mode. Write the next data byte.
780 writel(i2c
->msg
->buf
[i2c
->msg_ptr
++], _IDBR(i2c
));
782 icr
|= ICR_ALDIE
| ICR_TB
;
785 * If this is the last byte of the last message, send
788 if (i2c
->msg_ptr
== i2c
->msg
->len
&&
789 i2c
->msg_idx
== i2c
->msg_num
- 1)
791 } else if (i2c
->msg_idx
< i2c
->msg_num
- 1) {
793 * Next segment of the message.
800 * If we aren't doing a repeated start and address,
801 * go back and try to send the next byte. Note that
802 * we do not support switching the R/W direction here.
804 if (i2c
->msg
->flags
& I2C_M_NOSTART
)
808 * Write the next address.
810 writel(i2c_pxa_addr_byte(i2c
->msg
), _IDBR(i2c
));
813 * And trigger a repeated start, and send the byte.
816 icr
|= ICR_START
| ICR_TB
;
818 if (i2c
->msg
->len
== 0) {
820 * Device probes have a message length of zero
821 * and need the bus to be reset before it can
826 i2c_pxa_master_complete(i2c
, 0);
829 i2c
->icrlog
[i2c
->irqlogidx
-1] = icr
;
831 writel(icr
, _ICR(i2c
));
835 static void i2c_pxa_irq_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
837 u32 icr
= readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
|ICR_ACKNAK
|ICR_TB
);
842 i2c
->msg
->buf
[i2c
->msg_ptr
++] = readl(_IDBR(i2c
));
844 if (i2c
->msg_ptr
< i2c
->msg
->len
) {
846 * If this is the last byte of the last
847 * message, send a STOP.
849 if (i2c
->msg_ptr
== i2c
->msg
->len
- 1)
850 icr
|= ICR_STOP
| ICR_ACKNAK
;
852 icr
|= ICR_ALDIE
| ICR_TB
;
854 i2c_pxa_master_complete(i2c
, 0);
857 i2c
->icrlog
[i2c
->irqlogidx
-1] = icr
;
859 writel(icr
, _ICR(i2c
));
862 static irqreturn_t
i2c_pxa_handler(int this_irq
, void *dev_id
)
864 struct pxa_i2c
*i2c
= dev_id
;
865 u32 isr
= readl(_ISR(i2c
));
867 if (i2c_debug
> 2 && 0) {
868 dev_dbg(&i2c
->adap
.dev
, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
869 __func__
, isr
, readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
873 if (i2c
->irqlogidx
< ARRAY_SIZE(i2c
->isrlog
))
874 i2c
->isrlog
[i2c
->irqlogidx
++] = isr
;
879 * Always clear all pending IRQs.
881 writel(isr
& (ISR_SSD
|ISR_ALD
|ISR_ITE
|ISR_IRF
|ISR_SAD
|ISR_BED
), _ISR(i2c
));
884 i2c_pxa_slave_start(i2c
, isr
);
886 i2c_pxa_slave_stop(i2c
);
888 if (i2c_pxa_is_slavemode(i2c
)) {
890 i2c_pxa_slave_txempty(i2c
, isr
);
892 i2c_pxa_slave_rxfull(i2c
, isr
);
893 } else if (i2c
->msg
) {
895 i2c_pxa_irq_txempty(i2c
, isr
);
897 i2c_pxa_irq_rxfull(i2c
, isr
);
899 i2c_pxa_scream_blue_murder(i2c
, "spurious irq");
906 static int i2c_pxa_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
908 struct pxa_i2c
*i2c
= adap
->algo_data
;
911 /* If the I2C controller is disabled we need to reset it (probably due
912 to a suspend/resume destroying state). We do this here as we can then
913 avoid worrying about resuming the controller before its users. */
914 if (!(readl(_ICR(i2c
)) & ICR_IUE
))
917 for (i
= adap
->retries
; i
>= 0; i
--) {
918 ret
= i2c_pxa_do_xfer(i2c
, msgs
, num
);
919 if (ret
!= I2C_RETRY
)
923 dev_dbg(&adap
->dev
, "Retrying transmission\n");
926 i2c_pxa_scream_blue_murder(i2c
, "exhausted retries");
929 i2c_pxa_set_slave(i2c
, ret
);
933 static u32
i2c_pxa_functionality(struct i2c_adapter
*adap
)
935 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
938 static const struct i2c_algorithm i2c_pxa_algorithm
= {
939 .master_xfer
= i2c_pxa_xfer
,
940 .functionality
= i2c_pxa_functionality
,
943 static const struct i2c_algorithm i2c_pxa_pio_algorithm
= {
944 .master_xfer
= i2c_pxa_pio_xfer
,
945 .functionality
= i2c_pxa_functionality
,
948 static void i2c_pxa_enable(struct platform_device
*dev
)
950 if (cpu_is_pxa27x()) {
953 pxa_gpio_mode(GPIO117_I2CSCL_MD
);
954 pxa_gpio_mode(GPIO118_I2CSDA_MD
);
965 static void i2c_pxa_disable(struct platform_device
*dev
)
967 if (cpu_is_pxa27x() && dev
->id
== 1) {
969 PCFR
&= ~PCFR_PI2CEN
;
974 #define res_len(r) ((r)->end - (r)->start + 1)
975 static int i2c_pxa_probe(struct platform_device
*dev
)
978 struct resource
*res
;
979 struct i2c_pxa_platform_data
*plat
= dev
->dev
.platform_data
;
983 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
984 irq
= platform_get_irq(dev
, 0);
985 if (res
== NULL
|| irq
< 0)
988 if (!request_mem_region(res
->start
, res_len(res
), res
->name
))
991 i2c
= kzalloc(sizeof(struct pxa_i2c
), GFP_KERNEL
);
997 i2c
->adap
.owner
= THIS_MODULE
;
998 i2c
->adap
.retries
= 5;
1000 spin_lock_init(&i2c
->lock
);
1001 init_waitqueue_head(&i2c
->wait
);
1004 * If "dev->id" is negative we consider it as zero.
1005 * The reason to do so is to avoid sysfs names that only make
1006 * sense when there are multiple adapters.
1008 i2c
->adap
.nr
= dev
->id
!= -1 ? dev
->id
: 0;
1009 snprintf(i2c
->adap
.name
, sizeof(i2c
->adap
.name
), "pxa_i2c-i2c.%u",
1012 i2c
->clk
= clk_get(&dev
->dev
, "I2CCLK");
1013 if (IS_ERR(i2c
->clk
)) {
1014 ret
= PTR_ERR(i2c
->clk
);
1018 i2c
->reg_base
= ioremap(res
->start
, res_len(res
));
1019 if (!i2c
->reg_base
) {
1024 i2c
->iobase
= res
->start
;
1025 i2c
->iosize
= res_len(res
);
1029 i2c
->slave_addr
= I2C_PXA_SLAVE_ADDR
;
1031 #ifdef CONFIG_I2C_PXA_SLAVE
1033 i2c
->slave_addr
= plat
->slave_addr
;
1034 i2c
->slave
= plat
->slave
;
1038 clk_enable(i2c
->clk
);
1039 i2c_pxa_enable(dev
);
1042 i2c
->adap
.class = plat
->class;
1043 i2c
->use_pio
= plat
->use_pio
;
1047 i2c
->adap
.algo
= &i2c_pxa_pio_algorithm
;
1049 i2c
->adap
.algo
= &i2c_pxa_algorithm
;
1050 ret
= request_irq(irq
, i2c_pxa_handler
, IRQF_DISABLED
,
1051 i2c
->adap
.name
, i2c
);
1058 i2c
->adap
.algo_data
= i2c
;
1059 i2c
->adap
.dev
.parent
= &dev
->dev
;
1061 ret
= i2c_add_numbered_adapter(&i2c
->adap
);
1063 printk(KERN_INFO
"I2C: Failed to add bus\n");
1067 platform_set_drvdata(dev
, i2c
);
1069 #ifdef CONFIG_I2C_PXA_SLAVE
1070 printk(KERN_INFO
"I2C: %s: PXA I2C adapter, slave address %d\n",
1071 i2c
->adap
.dev
.bus_id
, i2c
->slave_addr
);
1073 printk(KERN_INFO
"I2C: %s: PXA I2C adapter\n",
1074 i2c
->adap
.dev
.bus_id
);
1082 clk_disable(i2c
->clk
);
1083 i2c_pxa_disable(dev
);
1084 iounmap(i2c
->reg_base
);
1090 release_mem_region(res
->start
, res_len(res
));
1094 static int __exit
i2c_pxa_remove(struct platform_device
*dev
)
1096 struct pxa_i2c
*i2c
= platform_get_drvdata(dev
);
1098 platform_set_drvdata(dev
, NULL
);
1100 i2c_del_adapter(&i2c
->adap
);
1102 free_irq(i2c
->irq
, i2c
);
1104 clk_disable(i2c
->clk
);
1106 i2c_pxa_disable(dev
);
1108 iounmap(i2c
->reg_base
);
1109 release_mem_region(i2c
->iobase
, i2c
->iosize
);
1115 static struct platform_driver i2c_pxa_driver
= {
1116 .probe
= i2c_pxa_probe
,
1117 .remove
= __exit_p(i2c_pxa_remove
),
1119 .name
= "pxa2xx-i2c",
1120 .owner
= THIS_MODULE
,
1124 static int __init
i2c_adap_pxa_init(void)
1126 return platform_driver_register(&i2c_pxa_driver
);
1129 static void __exit
i2c_adap_pxa_exit(void)
1131 platform_driver_unregister(&i2c_pxa_driver
);
1134 MODULE_LICENSE("GPL");
1135 MODULE_ALIAS("platform:pxa2xx-i2c");
1137 module_init(i2c_adap_pxa_init
);
1138 module_exit(i2c_adap_pxa_exit
);