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ide: move ->failed_pc to ide_drive_t
[linux-ginger.git] / drivers / staging / sxg / sxghw.h
blobb0efff9ff1178ad58968c9e9b64fb101e8f2db54
1 /*
2 * Copyright © 1997-2007 Alacritech, Inc. All rights reserved
3 *
4 * $Id: sxghw.h,v 1.2 2008/07/24 17:24:23 chris Exp $
5 *
6 * sxghw.h:
7 *
8 * This file contains structures and definitions for the
9 * Alacritech Sahara hardware
10 */
11
12
13 /*******************************************************************************
14 * Configuration space
15 *******************************************************************************/
16 /* PCI Vendor ID */
17 #define SXG_VENDOR_ID 0x139A /* Alacritech's Vendor ID */
18
19 // PCI Device ID
20 #define SXG_DEVICE_ID 0x0009 /* Sahara Device ID */
21
22 //
23 // Subsystem IDs.
24 //
25 // The subsystem ID value is broken into bit fields as follows:
26 // Bits [15:12] - Function
27 // Bits [11:8] - OEM and/or operating system.
28 // Bits [7:0] - Base SID.
29 //
30 // SSID field (bit) masks
31 #define SSID_BASE_MASK 0x00FF // Base subsystem ID mask
32 #define SSID_OEM_MASK 0x0F00 // Subsystem OEM mask
33 #define SSID_FUNC_MASK 0xF000 // Subsystem function mask
34
35 // Base SSID's
36 #define SSID_SAHARA_PROTO 0x0018 // 100022 Sahara prototype (XenPak) board
37 #define SSID_SAHARA_FIBER 0x0019 // 100023 Sahara 1-port fiber board
38 #define SSID_SAHARA_COPPER 0x001A // 100024 Sahara 1-port copper board
39
40 // Useful SSID macros
41 #define SSID_BASE(ssid) ((ssid) & SSID_BASE_MASK) // isolate base SSID bits
42 #define SSID_OEM(ssid) ((ssid) & SSID_OEM_MASK) // isolate SSID OEM bits
43 #define SSID_FUNC(ssid) ((ssid) & SSID_FUNC_MASK) // isolate SSID function bits
44
45 /*******************************************************************************
46 * HW Register Space
47 *******************************************************************************/
48 #define SXG_HWREG_MEMSIZE 0x4000 // 16k
49
50 #pragma pack(push, 1)
51 struct SXG_HW_REGS {
52 u32 Reset; // Write 0xdead to invoke soft reset
53 u32 Pad1; // No register defined at offset 4
54 u32 InterruptMask0; // Deassert legacy interrupt on function 0
55 u32 InterruptMask1; // Deassert legacy interrupt on function 1
56 u32 UcodeDataLow; // Store microcode instruction bits 31-0
57 u32 UcodeDataMiddle; // Store microcode instruction bits 63-32
58 u32 UcodeDataHigh; // Store microcode instruction bits 95-64
59 u32 UcodeAddr; // Store microcode address - See flags below
60 u32 PadTo0x80[24]; // Pad to Xcv configuration registers
61 u32 MacConfig0; // 0x80 - AXGMAC Configuration Register 0
62 u32 MacConfig1; // 0x84 - AXGMAC Configuration Register 1
63 u32 MacConfig2; // 0x88 - AXGMAC Configuration Register 2
64 u32 MacConfig3; // 0x8C - AXGMAC Configuration Register 3
65 u32 MacAddressLow; // 0x90 - AXGMAC MAC Station Address - octets 1-4
66 u32 MacAddressHigh; // 0x94 - AXGMAC MAC Station Address - octets 5-6
67 u32 MacReserved1[2]; // 0x98 - AXGMAC Reserved
68 u32 MacMaxFrameLen; // 0xA0 - AXGMAC Maximum Frame Length
69 u32 MacReserved2[2]; // 0xA4 - AXGMAC Reserved
70 u32 MacRevision; // 0xAC - AXGMAC Revision Level Register
71 u32 MacReserved3[4]; // 0xB0 - AXGMAC Reserved
72 u32 MacAmiimCmd; // 0xC0 - AXGMAC AMIIM Command Register
73 u32 MacAmiimField; // 0xC4 - AXGMAC AMIIM Field Register
74 u32 MacAmiimConfig; // 0xC8 - AXGMAC AMIIM Configuration Register
75 u32 MacAmiimLink; // 0xCC - AXGMAC AMIIM Link Fail Vector Register
76 u32 MacAmiimIndicator; // 0xD0 - AXGMAC AMIIM Indicator Registor
77 u32 PadTo0x100[11]; // 0xD4 - 0x100 - Pad
78 u32 XmtConfig; // 0x100 - Transmit Configuration Register
79 u32 RcvConfig; // 0x104 - Receive Configuration Register 1
80 u32 LinkAddress0Low; // 0x108 - Link address 0
81 u32 LinkAddress0High; // 0x10C - Link address 0
82 u32 LinkAddress1Low; // 0x110 - Link address 1
83 u32 LinkAddress1High; // 0x114 - Link address 1
84 u32 LinkAddress2Low; // 0x118 - Link address 2
85 u32 LinkAddress2High; // 0x11C - Link address 2
86 u32 LinkAddress3Low; // 0x120 - Link address 3
87 u32 LinkAddress3High; // 0x124 - Link address 3
88 u32 ToeplitzKey[10]; // 0x128 - 0x150 - Toeplitz key
89 u32 SocketKey[10]; // 0x150 - 0x178 - Socket Key
90 u32 LinkStatus; // 0x178 - Link status
91 u32 ClearStats; // 0x17C - Clear Stats
92 u32 XmtErrorsLow; // 0x180 - Transmit stats - errors
93 u32 XmtErrorsHigh; // 0x184 - Transmit stats - errors
94 u32 XmtFramesLow; // 0x188 - Transmit stats - frame count
95 u32 XmtFramesHigh; // 0x18C - Transmit stats - frame count
96 u32 XmtBytesLow; // 0x190 - Transmit stats - byte count
97 u32 XmtBytesHigh; // 0x194 - Transmit stats - byte count
98 u32 XmtTcpSegmentsLow; // 0x198 - Transmit stats - TCP segments
99 u32 XmtTcpSegmentsHigh; // 0x19C - Transmit stats - TCP segments
100 u32 XmtTcpBytesLow; // 0x1A0 - Transmit stats - TCP bytes
101 u32 XmtTcpBytesHigh; // 0x1A4 - Transmit stats - TCP bytes
102 u32 RcvErrorsLow; // 0x1A8 - Receive stats - errors
103 u32 RcvErrorsHigh; // 0x1AC - Receive stats - errors
104 u32 RcvFramesLow; // 0x1B0 - Receive stats - frame count
105 u32 RcvFramesHigh; // 0x1B4 - Receive stats - frame count
106 u32 RcvBytesLow; // 0x1B8 - Receive stats - byte count
107 u32 RcvBytesHigh; // 0x1BC - Receive stats - byte count
108 u32 RcvTcpSegmentsLow; // 0x1C0 - Receive stats - TCP segments
109 u32 RcvTcpSegmentsHigh; // 0x1C4 - Receive stats - TCP segments
110 u32 RcvTcpBytesLow; // 0x1C8 - Receive stats - TCP bytes
111 u32 RcvTcpBytesHigh; // 0x1CC - Receive stats - TCP bytes
112 u32 PadTo0x200[12]; // 0x1D0 - 0x200 - Pad
113 u32 Software[1920]; // 0x200 - 0x2000 - Software defined (not used)
114 u32 MsixTable[1024]; // 0x2000 - 0x3000 - MSIX Table
115 u32 MsixBitArray[1024]; // 0x3000 - 0x4000 - MSIX Pending Bit Array
116 };
117 #pragma pack(pop)
118
119 // Microcode Address Flags
120 #define MICROCODE_ADDRESS_GO 0x80000000 // Start microcode
121 #define MICROCODE_ADDRESS_WRITE 0x40000000 // Store microcode
122 #define MICROCODE_ADDRESS_READ 0x20000000 // Read microcode
123 #define MICROCODE_ADDRESS_PARITY 0x10000000 // Parity error detected
124 #define MICROCODE_ADDRESS_MASK 0x00001FFF // Address bits
125
126 // Link Address Registers
127 #define LINK_ADDRESS_ENABLE 0x80000000 // Applied to link address high
128
129 // Microsoft register space size
130 #define SXG_UCODEREG_MEMSIZE 0x40000 // 256k
131
132 // Sahara microcode register address format. The command code,
133 // extended command code, and associated processor are encoded in
134 // the address bits as follows
135 #define SXG_ADDRESS_CODE_SHIFT 2 // Base command code
136 #define SXG_ADDRESS_CODE_MASK 0x0000003C
137 #define SXG_ADDRESS_EXCODE_SHIFT 6 // Extended (or sub) command code
138 #define SXG_ADDRESS_EXCODE_MASK 0x00001FC0
139 #define SXG_ADDRESS_CPUID_SHIFT 13 // CPU
140 #define SXG_ADDRESS_CPUID_MASK 0x0003E000
141 #define SXG_REGISTER_SIZE_PER_CPU 0x00002000 // Used to sanity check UCODE_REGS structure
142
143 // Sahara receive sequencer status values
144 #define SXG_RCV_STATUS_ATTN 0x80000000 // Attention
145 #define SXG_RCV_STATUS_TRANSPORT_MASK 0x3F000000 // Transport mask
146 #define SXG_RCV_STATUS_TRANSPORT_ERROR 0x20000000 // Transport error
147 #define SXG_RCV_STATUS_TRANSPORT_CSUM 0x23000000 // Transport cksum error
148 #define SXG_RCV_STATUS_TRANSPORT_UFLOW 0x22000000 // Transport underflow
149 #define SXG_RCV_STATUS_TRANSPORT_HDRLEN 0x20000000 // Transport header length
150 #define SXG_RCV_STATUS_TRANSPORT_FLAGS 0x10000000 // Transport flags detected
151 #define SXG_RCV_STATUS_TRANSPORT_OPTS 0x08000000 // Transport options detected
152 #define SXG_RCV_STATUS_TRANSPORT_SESS_MASK 0x07000000 // Transport DDP
153 #define SXG_RCV_STATUS_TRANSPORT_DDP 0x06000000 // Transport DDP
154 #define SXG_RCV_STATUS_TRANSPORT_iSCSI 0x05000000 // Transport iSCSI
155 #define SXG_RCV_STATUS_TRANSPORT_NFS 0x04000000 // Transport NFS
156 #define SXG_RCV_STATUS_TRANSPORT_FTP 0x03000000 // Transport FTP
157 #define SXG_RCV_STATUS_TRANSPORT_HTTP 0x02000000 // Transport HTTP
158 #define SXG_RCV_STATUS_TRANSPORT_SMB 0x01000000 // Transport SMB
159 #define SXG_RCV_STATUS_NETWORK_MASK 0x00FF0000 // Network mask
160 #define SXG_RCV_STATUS_NETWORK_ERROR 0x00800000 // Network error
161 #define SXG_RCV_STATUS_NETWORK_CSUM 0x00830000 // Network cksum error
162 #define SXG_RCV_STATUS_NETWORK_UFLOW 0x00820000 // Network underflow error
163 #define SXG_RCV_STATUS_NETWORK_HDRLEN 0x00800000 // Network header length
164 #define SXG_RCV_STATUS_NETWORK_OFLOW 0x00400000 // Network overflow detected
165 #define SXG_RCV_STATUS_NETWORK_MCAST 0x00200000 // Network multicast detected
166 #define SXG_RCV_STATUS_NETWORK_OPTIONS 0x00100000 // Network options detected
167 #define SXG_RCV_STATUS_NETWORK_OFFSET 0x00080000 // Network offset detected
168 #define SXG_RCV_STATUS_NETWORK_FRAGMENT 0x00040000 // Network fragment detected
169 #define SXG_RCV_STATUS_NETWORK_TRANS_MASK 0x00030000 // Network transport type mask
170 #define SXG_RCV_STATUS_NETWORK_UDP 0x00020000 // UDP
171 #define SXG_RCV_STATUS_NETWORK_TCP 0x00010000 // TCP
172 #define SXG_RCV_STATUS_IPONLY 0x00008000 // IP-only not TCP
173 #define SXG_RCV_STATUS_PKT_PRI 0x00006000 // Receive priority
174 #define SXG_RCV_STATUS_PKT_PRI_SHFT 13 // Receive priority shift
175 #define SXG_RCV_STATUS_PARITY 0x00001000 // MAC Receive RAM parity error
176 #define SXG_RCV_STATUS_ADDRESS_MASK 0x00000F00 // Link address detection mask
177 #define SXG_RCV_STATUS_ADDRESS_D 0x00000B00 // Link address D
178 #define SXG_RCV_STATUS_ADDRESS_C 0x00000A00 // Link address C
179 #define SXG_RCV_STATUS_ADDRESS_B 0x00000900 // Link address B
180 #define SXG_RCV_STATUS_ADDRESS_A 0x00000800 // Link address A
181 #define SXG_RCV_STATUS_ADDRESS_BCAST 0x00000300 // Link address broadcast
182 #define SXG_RCV_STATUS_ADDRESS_MCAST 0x00000200 // Link address multicast
183 #define SXG_RCV_STATUS_ADDRESS_CMCAST 0x00000100 // Link control multicast
184 #define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask
185 #define SXG_RCV_STATUS_LINK_ERROR 0x00000080 // Link error
186 #define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask
187 #define SXG_RCV_STATUS_LINK_PARITY 0x00000087 // RcvMacQ parity error
188 #define SXG_RCV_STATUS_LINK_EARLY 0x00000086 // Data early
189 #define SXG_RCV_STATUS_LINK_BUFOFLOW 0x00000085 // Buffer overflow
190 #define SXG_RCV_STATUS_LINK_CODE 0x00000084 // Link code error
191 #define SXG_RCV_STATUS_LINK_DRIBBLE 0x00000083 // Dribble nibble
192 #define SXG_RCV_STATUS_LINK_CRC 0x00000082 // CRC error
193 #define SXG_RCV_STATUS_LINK_OFLOW 0x00000081 // Link overflow
194 #define SXG_RCV_STATUS_LINK_UFLOW 0x00000080 // Link underflow
195 #define SXG_RCV_STATUS_LINK_8023 0x00000020 // 802.3
196 #define SXG_RCV_STATUS_LINK_SNAP 0x00000010 // Snap
197 #define SXG_RCV_STATUS_LINK_VLAN 0x00000008 // VLAN
198 #define SXG_RCV_STATUS_LINK_TYPE_MASK 0x00000007 // Network type mask
199 #define SXG_RCV_STATUS_LINK_CONTROL 0x00000003 // Control packet
200 #define SXG_RCV_STATUS_LINK_IPV6 0x00000002 // IPv6 packet
201 #define SXG_RCV_STATUS_LINK_IPV4 0x00000001 // IPv4 packet
202
203 /***************************************************************************
204 * Sahara receive and transmit configuration registers
205 ***************************************************************************/
206 #define RCV_CONFIG_RESET 0x80000000 // RcvConfig register reset
207 #define RCV_CONFIG_ENABLE 0x40000000 // Enable the receive logic
208 #define RCV_CONFIG_ENPARSE 0x20000000 // Enable the receive parser
209 #define RCV_CONFIG_SOCKET 0x10000000 // Enable the socket detector
210 #define RCV_CONFIG_RCVBAD 0x08000000 // Receive all bad frames
211 #define RCV_CONFIG_CONTROL 0x04000000 // Receive all control frames
212 #define RCV_CONFIG_RCVPAUSE 0x02000000 // Enable pause transmit when attn
213 #define RCV_CONFIG_TZIPV6 0x01000000 // Include TCP port w/ IPv6 toeplitz
214 #define RCV_CONFIG_TZIPV4 0x00800000 // Include TCP port w/ IPv4 toeplitz
215 #define RCV_CONFIG_FLUSH 0x00400000 // Flush buffers
216 #define RCV_CONFIG_PRIORITY_MASK 0x00300000 // Priority level
217 #define RCV_CONFIG_HASH_MASK 0x00030000 // Hash depth
218 #define RCV_CONFIG_HASH_8 0x00000000 // Hash depth 8
219 #define RCV_CONFIG_HASH_16 0x00010000 // Hash depth 16
220 #define RCV_CONFIG_HASH_4 0x00020000 // Hash depth 4
221 #define RCV_CONFIG_HASH_2 0x00030000 // Hash depth 2
222 #define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0 // Buffer length bits 15:4. ie multiple of 16.
223 #define RCV_CONFIG_SKT_DIS 0x00000008 // Disable socket detection on attn
224 // Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size.
225 // We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC,
226 // and round up to nearest 16 byte boundary
227 #define RCV_CONFIG_BUFSIZE(_MaxFrame) ((((_MaxFrame) + 22) + 15) & RCV_CONFIG_BUFLEN_MASK)
228
229 #define XMT_CONFIG_RESET 0x80000000 // XmtConfig register reset
230 #define XMT_CONFIG_ENABLE 0x40000000 // Enable transmit logic
231 #define XMT_CONFIG_MAC_PARITY 0x20000000 // Inhibit MAC RAM parity error
232 #define XMT_CONFIG_BUF_PARITY 0x10000000 // Inhibit D2F buffer parity error
233 #define XMT_CONFIG_MEM_PARITY 0x08000000 // Inhibit 1T SRAM parity error
234 #define XMT_CONFIG_INVERT_PARITY 0x04000000 // Invert MAC RAM parity
235 #define XMT_CONFIG_INITIAL_IPID 0x0000FFFF // Initial IPID
236
237 /***************************************************************************
238 * A-XGMAC Registers - Occupy 0x80 - 0xD4 of the SXG_HW_REGS
239 *
240 * Full register descriptions can be found in axgmac.pdf
241 ***************************************************************************/
242 // A-XGMAC Configuration Register 0
243 #define AXGMAC_CFG0_SUB_RESET 0x80000000 // Sub module reset
244 #define AXGMAC_CFG0_RCNTRL_RESET 0x00400000 // Receive control reset
245 #define AXGMAC_CFG0_RFUNC_RESET 0x00200000 // Receive function reset
246 #define AXGMAC_CFG0_TCNTRL_RESET 0x00040000 // Transmit control reset
247 #define AXGMAC_CFG0_TFUNC_RESET 0x00020000 // Transmit function reset
248 #define AXGMAC_CFG0_MII_RESET 0x00010000 // MII Management reset
249
250 // A-XGMAC Configuration Register 1
251 #define AXGMAC_CFG1_XMT_PAUSE 0x80000000 // Allow the sending of Pause frames
252 #define AXGMAC_CFG1_XMT_EN 0x40000000 // Enable transmit
253 #define AXGMAC_CFG1_RCV_PAUSE 0x20000000 // Allow the detection of Pause frames
254 #define AXGMAC_CFG1_RCV_EN 0x10000000 // Enable receive
255 #define AXGMAC_CFG1_XMT_STATE 0x04000000 // Current transmit state - READ ONLY
256 #define AXGMAC_CFG1_RCV_STATE 0x01000000 // Current receive state - READ ONLY
257 #define AXGMAC_CFG1_XOFF_SHORT 0x00001000 // Only pause for 64 slot on XOFF
258 #define AXGMAC_CFG1_XMG_FCS1 0x00000400 // Delay transmit FCS 1 4-byte word
259 #define AXGMAC_CFG1_XMG_FCS2 0x00000800 // Delay transmit FCS 2 4-byte words
260 #define AXGMAC_CFG1_XMG_FCS3 0x00000C00 // Delay transmit FCS 3 4-byte words
261 #define AXGMAC_CFG1_RCV_FCS1 0x00000100 // Delay receive FCS 1 4-byte word
262 #define AXGMAC_CFG1_RCV_FCS2 0x00000200 // Delay receive FCS 2 4-byte words
263 #define AXGMAC_CFG1_RCV_FCS3 0x00000300 // Delay receive FCS 3 4-byte words
264 #define AXGMAC_CFG1_PKT_OVERRIDE 0x00000080 // Per-packet override enable
265 #define AXGMAC_CFG1_SWAP 0x00000040 // Byte swap enable
266 #define AXGMAC_CFG1_SHORT_ASSERT 0x00000020 // ASSERT srdrpfrm on short frame (<64)
267 #define AXGMAC_CFG1_RCV_STRICT 0x00000010 // RCV only 802.3AE when CLEAR
268 #define AXGMAC_CFG1_CHECK_LEN 0x00000008 // Verify frame length
269 #define AXGMAC_CFG1_GEN_FCS 0x00000004 // Generate FCS
270 #define AXGMAC_CFG1_PAD_MASK 0x00000003 // Mask for pad bits
271 #define AXGMAC_CFG1_PAD_64 0x00000001 // Pad frames to 64 bytes
272 #define AXGMAC_CFG1_PAD_VLAN 0x00000002 // Detect VLAN and pad to 68 bytes
273 #define AXGMAC_CFG1_PAD_68 0x00000003 // Pad to 68 bytes
274
275 // A-XGMAC Configuration Register 2
276 #define AXGMAC_CFG2_GEN_PAUSE 0x80000000 // Generate single pause frame (test)
277 #define AXGMAC_CFG2_LF_MANUAL 0x08000000 // Manual link fault sequence
278 #define AXGMAC_CFG2_LF_AUTO 0x04000000 // Auto link fault sequence
279 #define AXGMAC_CFG2_LF_REMOTE 0x02000000 // Remote link fault (READ ONLY)
280 #define AXGMAC_CFG2_LF_LOCAL 0x01000000 // Local link fault (READ ONLY)
281 #define AXGMAC_CFG2_IPG_MASK 0x001F0000 // Inter packet gap
282 #define AXGMAC_CFG2_IPG_SHIFT 16
283 #define AXGMAC_CFG2_PAUSE_XMT 0x00008000 // Pause transmit module
284 #define AXGMAC_CFG2_IPG_EXTEN 0x00000020 // Enable IPG extension algorithm
285 #define AXGMAC_CFG2_IPGEX_MASK 0x0000001F // IPG extension
286
287 // A-XGMAC Configuration Register 3
288 #define AXGMAC_CFG3_RCV_DROP 0xFFFF0000 // Receive frame drop filter
289 #define AXGMAC_CFG3_RCV_DONT_CARE 0x0000FFFF // Receive frame don't care filter
290
291 // A-XGMAC Station Address Register - Octets 1-4
292 #define AXGMAC_SARLOW_OCTET_ONE 0xFF000000 // First octet
293 #define AXGMAC_SARLOW_OCTET_TWO 0x00FF0000 // Second octet
294 #define AXGMAC_SARLOW_OCTET_THREE 0x0000FF00 // Third octet
295 #define AXGMAC_SARLOW_OCTET_FOUR 0x000000FF // Fourth octet
296
297 // A-XGMAC Station Address Register - Octets 5-6
298 #define AXGMAC_SARHIGH_OCTET_FIVE 0xFF000000 // Fifth octet
299 #define AXGMAC_SARHIGH_OCTET_SIX 0x00FF0000 // Sixth octet
300
301 // A-XGMAC Maximum frame length register
302 #define AXGMAC_MAXFRAME_XMT 0x3FFF0000 // Maximum transmit frame length
303 #define AXGMAC_MAXFRAME_XMT_SHIFT 16
304 #define AXGMAC_MAXFRAME_RCV 0x0000FFFF // Maximum receive frame length
305 // This register doesn't need to be written for standard MTU.
306 // For jumbo, I'll just statically define the value here. This
307 // value sets the receive byte count to 9036 (0x234C) and the
308 // transmit WORD count to 2259 (0x8D3). These values include 22
309 // bytes of padding beyond the jumbo MTU of 9014
310 #define AXGMAC_MAXFRAME_JUMBO 0x08D3234C
311
312 // A-XGMAC Revision level
313 #define AXGMAC_REVISION_MASK 0x0000FFFF // Revision level
314
315 // A-XGMAC AMIIM Command Register
316 #define AXGMAC_AMIIM_CMD_START 0x00000008 // Command start
317 #define AXGMAC_AMIIM_CMD_MASK 0x00000007 // Command
318 #define AXGMAC_AMIIM_CMD_LEGACY_WRITE 1 // 10/100/1000 Mbps Phy Write
319 #define AXGMAC_AMIIM_CMD_LEGACY_READ 2 // 10/100/1000 Mbps Phy Read
320 #define AXGMAC_AMIIM_CMD_MONITOR_SINGLE 3 // Monitor single PHY
321 #define AXGMAC_AMIIM_CMD_MONITOR_MULTIPLE 4 // Monitor multiple contiguous PHYs
322 #define AXGMAC_AMIIM_CMD_10G_OPERATION 5 // Present AMIIM Field Reg
323 #define AXGMAC_AMIIM_CMD_CLEAR_LINK_FAIL 6 // Clear Link Fail Bit in MIIM
324
325 // A-XGMAC AMIIM Field Register
326 #define AXGMAC_AMIIM_FIELD_ST 0xC0000000 // 2-bit ST field
327 #define AXGMAC_AMIIM_FIELD_ST_SHIFT 30
328 #define AXGMAC_AMIIM_FIELD_OP 0x30000000 // 2-bit OP field
329 #define AXGMAC_AMIIM_FIELD_OP_SHIFT 28
330 #define AXGMAC_AMIIM_FIELD_PORT_ADDR 0x0F800000 // Port address field (hstphyadx in spec)
331 #define AXGMAC_AMIIM_FIELD_PORT_SHIFT 23
332 #define AXGMAC_AMIIM_FIELD_DEV_ADDR 0x007C0000 // Device address field (hstregadx in spec)
333 #define AXGMAC_AMIIM_FIELD_DEV_SHIFT 18
334 #define AXGMAC_AMIIM_FIELD_TA 0x00030000 // 2-bit TA field
335 #define AXGMAC_AMIIM_FIELD_TA_SHIFT 16
336 #define AXGMAC_AMIIM_FIELD_DATA 0x0000FFFF // Data field
337
338 // Values for the AXGMAC_AMIIM_FIELD_OP field in the A-XGMAC AMIIM Field Register
339 #define MIIM_OP_ADDR 0 // MIIM Address set operation
340 #define MIIM_OP_WRITE 1 // MIIM Write register operation
341 #define MIIM_OP_READ 2 // MIIM Read register operation
342 #define MIIM_OP_ADDR_SHIFT (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT)
343
344 // Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM Field Register
345 #define MIIM_PORT_NUM 1 // All Sahara MIIM modules use port 1
346
347 // Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM Field Register
348 #define MIIM_DEV_PHY_PMA 1 // PHY PMA/PMD module MIIM device number
349 #define MIIM_DEV_PHY_PCS 3 // PHY PCS module MIIM device number
350 #define MIIM_DEV_PHY_XS 4 // PHY XS module MIIM device number
351 #define MIIM_DEV_XGXS 5 // XGXS MIIM device number
352
353 // Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field Register
354 #define MIIM_TA_10GB 2 // set to 2 for 10 GB operation
355
356 // A-XGMAC AMIIM Configuration Register
357 #define AXGMAC_AMIIM_CFG_NOPREAM 0x00000080 // Bypass preamble of mngmt frame
358 #define AXGMAC_AMIIM_CFG_HALF_CLOCK 0x0000007F // half-clock duration of MDC output
359
360 // A-XGMAC AMIIM Indicator Register
361 #define AXGMAC_AMIIM_INDC_LINK 0x00000010 // Link status from legacy PHY or MMD
362 #define AXGMAC_AMIIM_INDC_MPHY 0x00000008 // Multiple phy operation in progress
363 #define AXGMAC_AMIIM_INDC_SPHY 0x00000004 // Single phy operation in progress
364 #define AXGMAC_AMIIM_INDC_MON 0x00000002 // Single or multiple monitor cmd
365 #define AXGMAC_AMIIM_INDC_BUSY 0x00000001 // Set until cmd operation complete
366
367 // Link Status and Control Register
368 #define LS_PHY_CLR_RESET 0x80000000 // Clear reset signal to PHY
369 #define LS_SERDES_POWER_DOWN 0x40000000 // Power down the Sahara Serdes
370 #define LS_XGXS_ENABLE 0x20000000 // Enable the XAUI XGXS logic
371 #define LS_XGXS_CTL 0x10000000 // Hold XAUI XGXS logic reset until Serdes is up
372 #define LS_SERDES_DOWN 0x08000000 // When 0, XAUI Serdes is up and initialization is complete
373 #define LS_TRACE_DOWN 0x04000000 // When 0, Trace Serdes is up and initialization is complete
374 #define LS_PHY_CLK_25MHZ 0x02000000 // Set PHY clock to 25 MHz (else 156.125 MHz)
375 #define LS_PHY_CLK_EN 0x01000000 // Enable clock to PHY
376 #define LS_XAUI_LINK_UP 0x00000010 // XAUI link is up
377 #define LS_XAUI_LINK_CHNG 0x00000008 // XAUI link status has changed
378 #define LS_LINK_ALARM 0x00000004 // Link alarm pin
379 #define LS_ATTN_CTRL_MASK 0x00000003 // Mask link attention control bits
380 #define LS_ATTN_ALARM 0x00000000 // 00 => Attn on link alarm
381 #define LS_ATTN_ALARM_OR_STAT_CHNG 0x00000001 // 01 => Attn on link alarm or status change
382 #define LS_ATTN_STAT_CHNG 0x00000002 // 10 => Attn on link status change
383 #define LS_ATTN_NONE 0x00000003 // 11 => no Attn
384
385 // Link Address High Registers
386 #define LINK_ADDR_ENABLE 0x80000000 // Enable this link address
387
388
389 /***************************************************************************
390 * XGXS XAUI XGMII Extender registers
391 *
392 * Full register descriptions can be found in mxgxs.pdf
393 ***************************************************************************/
394 // XGXS Register Map
395 #define XGXS_ADDRESS_CONTROL1 0x0000 // XS Control 1
396 #define XGXS_ADDRESS_STATUS1 0x0001 // XS Status 1
397 #define XGXS_ADDRESS_DEVID_LOW 0x0002 // XS Device ID (low)
398 #define XGXS_ADDRESS_DEVID_HIGH 0x0003 // XS Device ID (high)
399 #define XGXS_ADDRESS_SPEED 0x0004 // XS Speed ability
400 #define XGXS_ADDRESS_DEV_LOW 0x0005 // XS Devices in package
401 #define XGXS_ADDRESS_DEV_HIGH 0x0006 // XS Devices in package
402 #define XGXS_ADDRESS_STATUS2 0x0008 // XS Status 2
403 #define XGXS_ADDRESS_PKGID_lOW 0x000E // XS Package Identifier
404 #define XGXS_ADDRESS_PKGID_HIGH 0x000F // XS Package Identifier
405 #define XGXS_ADDRESS_LANE_STATUS 0x0018 // 10G XGXS Lane Status
406 #define XGXS_ADDRESS_TEST_CTRL 0x0019 // 10G XGXS Test Control
407 #define XGXS_ADDRESS_RESET_LO1 0x8000 // Vendor-Specific Reset Lo 1
408 #define XGXS_ADDRESS_RESET_LO2 0x8001 // Vendor-Specific Reset Lo 2
409 #define XGXS_ADDRESS_RESET_HI1 0x8002 // Vendor-Specific Reset Hi 1
410 #define XGXS_ADDRESS_RESET_HI2 0x8003 // Vendor-Specific Reset Hi 2
411
412 // XS Control 1 register bit definitions
413 #define XGXS_CONTROL1_RESET 0x8000 // Reset - self clearing
414 #define XGXS_CONTROL1_LOOPBACK 0x4000 // Enable loopback
415 #define XGXS_CONTROL1_SPEED1 0x2000 // 0 = unspecified, 1 = 10Gb+
416 #define XGXS_CONTROL1_LOWPOWER 0x0400 // 1 = Low power mode
417 #define XGXS_CONTROL1_SPEED2 0x0040 // Same as SPEED1 (?)
418 #define XGXS_CONTROL1_SPEED 0x003C // Everything reserved except zero (?)
419
420 // XS Status 1 register bit definitions
421 #define XGXS_STATUS1_FAULT 0x0080 // Fault detected
422 #define XGXS_STATUS1_LINK 0x0004 // 1 = Link up
423 #define XGXS_STATUS1_LOWPOWER 0x0002 // 1 = Low power supported
424
425 // XS Speed register bit definitions
426 #define XGXS_SPEED_10G 0x0001 // 1 = 10G capable
427
428 // XS Devices register bit definitions
429 #define XGXS_DEVICES_DTE 0x0020 // DTE XS Present
430 #define XGXS_DEVICES_PHY 0x0010 // PHY XS Present
431 #define XGXS_DEVICES_PCS 0x0008 // PCS Present
432 #define XGXS_DEVICES_WIS 0x0004 // WIS Present
433 #define XGXS_DEVICES_PMD 0x0002 // PMD/PMA Present
434 #define XGXS_DEVICES_CLAUSE22 0x0001 // Clause 22 registers present
435
436 // XS Devices High register bit definitions
437 #define XGXS_DEVICES_VENDOR2 0x8000 // Vendor specific device 2
438 #define XGXS_DEVICES_VENDOR1 0x4000 // Vendor specific device 1
439
440 // XS Status 2 register bit definitions
441 #define XGXS_STATUS2_DEV_MASK 0xC000 // Device present mask
442 #define XGXS_STATUS2_DEV_RESPOND 0x8000 // Device responding
443 #define XGXS_STATUS2_XMT_FAULT 0x0800 // Transmit fault
444 #define XGXS_STATUS2_RCV_FAULT 0x0400 // Receive fault
445
446 // XS Package ID High register bit definitions
447 #define XGXS_PKGID_HIGH_ORG 0xFC00 // Organizationally Unique
448 #define XGXS_PKGID_HIGH_MFG 0x03F0 // Manufacturer Model
449 #define XGXS_PKGID_HIGH_REV 0x000F // Revision Number
450
451 // XS Lane Status register bit definitions
452 #define XGXS_LANE_PHY 0x1000 // PHY/DTE lane alignment status
453 #define XGXS_LANE_PATTERN 0x0800 // Pattern testing ability
454 #define XGXS_LANE_LOOPBACK 0x0400 // PHY loopback ability
455 #define XGXS_LANE_SYNC3 0x0008 // Lane 3 sync
456 #define XGXS_LANE_SYNC2 0x0004 // Lane 2 sync
457 #define XGXS_LANE_SYNC1 0x0002 // Lane 1 sync
458 #define XGXS_LANE_SYNC0 0x0001 // Lane 0 sync
459
460 // XS Test Control register bit definitions
461 #define XGXS_TEST_PATTERN_ENABLE 0x0004 // Test pattern enabled
462 #define XGXS_TEST_PATTERN_MASK 0x0003 // Test patterns
463 #define XGXS_TEST_PATTERN_RSVD 0x0003 // Test pattern - reserved
464 #define XGXS_TEST_PATTERN_MIX 0x0002 // Test pattern - mixed
465 #define XGXS_TEST_PATTERN_LOW 0x0001 // Test pattern - low
466 #define XGXS_TEST_PATTERN_HIGH 0x0001 // Test pattern - high
467
468 /***************************************************************************
469 * External MDIO Bus Registers
470 *
471 * Full register descriptions can be found in PHY/XENPAK/IEEE specs
472 ***************************************************************************/
473 // LASI (Link Alarm Status Interrupt) Registers (located in MIIM_DEV_PHY_PMA device)
474 #define LASI_RX_ALARM_CONTROL 0x9000 // LASI RX_ALARM Control
475 #define LASI_TX_ALARM_CONTROL 0x9001 // LASI TX_ALARM Control
476 #define LASI_CONTROL 0x9002 // LASI Control
477 #define LASI_RX_ALARM_STATUS 0x9003 // LASI RX_ALARM Status
478 #define LASI_TX_ALARM_STATUS 0x9004 // LASI TX_ALARM Status
479 #define LASI_STATUS 0x9005 // LASI Status
480
481 // LASI_CONTROL bit definitions
482 #define LASI_CTL_RX_ALARM_ENABLE 0x0004 // Enable RX_ALARM interrupts
483 #define LASI_CTL_TX_ALARM_ENABLE 0x0002 // Enable TX_ALARM interrupts
484 #define LASI_CTL_LS_ALARM_ENABLE 0x0001 // Enable Link Status interrupts
485
486 // LASI_STATUS bit definitions
487 #define LASI_STATUS_RX_ALARM 0x0004 // RX_ALARM status
488 #define LASI_STATUS_TX_ALARM 0x0002 // TX_ALARM status
489 #define LASI_STATUS_LS_ALARM 0x0001 // Link Status
490
491 // PHY registers - PMA/PMD (device 1)
492 #define PHY_PMA_CONTROL1 0x0000 // PMA/PMD Control 1
493 #define PHY_PMA_STATUS1 0x0001 // PMA/PMD Status 1
494 #define PHY_PMA_RCV_DET 0x000A // PMA/PMD Receive Signal Detect
495 // other PMA/PMD registers exist and can be defined as needed
496
497 // PHY registers - PCS (device 3)
498 #define PHY_PCS_CONTROL1 0x0000 // PCS Control 1
499 #define PHY_PCS_STATUS1 0x0001 // PCS Status 1
500 #define PHY_PCS_10G_STATUS1 0x0020 // PCS 10GBASE-R Status 1
501 // other PCS registers exist and can be defined as needed
502
503 // PHY registers - XS (device 4)
504 #define PHY_XS_CONTROL1 0x0000 // XS Control 1
505 #define PHY_XS_STATUS1 0x0001 // XS Status 1
506 #define PHY_XS_LANE_STATUS 0x0018 // XS Lane Status
507 // other XS registers exist and can be defined as needed
508
509 // PHY_PMA_CONTROL1 register bit definitions
510 #define PMA_CONTROL1_RESET 0x8000 // PMA/PMD reset
511
512 // PHY_PMA_RCV_DET register bit definitions
513 #define PMA_RCV_DETECT 0x0001 // PMA/PMD receive signal detect
514
515 // PHY_PCS_10G_STATUS1 register bit definitions
516 #define PCS_10B_BLOCK_LOCK 0x0001 // PCS 10GBASE-R locked to receive blocks
517
518 // PHY_XS_LANE_STATUS register bit definitions
519 #define XS_LANE_ALIGN 0x1000 // XS transmit lanes aligned
520
521 // PHY Microcode download data structure
522 struct PHY_UCODE {
523 ushort Addr;
524 ushort Data;
525 };
526
527
528 /*****************************************************************************
529 * Transmit Sequencer Command Descriptor definitions
530 *****************************************************************************/
531
532 // This descriptor must be placed in GRAM. The address of this descriptor
533 // (along with a couple of control bits) is pushed onto the PxhCmdQ or PxlCmdQ
534 // (Proxy high or low command queue). This data is read by the Proxy Sequencer,
535 // which pushes it onto the XmtCmdQ, which is (eventually) read by the Transmit
536 // Sequencer, causing a packet to be transmitted. Not all fields are valid for
537 // all commands - see the Sahara spec for details. Note that this structure is
538 // only valid when compiled on a little endian machine.
539 #pragma pack(push, 1)
540 struct XMT_DESC {
541 ushort XmtLen; // word 0, bits [15:0] - transmit length
542 unsigned char XmtCtl; // word 0, bits [23:16] - transmit control byte
543 unsigned char Cmd; // word 0, bits [31:24] - transmit command plus misc.
544 u32 XmtBufId; // word 1, bits [31:0] - transmit buffer ID
545 unsigned char TcpStrt; // word 2, bits [7:0] - byte address of TCP header
546 unsigned char IpStrt; // word 2, bits [15:8] - byte address of IP header
547 ushort IpCkSum; // word 2, bits [31:16] - partial IP checksum
548 ushort TcpCkSum; // word 3, bits [15:0] - partial TCP checksum
549 ushort Rsvd1; // word 3, bits [31:16] - PAD
550 u32 Rsvd2; // word 4, bits [31:0] - PAD
551 u32 Rsvd3; // word 5, bits [31:0] - PAD
552 u32 Rsvd4; // word 6, bits [31:0] - PAD
553 u32 Rsvd5; // word 7, bits [31:0] - PAD
554 };
555 #pragma pack(pop)
556
557 // XMT_DESC Cmd byte definitions
558 // command codes
559 #define XMT_DESC_CMD_RAW_SEND 0 // raw send descriptor
560 #define XMT_DESC_CMD_CSUM_INSERT 1 // checksum insert descriptor
561 #define XMT_DESC_CMD_FORMAT 2 // format descriptor
562 #define XMT_DESC_CMD_PRIME 3 // prime descriptor
563 #define XMT_DESC_CMD_CODE_SHFT 6 // comand code shift (shift to bits [31:30] in word 0)
564 // shifted command codes
565 #define XMT_RAW_SEND (XMT_DESC_CMD_RAW_SEND << XMT_DESC_CMD_CODE_SHFT)
566 #define XMT_CSUM_INSERT (XMT_DESC_CMD_CSUM_INSERT << XMT_DESC_CMD_CODE_SHFT)
567 #define XMT_FORMAT (XMT_DESC_CMD_FORMAT << XMT_DESC_CMD_CODE_SHFT)
568 #define XMT_PRIME (XMT_DESC_CMD_PRIME << XMT_DESC_CMD_CODE_SHFT)
569
570 // XMT_DESC Control Byte (XmtCtl) definitions
571 // NOTE: These bits do not work on Sahara (Rev A)!
572 #define XMT_CTL_PAUSE_FRAME 0x80 // current frame is a pause control frame (for statistics)
573 #define XMT_CTL_CONTROL_FRAME 0x40 // current frame is a control frame (for statistics)
574 #define XMT_CTL_PER_PKT_QUAL 0x20 // per packet qualifier
575 #define XMT_CTL_PAD_MODE_NONE 0x00 // do not pad frame
576 #define XMT_CTL_PAD_MODE_64 0x08 // pad frame to 64 bytes
577 #define XMT_CTL_PAD_MODE_VLAN_68 0x10 // pad frame to 64 bytes, and VLAN frames to 68 bytes
578 #define XMT_CTL_PAD_MODE_68 0x18 // pad frame to 68 bytes
579 #define XMT_CTL_GEN_FCS 0x04 // generate FCS (CRC) for this frame
580 #define XMT_CTL_DELAY_FCS_0 0x00 // do not delay FCS calcution
581 #define XMT_CTL_DELAY_FCS_1 0x01 // delay FCS calculation by 1 (4-byte) word
582 #define XMT_CTL_DELAY_FCS_2 0x02 // delay FCS calculation by 2 (4-byte) words
583 #define XMT_CTL_DELAY_FCS_3 0x03 // delay FCS calculation by 3 (4-byte) words
584
585 // XMT_DESC XmtBufId definition
586 #define XMT_BUF_ID_SHFT 8 // The Xmt buffer ID is formed by dividing
587 // the buffer (DRAM) address by 256 (or << 8)
588
589 /*****************************************************************************
590 * Receiver Sequencer Definitions
591 *****************************************************************************/
592
593 // Receive Event Queue (queues 3 - 6) bit definitions
594 #define RCV_EVTQ_RBFID_MASK 0x0000FFFF // bit mask for the Receive Buffer ID
595
596 // Receive Buffer ID definition
597 #define RCV_BUF_ID_SHFT 5 // The Rcv buffer ID is formed by dividing
598 // the buffer (DRAM) address by 32 (or << 5)
599
600 // Format of the 18 byte Receive Buffer returned by the
601 // Receive Sequencer for received packets
602 #pragma pack(push, 1)
603 struct RCV_BUF_HDR {
604 u32 Status; // Status word from Rcv Seq Parser
605 ushort Length; // Rcv packet byte count
606 union {
607 ushort TcpCsum; // TCP checksum
608 struct {
609 unsigned char TcpCsumL; // lower 8 bits of the TCP checksum
610 unsigned char LinkHash; // Link hash (multicast frames only)
611 };
612 };
613 ushort SktHash; // Socket hash
614 unsigned char TcpHdrOffset; // TCP header offset into packet
615 unsigned char IpHdrOffset; // IP header offset into packet
616 u32 TpzHash; // Toeplitz hash
617 ushort Reserved; // Reserved
618 };
619 #pragma pack(pop)
620
621
622 /*****************************************************************************
623 * Queue definitions
624 *****************************************************************************/
625
626 /* Ingress (read only) queue numbers */
627 #define PXY_BUF_Q 0 /* Proxy Buffer Queue */
628 #define HST_EVT_Q 1 /* Host Event Queue */
629 #define XMT_BUF_Q 2 /* Transmit Buffer Queue */
630 #define SKT_EVL_Q 3 /* RcvSqr Socket Event Low Priority Queue */
631 #define RCV_EVL_Q 4 /* RcvSqr Rcv Event Low Priority Queue */
632 #define SKT_EVH_Q 5 /* RcvSqr Socket Event High Priority Queue */
633 #define RCV_EVH_Q 6 /* RcvSqr Rcv Event High Priority Queue */
634 #define DMA_RSP_Q 7 /* Dma Response Queue - one per CPU context */
635 /* Local (read/write) queue numbers */
636 #define LOCAL_A_Q 8 /* Spare local Queue */
637 #define LOCAL_B_Q 9 /* Spare local Queue */
638 #define LOCAL_C_Q 10 /* Spare local Queue */
639 #define FSM_EVT_Q 11 /* Finite-State-Machine Event Queue */
640 #define SBF_PAL_Q 12 /* System Buffer Physical Address (low) Queue */
641 #define SBF_PAH_Q 13 /* System Buffer Physical Address (high) Queue */
642 #define SBF_VAL_Q 14 /* System Buffer Virtual Address (low) Queue */
643 #define SBF_VAH_Q 15 /* System Buffer Virtual Address (high) Queue */
644 /* Egress (write only) queue numbers */
645 #define H2G_CMD_Q 16 /* Host to GlbRam DMA Command Queue */
646 #define H2D_CMD_Q 17 /* Host to DRAM DMA Command Queue */
647 #define G2H_CMD_Q 18 /* GlbRam to Host DMA Command Queue */
648 #define G2D_CMD_Q 19 /* GlbRam to DRAM DMA Command Queue */
649 #define D2H_CMD_Q 20 /* DRAM to Host DMA Command Queue */
650 #define D2G_CMD_Q 21 /* DRAM to GlbRam DMA Command Queue */
651 #define D2D_CMD_Q 22 /* DRAM to DRAM DMA Command Queue */
652 #define PXL_CMD_Q 23 /* Low Priority Proxy Command Queue */
653 #define PXH_CMD_Q 24 /* High Priority Proxy Command Queue */
654 #define RSQ_CMD_Q 25 /* Receive Sequencer Command Queue */
655 #define RCV_BUF_Q 26 /* Receive Buffer Queue */
656
657 /* Bit definitions for the Proxy Command queues (PXL_CMD_Q and PXH_CMD_Q) */
658 #define PXY_COPY_EN 0x00200000 /* enable copy of xmt descriptor to xmt command queue */
659 #define PXY_SIZE_16 0x00000000 /* copy 16 bytes */
660 #define PXY_SIZE_32 0x00100000 /* copy 32 bytes */
661
662 /*****************************************************************************
663 * SXG EEPROM/Flash Configuration Definitions
664 *****************************************************************************/
665 #pragma pack(push, 1)
666
667 /* */
668 struct HW_CFG_DATA {
669 ushort Addr;
670 union {
671 ushort Data;
672 ushort Checksum;
673 };
674 };
675
676 /* */
677 #define NUM_HW_CFG_ENTRIES ((128/sizeof(struct HW_CFG_DATA)) - 4)
678
679 /* MAC address */
680 struct SXG_CONFIG_MAC {
681 unsigned char MacAddr[6]; /* MAC Address */
682 };
683
684 /* */
685 struct ATK_FRU {
686 unsigned char PartNum[6];
687 unsigned char Revision[2];
688 unsigned char Serial[14];
689 };
690
691 /* OEM FRU Format types */
692 #define ATK_FRU_FORMAT 0x0000
693 #define CPQ_FRU_FORMAT 0x0001
694 #define DELL_FRU_FORMAT 0x0002
695 #define HP_FRU_FORMAT 0x0003
696 #define IBM_FRU_FORMAT 0x0004
697 #define EMC_FRU_FORMAT 0x0005
698 #define NO_FRU_FORMAT 0xFFFF
699
700 /* EEPROM/Flash Format */
701 struct SXG_CONFIG {
702 /* */
703 /* Section 1 (128 bytes) */
704 /* */
705 ushort MagicWord; /* EEPROM/FLASH Magic code 'A5A5' */
706 ushort SpiClks; /* SPI bus clock dividers */
707 struct HW_CFG_DATA HwCfg[NUM_HW_CFG_ENTRIES];
708 /* */
709 /* */
710 /* */
711 ushort Version; /* EEPROM format version */
712 struct SXG_CONFIG_MAC MacAddr[4]; /* space for 4 MAC addresses */
713 struct ATK_FRU AtkFru; /* FRU information */
714 ushort OemFruFormat; /* OEM FRU format type */
715 unsigned char OemFru[76]; /* OEM FRU information (optional) */
716 ushort Checksum; /* Checksum of section 2 */
717 /* CS info XXXTODO */
718 };
719 #pragma pack(pop)
720
721 /*****************************************************************************
722 * Miscellaneous Hardware definitions
723 *****************************************************************************/
724
725 // Sahara (ASIC level) defines
726 #define SAHARA_GRAM_SIZE 0x020000 // GRAM size - 128 KB
727 #define SAHARA_DRAM_SIZE 0x200000 // DRAM size - 2 MB
728 #define SAHARA_QRAM_SIZE 0x004000 // QRAM size - 16K entries (64 KB)
729 #define SAHARA_WCS_SIZE 0x002000 // WCS - 8K instructions (x 108 bits)
730
731 // Arabia (board level) defines
732 #define FLASH_SIZE 0x080000 // 512 KB (4 Mb)
733 #define EEPROM_SIZE_XFMR 512 // true EEPROM size (bytes), including xfmr area
734 #define EEPROM_SIZE_NO_XFMR 256 // EEPROM size excluding xfmr area
Linux for Ginger Game Console