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ide: move ->failed_pc to ide_drive_t
[linux-ginger.git] / drivers / staging / winbond / reg.c
blobcd21272d7a9f5a7bed46d3029d3f30ce4b6d5456
1 #include "os_common.h"
2 #include "wbhal_f.h"
3
4 ///////////////////////////////////////////////////////////////////////////////////////////////////
5 // Original Phy.h
6 //*****************************************************************************
7
8 /*****************************************************************************
9 ; For MAXIM2825/6/7 Ver. 331 or more
10 ; Edited by Tiger, Sep-17-2003
11 ; revised by Ben, Sep-18-2003
12
13 0x00 0x000a2
14 0x01 0x21cc0
15 ;0x02 0x13802
16 0x02 0x1383a
17
18 ;channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333;
19 ;channe1 02 ;0x03 0x32141 ;0x04 0x08444;
20 ;channe1 03 ;0x03 0x32143 ;0x04 0x0aeee;
21 ;channe1 04 ;0x03 0x32142 ;0x04 0x0b333;
22 ;channe1 05 ;0x03 0x31141 ;0x04 0x08444;
23 ;channe1 06 ;
24 0x03 0x31143;
25 0x04 0x0aeee;
26 ;channe1 07 ;0x03 0x31142 ;0x04 0x0b333;
27 ;channe1 08 ;0x03 0x33141 ;0x04 0x08444;
28 ;channe1 09 ;0x03 0x33143 ;0x04 0x0aeee;
29 ;channe1 10 ;0x03 0x33142 ;0x04 0x0b333;
30 ;channe1 11 ;0x03 0x30941 ;0x04 0x08444;
31 ;channe1 12 ;0x03 0x30943 ;0x04 0x0aeee;
32 ;channe1 13 ;0x03 0x30942 ;0x04 0x0b333;
33
34 0x05 0x28986
35 0x06 0x18008
36 0x07 0x38400
37 0x08 0x05100; 100 Hz DC
38 ;0x08 0x05900; 30 KHz DC
39 0x09 0x24f08
40 0x0a 0x17e00, 0x17ea0
41 0x0b 0x37d80
42 0x0c 0x0c900 // 0x0ca00 (lager power 9db than 0x0c000), 0x0c000
43 *****************************************************************************/
44 // MAX2825 (pure b/g)
45 u32 max2825_rf_data[] =
46 {
47 (0x00<<18)|0x000a2,
48 (0x01<<18)|0x21cc0,
49 (0x02<<18)|0x13806,
50 (0x03<<18)|0x30142,
51 (0x04<<18)|0x0b333,
52 (0x05<<18)|0x289A6,
53 (0x06<<18)|0x18008,
54 (0x07<<18)|0x38000,
55 (0x08<<18)|0x05100,
56 (0x09<<18)|0x24f08,
57 (0x0A<<18)|0x14000,
58 (0x0B<<18)|0x37d80,
59 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
60 };
61
62 u32 max2825_channel_data_24[][3] =
63 {
64 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
65 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
66 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
67 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
68 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
69 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
70 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
71 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
72 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
73 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
74 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
75 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
76 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
77 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
78 };
79
80 u32 max2825_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
81
82 /****************************************************************************/
83 // MAX2827 (a/b/g)
84 u32 max2827_rf_data[] =
85 {
86 (0x00<<18)|0x000a2,
87 (0x01<<18)|0x21cc0,
88 (0x02<<18)|0x13806,
89 (0x03<<18)|0x30142,
90 (0x04<<18)|0x0b333,
91 (0x05<<18)|0x289A6,
92 (0x06<<18)|0x18008,
93 (0x07<<18)|0x38000,
94 (0x08<<18)|0x05100,
95 (0x09<<18)|0x24f08,
96 (0x0A<<18)|0x14000,
97 (0x0B<<18)|0x37d80,
98 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
99 };
100
101 u32 max2827_channel_data_24[][3] =
102 {
103 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
104 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
105 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
106 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
107 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
108 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
109 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
110 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
111 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
112 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
113 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
114 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
115 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
116 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
117 };
118
119 u32 max2827_channel_data_50[][3] =
120 {
121 {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 36
122 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 40
123 {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6}, // channel 44
124 {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x2A9A6}, // channel 48
125 {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x2A9A6}, // channel 52
126 {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 56
127 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 60
128 {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6} // channel 64
129 };
130
131 u32 max2827_power_data_24[] = {(0x0C<<18)|0x0C000, (0x0C<<18)|0x0D600, (0x0C<<18)|0x0C100};
132 u32 max2827_power_data_50[] = {(0x0C<<18)|0x0C400, (0x0C<<18)|0x0D500, (0x0C<<18)|0x0C300};
133
134 /****************************************************************************/
135 // MAX2828 (a/b/g)
136 u32 max2828_rf_data[] =
137 {
138 (0x00<<18)|0x000a2,
139 (0x01<<18)|0x21cc0,
140 (0x02<<18)|0x13806,
141 (0x03<<18)|0x30142,
142 (0x04<<18)|0x0b333,
143 (0x05<<18)|0x289A6,
144 (0x06<<18)|0x18008,
145 (0x07<<18)|0x38000,
146 (0x08<<18)|0x05100,
147 (0x09<<18)|0x24f08,
148 (0x0A<<18)|0x14000,
149 (0x0B<<18)|0x37d80,
150 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
151 };
152
153 u32 max2828_channel_data_24[][3] =
154 {
155 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
156 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
157 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
158 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
159 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
160 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
161 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
162 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
163 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
164 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
165 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
166 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
167 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
168 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
169 };
170
171 u32 max2828_channel_data_50[][3] =
172 {
173 {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 36
174 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 40
175 {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channel 44
176 {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x289A6}, // channel 48
177 {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x289A6}, // channel 52
178 {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 56
179 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 60
180 {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6} // channel 64
181 };
182
183 u32 max2828_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
184 u32 max2828_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
185
186 /****************************************************************************/
187 // LA20040728 kevin
188 // MAX2829 (a/b/g)
189 u32 max2829_rf_data[] =
190 {
191 (0x00<<18)|0x000a2,
192 (0x01<<18)|0x23520,
193 (0x02<<18)|0x13802,
194 (0x03<<18)|0x30142,
195 (0x04<<18)|0x0b333,
196 (0x05<<18)|0x28906,
197 (0x06<<18)|0x18008,
198 (0x07<<18)|0x3B500,
199 (0x08<<18)|0x05100,
200 (0x09<<18)|0x24f08,
201 (0x0A<<18)|0x14000,
202 (0x0B<<18)|0x37d80,
203 (0x0C<<18)|0x0F300 //TXVGA=51, (MAX-6 dB)
204 };
205
206 u32 max2829_channel_data_24[][3] =
207 {
208 {(3<<18)|0x30142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 01 (2412MHz)
209 {(3<<18)|0x32141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 02 (2417MHz)
210 {(3<<18)|0x32143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 03 (2422MHz)
211 {(3<<18)|0x32142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 04 (2427MHz)
212 {(3<<18)|0x31141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 05 (2432MHz)
213 {(3<<18)|0x31143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 06 (2437MHz)
214 {(3<<18)|0x31142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 07 (2442MHz)
215 {(3<<18)|0x33141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 08 (2447MHz)
216 {(3<<18)|0x33143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 09 (2452MHz)
217 {(3<<18)|0x33142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 10 (2457MHz)
218 {(3<<18)|0x30941, (4<<18)|0x08444, (5<<18)|0x289C6}, // 11 (2462MHz)
219 {(3<<18)|0x30943, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 12 (2467MHz)
220 {(3<<18)|0x30942, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 13 (2472MHz)
221 {(3<<18)|0x32941, (4<<18)|0x09999, (5<<18)|0x289C6}, // 14 (2484MHz) hh-modify
222 };
223
224 u32 max2829_channel_data_50[][4] =
225 {
226 {36, (3<<18)|0x33cc3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 36 (5.180GHz)
227 {40, (3<<18)|0x302c0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 40 (5.200GHz)
228 {44, (3<<18)|0x302c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 44 (5.220GHz)
229 {48, (3<<18)|0x322c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 48 (5.240GHz)
230 {52, (3<<18)|0x312c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 52 (5.260GHz)
231 {56, (3<<18)|0x332c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 56 (5.280GHz)
232 {60, (3<<18)|0x30ac0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 60 (5.300GHz)
233 {64, (3<<18)|0x30ac2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 64 (5.320GHz)
234
235 {100, (3<<18)|0x30ec0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 100 (5.500GHz)
236 {104, (3<<18)|0x30ec2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 104 (5.520GHz)
237 {108, (3<<18)|0x32ec1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 108 (5.540GHz)
238 {112, (3<<18)|0x31ec1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 112 (5.560GHz)
239 {116, (3<<18)|0x33ec3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 116 (5.580GHz)
240 {120, (3<<18)|0x301c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 120 (5.600GHz)
241 {124, (3<<18)|0x301c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 124 (5.620GHz)
242 {128, (3<<18)|0x321c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 128 (5.640GHz)
243 {132, (3<<18)|0x311c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 132 (5.660GHz)
244 {136, (3<<18)|0x331c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 136 (5.680GHz)
245 {140, (3<<18)|0x309c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 140 (5.700GHz)
246
247 {149, (3<<18)|0x329c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 149 (5.745GHz)
248 {153, (3<<18)|0x319c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 153 (5.765GHz)
249 {157, (3<<18)|0x339c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 157 (5.785GHz)
250 {161, (3<<18)|0x305c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 161 (5.805GHz)
251
252 // Japan
253 { 184, (3<<18)|0x308c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 184 (4.920GHz)
254 { 188, (3<<18)|0x328c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 188 (4.940GHz)
255 { 192, (3<<18)|0x318c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 192 (4.960GHz)
256 { 196, (3<<18)|0x338c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 196 (4.980GHz)
257 { 8, (3<<18)|0x324c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 8 (5.040GHz)
258 { 12, (3<<18)|0x314c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 12 (5.060GHz)
259 { 16, (3<<18)|0x334c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 16 (5.080GHz)
260 { 34, (3<<18)|0x31cc2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 34 (5.170GHz)
261 { 38, (3<<18)|0x33cc1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 38 (5.190GHz)
262 { 42, (3<<18)|0x302c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 42 (5.210GHz)
263 { 46, (3<<18)|0x322c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 46 (5.230GHz)
264 };
265
266 /*****************************************************************************
267 ; For MAXIM2825/6/7 Ver. 317 or less
268 ; Edited by Tiger, Sep-17-2003 for 2.4Ghz channels
269 ; Updated by Tiger, Sep-22-2003 for 5.0Ghz channels
270 ; Corrected by Tiger, Sep-23-2003, for 0x03 and 0x04 of 5.0Ghz channels
271
272 0x00 0x00080
273 0x01 0x214c0
274 0x02 0x13802
275
276 ;2.4GHz Channels
277 ;channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc
278 ;channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111
279 ;channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb
280 ;channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc
281 ;channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111
282 ;channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb
283 ;channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc
284 ;channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111
285 ;channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb
286 ;channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc
287 ;channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111
288 ;channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb
289 ;channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc
290
291 ;5.0Ghz Channels
292 ;channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333
293 ;channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000
294 ;channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333
295 ;channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999
296 ;channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666
297 ;channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc
298 ;channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000
299 ;channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333
300
301 ;2.4GHz band ;0x05 0x28986;
302 ;5.0GHz band
303 0x05 0x2a986
304
305 0x06 0x18008
306 0x07 0x38400
307 0x08 0x05108
308 0x09 0x27ff8
309 0x0a 0x14000
310 0x0b 0x37f99
311 0x0c 0x0c000
312 *****************************************************************************/
313 u32 maxim_317_rf_data[] =
314 {
315 (0x00<<18)|0x000a2,
316 (0x01<<18)|0x214c0,
317 (0x02<<18)|0x13802,
318 (0x03<<18)|0x30143,
319 (0x04<<18)|0x0accc,
320 (0x05<<18)|0x28986,
321 (0x06<<18)|0x18008,
322 (0x07<<18)|0x38400,
323 (0x08<<18)|0x05108,
324 (0x09<<18)|0x27ff8,
325 (0x0A<<18)|0x14000,
326 (0x0B<<18)|0x37f99,
327 (0x0C<<18)|0x0c000
328 };
329
330 u32 maxim_317_channel_data_24[][3] =
331 {
332 {(0x03<<18)|0x30143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 01
333 {(0x03<<18)|0x32140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 02
334 {(0x03<<18)|0x32142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 03
335 {(0x03<<18)|0x32143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 04
336 {(0x03<<18)|0x31140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 05
337 {(0x03<<18)|0x31142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 06
338 {(0x03<<18)|0x31143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 07
339 {(0x03<<18)|0x33140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 08
340 {(0x03<<18)|0x33142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 09
341 {(0x03<<18)|0x33143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 10
342 {(0x03<<18)|0x30940, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 11
343 {(0x03<<18)|0x30942, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 12
344 {(0x03<<18)|0x30943, (0x04<<18)|0x0accc, (0x05<<18)|0x28986} // channe1 13
345 };
346
347 u32 maxim_317_channel_data_50[][3] =
348 {
349 {(0x03<<18)|0x33cc0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a986}, // channel 36
350 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2a986}, // channel 40
351 {(0x03<<18)|0x302c3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a986}, // channel 44
352 {(0x03<<18)|0x322c1, (0x04<<18)|0x09666, (0x05<<18)|0x2a986}, // channel 48
353 {(0x03<<18)|0x312c2, (0x04<<18)|0x09999, (0x05<<18)|0x2a986}, // channel 52
354 {(0x03<<18)|0x332c0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a99e}, // channel 56
355 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2a99e}, // channel 60
356 {(0x03<<18)|0x30ac3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a99e} // channel 64
357 };
358
359 u32 maxim_317_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
360 u32 maxim_317_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
361
362 /*****************************************************************************
363 ;;AL2230 MP (Mass Production Version)
364 ;;RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004
365 ;;Updated by Tiger Huang (June 1st, 2004)
366 ;;20-bit length and LSB first
367
368 ;;Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC;
369 ;;Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD;
370 ;;Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC;
371 ;;Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD;
372 ;;Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC;
373 ;;Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD;
374 ;;Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC;
375 ;;Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD;
376 ;;Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC;
377 ;;Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD;
378 ;;Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC;
379 ;;Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD;
380 ;;Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC;
381 ;;Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666;
382
383 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low
384 ;;0x02 0x481DC; RXDCOC BW 30Khz for RXHP low
385
386 0x03 0xCFFF0
387 0x04 0x23800
388 0x05 0xA3B72
389 0x06 0x6DA01
390 0x07 0xE1688
391 0x08 0x11600
392 0x09 0x99E02
393 0x0A 0x5DDB0
394 0x0B 0xD9900
395 0x0C 0x3FFBD
396 0x0D 0xB0000
397 0x0F 0xF00A0
398
399 ;RF Calibration for Airoha AL2230
400 ;Edit by Ben Chang (01/30/04)
401 ;Updated by Tiger Huang (03/03/04)
402 0x0f 0xf00a0 ; Initial Setting
403 0x0f 0xf00b0 ; Activate TX DCC
404 0x0f 0xf02a0 ; Activate Phase Calibration
405 0x0f 0xf00e0 ; Activate Filter RC Calibration
406 0x0f 0xf00a0 ; Restore Initial Setting
407 *****************************************************************************/
408
409 u32 al2230_rf_data[] =
410 {
411 (0x00<<20)|0x09EFC,
412 (0x01<<20)|0x8CCCC,
413 (0x02<<20)|0x40058,// 20060627 Anson 0x401D8,
414 (0x03<<20)|0xCFFF0,
415 (0x04<<20)|0x24100,// 20060627 Anson 0x23800,
416 (0x05<<20)|0xA3B2F,// 20060627 Anson 0xA3B72
417 (0x06<<20)|0x6DA01,
418 (0x07<<20)|0xE3628,// 20060627 Anson 0xE1688,
419 (0x08<<20)|0x11600,
420 (0x09<<20)|0x9DC02,// 20060627 Anosn 0x97602,//0x99E02, //0x9AE02
421 (0x0A<<20)|0x5ddb0, // 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth
422 (0x0B<<20)|0xD9900,
423 (0x0C<<20)|0x3FFBD,
424 (0x0D<<20)|0xB0000,
425 (0x0F<<20)|0xF01A0 // 20060627 Anson 0xF00A0
426 };
427
428 u32 al2230s_rf_data[] =
429 {
430 (0x00<<20)|0x09EFC,
431 (0x01<<20)|0x8CCCC,
432 (0x02<<20)|0x40058,// 20060419 0x401D8,
433 (0x03<<20)|0xCFFF0,
434 (0x04<<20)|0x24100,// 20060419 0x23800,
435 (0x05<<20)|0xA3B2F,// 20060419 0xA3B72,
436 (0x06<<20)|0x6DA01,
437 (0x07<<20)|0xE3628,// 20060419 0xE1688,
438 (0x08<<20)|0x11600,
439 (0x09<<20)|0x9DC02,// 20060419 0x97602,//0x99E02, //0x9AE02
440 (0x0A<<20)|0x5DDB0,// 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth
441 (0x0B<<20)|0xD9900,
442 (0x0C<<20)|0x3FFBD,
443 (0x0D<<20)|0xB0000,
444 (0x0F<<20)|0xF01A0 // 20060419 0xF00A0
445 };
446
447 u32 al2230_channel_data_24[][2] =
448 {
449 {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCC}, // channe1 01
450 {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCD}, // channe1 02
451 {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCC}, // channe1 03
452 {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCD}, // channe1 04
453 {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCC}, // channe1 05
454 {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCD}, // channe1 06
455 {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCC}, // channe1 07
456 {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCD}, // channe1 08
457 {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCC}, // channe1 09
458 {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCD}, // channe1 10
459 {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCC}, // channe1 11
460 {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCD}, // channe1 12
461 {(0x00<<20)|0x03EFC, (0x01<<20)|0x8CCCC}, // channe1 13
462 {(0x00<<20)|0x03E7C, (0x01<<20)|0x86666} // channe1 14
463 };
464
465 // Current setting. u32 airoha_power_data_24[] = {(0x09<<20)|0x90202, (0x09<<20)|0x96602, (0x09<<20)|0x97602};
466 #define AIROHA_TXVGA_LOW_INDEX 31 // Index for 0x90202
467 #define AIROHA_TXVGA_MIDDLE_INDEX 12 // Index for 0x96602
468 #define AIROHA_TXVGA_HIGH_INDEX 8 // Index for 0x97602 1.0.24.0 1.0.28.0
469 /*
470 u32 airoha_power_data_24[] =
471 {
472 0x9FE02, // Max - 0 dB
473 0x9BE02, // Max - 1 dB
474 0x9DE02, // Max - 2 dB
475 0x99E02, // Max - 3 dB
476 0x9EE02, // Max - 4 dB
477 0x9AE02, // Max - 5 dB
478 0x9CE02, // Max - 6 dB
479 0x98E02, // Max - 7 dB
480 0x97602, // Max - 8 dB
481 0x93602, // Max - 9 dB
482 0x95602, // Max - 10 dB
483 0x91602, // Max - 11 dB
484 0x96602, // Max - 12 dB
485 0x92602, // Max - 13 dB
486 0x94602, // Max - 14 dB
487 0x90602, // Max - 15 dB
488 0x97A02, // Max - 16 dB
489 0x93A02, // Max - 17 dB
490 0x95A02, // Max - 18 dB
491 0x91A02, // Max - 19 dB
492 0x96A02, // Max - 20 dB
493 0x92A02, // Max - 21 dB
494 0x94A02, // Max - 22 dB
495 0x90A02, // Max - 23 dB
496 0x97202, // Max - 24 dB
497 0x93202, // Max - 25 dB
498 0x95202, // Max - 26 dB
499 0x91202, // Max - 27 dB
500 0x96202, // Max - 28 dB
501 0x92202, // Max - 29 dB
502 0x94202, // Max - 30 dB
503 0x90202 // Max - 31 dB
504 };
505 */
506
507 // 20040927 1.1.69.1000 ybjiang
508 // from John
509 u32 al2230_txvga_data[][2] =
510 {
511 //value , index
512 {0x090202, 0},
513 {0x094202, 2},
514 {0x092202, 4},
515 {0x096202, 6},
516 {0x091202, 8},
517 {0x095202, 10},
518 {0x093202, 12},
519 {0x097202, 14},
520 {0x090A02, 16},
521 {0x094A02, 18},
522 {0x092A02, 20},
523 {0x096A02, 22},
524 {0x091A02, 24},
525 {0x095A02, 26},
526 {0x093A02, 28},
527 {0x097A02, 30},
528 {0x090602, 32},
529 {0x094602, 34},
530 {0x092602, 36},
531 {0x096602, 38},
532 {0x091602, 40},
533 {0x095602, 42},
534 {0x093602, 44},
535 {0x097602, 46},
536 {0x090E02, 48},
537 {0x098E02, 49},
538 {0x094E02, 50},
539 {0x09CE02, 51},
540 {0x092E02, 52},
541 {0x09AE02, 53},
542 {0x096E02, 54},
543 {0x09EE02, 55},
544 {0x091E02, 56},
545 {0x099E02, 57},
546 {0x095E02, 58},
547 {0x09DE02, 59},
548 {0x093E02, 60},
549 {0x09BE02, 61},
550 {0x097E02, 62},
551 {0x09FE02, 63}
552 };
553
554 //--------------------------------
555 // For Airoha AL7230, 2.4Ghz band
556 // Edit by Tiger, (March, 9, 2005)
557 // 24bit, MSB first
558
559 //channel independent registers:
560 u32 al7230_rf_data_24[] =
561 {
562 (0x00<<24)|0x003790,
563 (0x01<<24)|0x133331,
564 (0x02<<24)|0x841FF2,
565 (0x03<<24)|0x3FDFA3,
566 (0x04<<24)|0x7FD784,
567 (0x05<<24)|0x802B55,
568 (0x06<<24)|0x56AF36,
569 (0x07<<24)|0xCE0207,
570 (0x08<<24)|0x6EBC08,
571 (0x09<<24)|0x221BB9,
572 (0x0A<<24)|0xE0000A,
573 (0x0B<<24)|0x08071B,
574 (0x0C<<24)|0x000A3C,
575 (0x0D<<24)|0xFFFFFD,
576 (0x0E<<24)|0x00000E,
577 (0x0F<<24)|0x1ABA8F
578 };
579
580 u32 al7230_channel_data_24[][2] =
581 {
582 {(0x00<<24)|0x003790, (0x01<<24)|0x133331}, // channe1 01
583 {(0x00<<24)|0x003790, (0x01<<24)|0x1B3331}, // channe1 02
584 {(0x00<<24)|0x003790, (0x01<<24)|0x033331}, // channe1 03
585 {(0x00<<24)|0x003790, (0x01<<24)|0x0B3331}, // channe1 04
586 {(0x00<<24)|0x0037A0, (0x01<<24)|0x133331}, // channe1 05
587 {(0x00<<24)|0x0037A0, (0x01<<24)|0x1B3331}, // channe1 06
588 {(0x00<<24)|0x0037A0, (0x01<<24)|0x033331}, // channe1 07
589 {(0x00<<24)|0x0037A0, (0x01<<24)|0x0B3331}, // channe1 08
590 {(0x00<<24)|0x0037B0, (0x01<<24)|0x133331}, // channe1 09
591 {(0x00<<24)|0x0037B0, (0x01<<24)|0x1B3331}, // channe1 10
592 {(0x00<<24)|0x0037B0, (0x01<<24)|0x033331}, // channe1 11
593 {(0x00<<24)|0x0037B0, (0x01<<24)|0x0B3331}, // channe1 12
594 {(0x00<<24)|0x0037C0, (0x01<<24)|0x133331}, // channe1 13
595 {(0x00<<24)|0x0037C0, (0x01<<24)|0x066661} // channel 14
596 };
597
598 //channel independent registers:
599 u32 al7230_rf_data_50[] =
600 {
601 (0x00<<24)|0x0FF520,
602 (0x01<<24)|0x000001,
603 (0x02<<24)|0x451FE2,
604 (0x03<<24)|0x5FDFA3,
605 (0x04<<24)|0x6FD784,
606 (0x05<<24)|0x853F55,
607 (0x06<<24)|0x56AF36,
608 (0x07<<24)|0xCE0207,
609 (0x08<<24)|0x6EBC08,
610 (0x09<<24)|0x221BB9,
611 (0x0A<<24)|0xE0600A,
612 (0x0B<<24)|0x08044B,
613 (0x0C<<24)|0x00143C,
614 (0x0D<<24)|0xFFFFFD,
615 (0x0E<<24)|0x00000E,
616 (0x0F<<24)|0x12BACF //5Ghz default state
617 };
618
619 u32 al7230_channel_data_5[][4] =
620 {
621 //channel dependent registers: 0x00, 0x01 and 0x04
622 //11J ===========
623 {184, (0x00<<24)|0x0FF520, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 184
624 {188, (0x00<<24)|0x0FF520, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 188
625 {192, (0x00<<24)|0x0FF530, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 192
626 {196, (0x00<<24)|0x0FF530, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 196
627 {8, (0x00<<24)|0x0FF540, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 008
628 {12, (0x00<<24)|0x0FF540, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 012
629 {16, (0x00<<24)|0x0FF550, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 016
630 {34, (0x00<<24)|0x0FF560, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 034
631 {38, (0x00<<24)|0x0FF570, (0x01<<24)|0x100001, (0x04<<24)|0x77F784}, // channel 038
632 {42, (0x00<<24)|0x0FF570, (0x01<<24)|0x1AAAA1, (0x04<<24)|0x77F784}, // channel 042
633 {46, (0x00<<24)|0x0FF570, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 046
634 //11 A/H =========
635 {36, (0x00<<24)|0x0FF560, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 036
636 {40, (0x00<<24)|0x0FF570, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 040
637 {44, (0x00<<24)|0x0FF570, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 044
638 {48, (0x00<<24)|0x0FF570, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 048
639 {52, (0x00<<24)|0x0FF580, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 052
640 {56, (0x00<<24)|0x0FF580, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 056
641 {60, (0x00<<24)|0x0FF580, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 060
642 {64, (0x00<<24)|0x0FF590, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 064
643 {100, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 100
644 {104, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 104
645 {108, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 108
646 {112, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 112
647 {116, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 116
648 {120, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 120
649 {124, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 124
650 {128, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 128
651 {132, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 132
652 {136, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 136
653 {140, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 140
654 {149, (0x00<<24)|0x0FF600, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 149
655 {153, (0x00<<24)|0x0FF600, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784}, // channel 153
656 {157, (0x00<<24)|0x0FF600, (0x01<<24)|0x0D5551, (0x04<<24)|0x77F784}, // channel 157
657 {161, (0x00<<24)|0x0FF610, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 161
658 {165, (0x00<<24)|0x0FF610, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784} // channel 165
659 };
660
661 //; RF Calibration <=== Register 0x0F
662 //0x0F 0x1ABA8F; start from 2.4Ghz default state
663 //0x0F 0x9ABA8F; TXDC compensation
664 //0x0F 0x3ABA8F; RXFIL adjustment
665 //0x0F 0x1ABA8F; restore 2.4Ghz default state
666
667 //;TXVGA Mapping Table <=== Register 0x0B
668 u32 al7230_txvga_data[][2] =
669 {
670 {0x08040B, 0}, //TXVGA=0;
671 {0x08041B, 1}, //TXVGA=1;
672 {0x08042B, 2}, //TXVGA=2;
673 {0x08043B, 3}, //TXVGA=3;
674 {0x08044B, 4}, //TXVGA=4;
675 {0x08045B, 5}, //TXVGA=5;
676 {0x08046B, 6}, //TXVGA=6;
677 {0x08047B, 7}, //TXVGA=7;
678 {0x08048B, 8}, //TXVGA=8;
679 {0x08049B, 9}, //TXVGA=9;
680 {0x0804AB, 10}, //TXVGA=10;
681 {0x0804BB, 11}, //TXVGA=11;
682 {0x0804CB, 12}, //TXVGA=12;
683 {0x0804DB, 13}, //TXVGA=13;
684 {0x0804EB, 14}, //TXVGA=14;
685 {0x0804FB, 15}, //TXVGA=15;
686 {0x08050B, 16}, //TXVGA=16;
687 {0x08051B, 17}, //TXVGA=17;
688 {0x08052B, 18}, //TXVGA=18;
689 {0x08053B, 19}, //TXVGA=19;
690 {0x08054B, 20}, //TXVGA=20;
691 {0x08055B, 21}, //TXVGA=21;
692 {0x08056B, 22}, //TXVGA=22;
693 {0x08057B, 23}, //TXVGA=23;
694 {0x08058B, 24}, //TXVGA=24;
695 {0x08059B, 25}, //TXVGA=25;
696 {0x0805AB, 26}, //TXVGA=26;
697 {0x0805BB, 27}, //TXVGA=27;
698 {0x0805CB, 28}, //TXVGA=28;
699 {0x0805DB, 29}, //TXVGA=29;
700 {0x0805EB, 30}, //TXVGA=30;
701 {0x0805FB, 31}, //TXVGA=31;
702 {0x08060B, 32}, //TXVGA=32;
703 {0x08061B, 33}, //TXVGA=33;
704 {0x08062B, 34}, //TXVGA=34;
705 {0x08063B, 35}, //TXVGA=35;
706 {0x08064B, 36}, //TXVGA=36;
707 {0x08065B, 37}, //TXVGA=37;
708 {0x08066B, 38}, //TXVGA=38;
709 {0x08067B, 39}, //TXVGA=39;
710 {0x08068B, 40}, //TXVGA=40;
711 {0x08069B, 41}, //TXVGA=41;
712 {0x0806AB, 42}, //TXVGA=42;
713 {0x0806BB, 43}, //TXVGA=43;
714 {0x0806CB, 44}, //TXVGA=44;
715 {0x0806DB, 45}, //TXVGA=45;
716 {0x0806EB, 46}, //TXVGA=46;
717 {0x0806FB, 47}, //TXVGA=47;
718 {0x08070B, 48}, //TXVGA=48;
719 {0x08071B, 49}, //TXVGA=49;
720 {0x08072B, 50}, //TXVGA=50;
721 {0x08073B, 51}, //TXVGA=51;
722 {0x08074B, 52}, //TXVGA=52;
723 {0x08075B, 53}, //TXVGA=53;
724 {0x08076B, 54}, //TXVGA=54;
725 {0x08077B, 55}, //TXVGA=55;
726 {0x08078B, 56}, //TXVGA=56;
727 {0x08079B, 57}, //TXVGA=57;
728 {0x0807AB, 58}, //TXVGA=58;
729 {0x0807BB, 59}, //TXVGA=59;
730 {0x0807CB, 60}, //TXVGA=60;
731 {0x0807DB, 61}, //TXVGA=61;
732 {0x0807EB, 62}, //TXVGA=62;
733 {0x0807FB, 63}, //TXVGA=63;
734 };
735 //--------------------------------
736
737
738 //; W89RF242 RFIC SPI programming initial data
739 //; Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b
740 //; Update Date: Ocotber 3, 2005 by PP10 Hsiang-Te Ho
741 //;
742 //; Version 1.3b revision items: (Oct. 1, 2005 by HTHo) for FA5976A
743 u32 w89rf242_rf_data[] =
744 {
745 (0x00<<24)|0xF86100, // 20060721 0xF86100, //; 3E184; MODA (0x00) -- Normal mode ; calibration off
746 (0x01<<24)|0xEFFFC2, //; 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on
747 (0x02<<24)|0x102504, //; 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA
748 (0x03<<24)|0x026286, //; 0098A; FCHN (0x03) -- default CH7, 2442MHz
749 (0x04<<24)|0x000208, // 20060612.1.a 0x0002C8, // 20050818 // 20050816 0x000388
750 //; 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C
751 (0x05<<24)|0x24C60A, // 20060612.1.a 0x24C58A, // 941003 0x24C48A, // 20050818.2 0x24848A, // 20050818 // 20050816 0x24C48A
752 //; 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D
753 (0x06<<24)|0x3432CC, // 941003 0x26C34C, // 20050818 0x06B40C
754 //; 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input
755 (0x07<<24)|0x0C68CE, // 20050818.2 0x0C66CE, // 20050818 // 20050816 0x0C68CE
756 //; 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100
757 (0x08<<24)|0x100010, //; 04000; TCAL (0x08) -- //for LO
758 (0x09<<24)|0x004012, // 20060612.1.a 0x6E4012, // 0x004012,
759 //; 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C)
760 (0x0A<<24)|0x704014, //; 1C100; RCALB (0x0A)
761 (0x0B<<24)|0x18BDD6, // 941003 0x1805D6, // 20050818.2 0x1801D6, // 20050818 // 20050816 0x1805D6
762 //; 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B (2005/09/29)
763 (0x0C<<24)|0x575558, // 20050818.2 0x555558, // 20050818 // 20050816 0x575558
764 //; 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner
765 (0x0D<<24)|0x55545A, // 20060612.1.a 0x55555A,
766 //; 15555 ; IBSB (0x0D)
767 (0x0E<<24)|0x5557DC, // 20060612.1.a 0x55555C, // 941003 0x5557DC,
768 //; 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F (2005/11/25)
769 (0x10<<24)|0x000C20, // 941003 0x000020, // 20050818
770 //; 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB
771 (0x11<<24)|0x0C0022, // 941003 0x030022 // 20050818.2 0x030022 // 20050818 // 20050816 0x0C0022
772 //; 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C)
773 (0x12<<24)|0x000024 // 20060612.1.a 0x001824 // 941003 add
774 //; TMODC (0x12) -- Turn OFF Tempearure sensor
775 };
776
777 u32 w89rf242_channel_data_24[][2] =
778 {
779 {(0x03<<24)|0x025B06, (0x04<<24)|0x080408}, // channe1 01
780 {(0x03<<24)|0x025C46, (0x04<<24)|0x080408}, // channe1 02
781 {(0x03<<24)|0x025D86, (0x04<<24)|0x080408}, // channe1 03
782 {(0x03<<24)|0x025EC6, (0x04<<24)|0x080408}, // channe1 04
783 {(0x03<<24)|0x026006, (0x04<<24)|0x080408}, // channe1 05
784 {(0x03<<24)|0x026146, (0x04<<24)|0x080408}, // channe1 06
785 {(0x03<<24)|0x026286, (0x04<<24)|0x080408}, // channe1 07
786 {(0x03<<24)|0x0263C6, (0x04<<24)|0x080408}, // channe1 08
787 {(0x03<<24)|0x026506, (0x04<<24)|0x080408}, // channe1 09
788 {(0x03<<24)|0x026646, (0x04<<24)|0x080408}, // channe1 10
789 {(0x03<<24)|0x026786, (0x04<<24)|0x080408}, // channe1 11
790 {(0x03<<24)|0x0268C6, (0x04<<24)|0x080408}, // channe1 12
791 {(0x03<<24)|0x026A06, (0x04<<24)|0x080408}, // channe1 13
792 {(0x03<<24)|0x026D06, (0x04<<24)|0x080408} // channe1 14
793 };
794
795 u32 w89rf242_power_data_24[] = {(0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A};
796
797 // 20060315.6 Enlarge for new scale
798 // 20060316.6 20060619.2.a add mapping array
799 u32 w89rf242_txvga_old_mapping[][2] =
800 {
801 {0, 0} , // New <-> Old
802 {1, 1} ,
803 {2, 2} ,
804 {3, 3} ,
805 {4, 4} ,
806 {6, 5} ,
807 {8, 6 },
808 {10, 7 },
809 {12, 8 },
810 {14, 9 },
811 {16, 10},
812 {18, 11},
813 {20, 12},
814 {22, 13},
815 {24, 14},
816 {26, 15},
817 {28, 16},
818 {30, 17},
819 {32, 18},
820 {34, 19},
821
822
823 };
824
825 // 20060619.3 modify from Bruce's mail
826 u32 w89rf242_txvga_data[][5] =
827 {
828 //low gain mode
829 { (0x05<<24)|0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131 },// ; min gain
830 { (0x05<<24)|0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131 },
831 { (0x05<<24)|0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131 },// (default) +14dBm (ANT)
832 { (0x05<<24)|0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131 },
833
834 //TXVGA=0x10
835 { (0x05<<24)|0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838 },
836 { (0x05<<24)|0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B },
837
838 //TXVGA=0x11
839 { (0x05<<24)|0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333 },
840 { (0x05<<24)|0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737 },
841
842 //TXVGA=0x12
843 { (0x05<<24)|0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030 },
844 { (0x05<<24)|0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434 },
845
846 //TXVGA=0x13
847 { (0x05<<24)|0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030 },
848 { (0x05<<24)|0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232 },
849
850 //TXVGA=0x14
851 { (0x05<<24)|0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131 },
852 { (0x05<<24)|0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434 },
853
854 //TXVGA=0x15
855 { (0x05<<24)|0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131 },
856 { (0x05<<24)|0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434 },
857
858 //TXVGA=0x16
859 { (0x05<<24)|0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131 },
860 { (0x05<<24)|0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535 },
861
862 //TXVGA=0x17
863 { (0x05<<24)|0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F },
864 { (0x05<<24)|0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131 },
865
866 //TXVGA=0x18
867 { (0x05<<24)|0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E },
868 { (0x05<<24)|0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030 },
869
870 //TXVGA=0x19
871 { (0x05<<24)|0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D },
872 { (0x05<<24)|0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030 },
873
874 //TXVGA=0x1A
875 { (0x05<<24)|0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E },
876 { (0x05<<24)|0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131 },
877
878 //TXVGA=0x1B
879 { (0x05<<24)|0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030 },
880 { (0x05<<24)|0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434 },
881
882 //TXVGA=0x1C
883 { (0x05<<24)|0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131 },
884 { (0x05<<24)|0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636 },
885
886 //TXVGA=0x1D
887 { (0x05<<24)|0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737 },
888 { (0x05<<24)|0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B },
889
890 //TXVGA=0x1E
891 { (0x05<<24)|0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B },
892 { (0x05<<24)|0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141 },
893
894 //TXVGA=0x1F
895 { (0x05<<24)|0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242 }
896 };
897
898 ///////////////////////////////////////////////////////////////////////////////////////////////////
899 ///////////////////////////////////////////////////////////////////////////////////////////////////
900 ///////////////////////////////////////////////////////////////////////////////////////////////////
901
902
903
904 //=============================================================================================================
905 // Uxx_ReadEthernetAddress --
906 //
907 // Routine Description:
908 // Reads in the Ethernet address from the IC.
909 //
910 // Arguments:
911 // pHwData - The pHwData structure
912 //
913 // Return Value:
914 //
915 // The address is stored in EthernetIDAddr.
916 //=============================================================================================================
917 void
918 Uxx_ReadEthernetAddress( phw_data_t pHwData )
919 {
920 u32 ltmp;
921
922 // Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change.
923 // Only unplug and plug again can make hardware read EEPROM again. 20060727
924 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d)
925 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
926 *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian
927 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d)
928 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
929 *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
930 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d)
931 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
932 *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
933 *(u16 *)(pHwData->PermanentMacAddress + 6) = 0;
934 Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress) ); //20060926 anson's endian
935 Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian
936 }
937
938
939 //===============================================================================================================
940 // CardGetMulticastBit --
941 // Description:
942 // For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to.
943 // Calls CardComputeCrc() to determine the CRC value.
944 // Arguments:
945 // Address - the address
946 // Byte - the byte that it hashes to
947 // Value - will have a 1 in the relevant bit
948 // Return Value:
949 // None.
950 //==============================================================================================================
951 void CardGetMulticastBit( u8 Address[ETH_LENGTH_OF_ADDRESS],
952 u8 *Byte, u8 *Value )
953 {
954 u32 Crc;
955 u32 BitNumber;
956
957 // First compute the CRC.
958 Crc = CardComputeCrc(Address, ETH_LENGTH_OF_ADDRESS);
959
960 // The computed CRC is bit0~31 from left to right
961 //At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128
962 BitNumber = (u32) ((Crc >> 26) & 0x3f);
963
964 *Byte = (u8) (BitNumber >> 3);// 900514 original (BitNumber / 8)
965 *Value = (u8) ((u8)1 << (BitNumber % 8));
966 }
967
968 void Uxx_power_on_procedure( phw_data_t pHwData )
969 {
970 u32 ltmp, loop;
971
972 if( pHwData->phy_type <= RF_MAXIM_V1 )
973 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xffffff38 );
974 else
975 {
976 Wb35Reg_WriteSync( pHwData, 0x03f4, 0xFF5807FF );// 20060721 For NEW IC 0xFF5807FF
977
978 // 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail
979 Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
980 msleep(10); // Modify 20051221.1.b
981 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and
982 msleep(10); // Modify 20051221.1.b
983
984 ltmp = 0x4968;
985 if( (pHwData->phy_type == RF_WB_242) ||
986 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
987 ltmp = 0x4468;
988 Wb35Reg_WriteSync( pHwData, 0x03d0, ltmp );
989
990 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
991
992 msleep(20); // Modify 20051221.1.b
993 Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp );
994 loop = 500; // Wait for 5 second 20061101
995 while( !(ltmp & 0x20) && loop-- )
996 {
997 msleep(10); // Modify 20051221.1.b
998 if( !Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp ) )
999 break;
1000 }
1001
1002 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
1003 }
1004
1005 Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
1006 msleep(10); // Add this 20051221.1.b
1007
1008 // Set burst write delay
1009 Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff );
1010 }
1011
1012 void Set_ChanIndep_RfData_al7230_24( phw_data_t pHwData, u32 *pltmp ,char number)
1013 {
1014 u8 i;
1015
1016 for( i=0; i<number; i++ )
1017 {
1018 pHwData->phy_para[i] = al7230_rf_data_24[i];
1019 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i]&0xffffff);
1020 }
1021 }
1022
1023 void Set_ChanIndep_RfData_al7230_50( phw_data_t pHwData, u32 *pltmp, char number)
1024 {
1025 u8 i;
1026
1027 for( i=0; i<number; i++ )
1028 {
1029 pHwData->phy_para[i] = al7230_rf_data_50[i];
1030 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i]&0xffffff);
1031 }
1032 }
1033
1034
1035 //=============================================================================================================
1036 // RFSynthesizer_initial --
1037 //=============================================================================================================
1038 void
1039 RFSynthesizer_initial(phw_data_t pHwData)
1040 {
1041 u32 altmp[32];
1042 u32 * pltmp = altmp;
1043 u32 ltmp;
1044 u8 number=0x00; // The number of register vale
1045 u8 i;
1046
1047 //
1048 // bit[31] SPI Enable.
1049 // 1=perform synthesizer program operation. This bit will
1050 // cleared automatically after the operation is completed.
1051 // bit[30] SPI R/W Control
1052 // 0=write, 1=read
1053 // bit[29:24] SPI Data Format Length
1054 // bit[17:4 ] RF Data bits.
1055 // bit[3 :0 ] RF address.
1056 switch( pHwData->phy_type )
1057 {
1058 case RF_MAXIM_2825:
1059 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1060 number = sizeof(max2825_rf_data)/sizeof(max2825_rf_data[0]);
1061 for( i=0; i<number; i++ )
1062 {
1063 pHwData->phy_para[i] = max2825_rf_data[i];// Backup Rf parameter
1064 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_rf_data[i], 18);
1065 }
1066 break;
1067
1068 case RF_MAXIM_2827:
1069 number = sizeof(max2827_rf_data)/sizeof(max2827_rf_data[0]);
1070 for( i=0; i<number; i++ )
1071 {
1072 pHwData->phy_para[i] = max2827_rf_data[i];
1073 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_rf_data[i], 18);
1074 }
1075 break;
1076
1077 case RF_MAXIM_2828:
1078 number = sizeof(max2828_rf_data)/sizeof(max2828_rf_data[0]);
1079 for( i=0; i<number; i++ )
1080 {
1081 pHwData->phy_para[i] = max2828_rf_data[i];
1082 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_rf_data[i], 18);
1083 }
1084 break;
1085
1086 case RF_MAXIM_2829:
1087 number = sizeof(max2829_rf_data)/sizeof(max2829_rf_data[0]);
1088 for( i=0; i<number; i++ )
1089 {
1090 pHwData->phy_para[i] = max2829_rf_data[i];
1091 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_rf_data[i], 18);
1092 }
1093 break;
1094
1095 case RF_AIROHA_2230:
1096 number = sizeof(al2230_rf_data)/sizeof(al2230_rf_data[0]);
1097 for( i=0; i<number; i++ )
1098 {
1099 pHwData->phy_para[i] = al2230_rf_data[i];
1100 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[i], 20);
1101 }
1102 break;
1103
1104 case RF_AIROHA_2230S:
1105 number = sizeof(al2230s_rf_data)/sizeof(al2230s_rf_data[0]);
1106 for( i=0; i<number; i++ )
1107 {
1108 pHwData->phy_para[i] = al2230s_rf_data[i];
1109 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230s_rf_data[i], 20);
1110 }
1111 break;
1112
1113 case RF_AIROHA_7230:
1114
1115 //Start to fill RF parameters, PLL_ON should be pulled low.
1116 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
1117 #ifdef _PE_STATE_DUMP_
1118 WBDEBUG(("* PLL_ON low\n"));
1119 #endif
1120
1121 number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]);
1122 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
1123 break;
1124
1125 case RF_WB_242:
1126 case RF_WB_242_1: // 20060619.5 Add
1127 number = sizeof(w89rf242_rf_data)/sizeof(w89rf242_rf_data[0]);
1128 for( i=0; i<number; i++ )
1129 {
1130 ltmp = w89rf242_rf_data[i];
1131 if( i == 4 ) // Update the VCO trim from EEPROM
1132 {
1133 ltmp &= ~0xff0; // Mask bit4 ~bit11
1134 ltmp |= pHwData->VCO_trim<<4;
1135 }
1136
1137 pHwData->phy_para[i] = ltmp;
1138 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( ltmp, 24);
1139 }
1140 break;
1141 }
1142
1143 pHwData->phy_number = number;
1144
1145 // The 16 is the maximum capability of hardware. Here use 12
1146 if( number > 12 ) {
1147 //Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 12, NO_INCREMENT );
1148 for( i=0; i<12; i++ ) // For Al2230
1149 Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
1150
1151 pltmp += 12;
1152 number -= 12;
1153 }
1154
1155 // Write to register. number must less and equal than 16
1156 for( i=0; i<number; i++ )
1157 Wb35Reg_WriteSync( pHwData, 0x864, pltmp[i] );
1158
1159 // 20060630.1 Calibration only 1 time
1160 if( pHwData->CalOneTime )
1161 return;
1162 pHwData->CalOneTime = 1;
1163
1164 switch( pHwData->phy_type )
1165 {
1166 case RF_AIROHA_2230:
1167
1168 // 20060511.1 --- Modifying the follow step for Rx issue-----------------
1169 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20);
1170 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1171 msleep(10);
1172 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20);
1173 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1174 msleep(10);
1175
1176 case RF_AIROHA_2230S: // 20060420 Add this
1177
1178 // 20060511.1 --- Modifying the follow step for Rx issue-----------------
1179 Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
1180 msleep(10); // Modify 20051221.1.b
1181
1182 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
1183 msleep(10); // Modify 20051221.1.b
1184
1185 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
1186 Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
1187 msleep(10); // Add this 20051221.1.b
1188 //------------------------------------------------------------------------
1189
1190 // The follow code doesn't use the burst-write mode
1191 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Raise Initial Setting
1192 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
1193 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1194
1195 ltmp = pHwData->reg.BB5C & 0xfffff000;
1196 Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
1197 pHwData->reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify
1198 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1199 msleep(5);
1200
1201 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal.
1202 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20);
1203 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1204 msleep(5);
1205
1206 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC
1207 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20);
1208 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1209 msleep(5);
1210
1211 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting
1212 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
1213 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1214
1215 // //Force TXI(Q)P(N) to normal control
1216 Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->reg.BB5C );
1217 pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);
1218 Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->reg.BB50);
1219 break;
1220
1221 case RF_AIROHA_7230:
1222
1223 //RF parameters have filled completely, PLL_ON should be
1224 //pulled high
1225 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1226 #ifdef _PE_STATE_DUMP_
1227 WBDEBUG(("* PLL_ON high\n"));
1228 #endif
1229
1230 //2.4GHz
1231 //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1232 //Wb35Reg_WriteSync pHwData, 0x0864, ltmp );
1233 //msleep(1); // Sleep 1 ms
1234 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1235 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1236 msleep(5);
1237 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1238 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1239 msleep(5);
1240 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1241 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1242 msleep(5);
1243
1244 //5GHz
1245 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
1246 #ifdef _PE_STATE_DUMP_
1247 WBDEBUG(("* PLL_ON low\n"));
1248 #endif
1249
1250 number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]);
1251 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1252 // Write to register. number must less and equal than 16
1253 for( i=0; i<number; i++ )
1254 Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
1255 msleep(5);
1256
1257 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1258 #ifdef _PE_STATE_DUMP_
1259 WBDEBUG(("* PLL_ON high\n"));
1260 #endif
1261
1262 //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1263 //Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1264 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1265 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1266 msleep(5);
1267 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1268 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1269 msleep(5);
1270 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1271 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1272 msleep(5);
1273
1274 //Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1275 //WBDEBUG(("* PLL_ON high\n"));
1276 break;
1277
1278 case RF_WB_242:
1279 case RF_WB_242_1: // 20060619.5 Add
1280
1281 //
1282 // ; Version 1.3B revision items: for FA5976A , October 3, 2005 by HTHo
1283 //
1284 ltmp = pHwData->reg.BB5C & 0xfffff000;
1285 Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
1286 Wb35Reg_WriteSync( pHwData, 0x1058, 0 );
1287 pHwData->reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630
1288 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1289
1290 //----- Calibration (1). VCO frequency calibration
1291 //Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10)
1292 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24);
1293 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1294 msleep(5); // Sleep 5ms
1295 //Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time
1296 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24);
1297 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1298 msleep(2); // Sleep 2ms
1299
1300 //----- Calibration (2). TX baseband Gm-C filter auto-tuning
1301 //Calibration (2a). turn off ENCAL signal
1302 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
1303 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1304 //Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default)
1305 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24);
1306 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1307 //Calibration (2b). send TX reset signal (HTHo corrected May 10, 2005)
1308 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00201E, 24);
1309 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1310 //Calibration (2c). turn-on TX Gm-C filter auto-tuning
1311 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24);
1312 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1313 udelay(150); // Sleep 150 us
1314 //turn off ENCAL signal
1315 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
1316 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1317
1318 //----- Calibration (3). RX baseband Gm-C filter auto-tuning
1319 //Calibration (3a). turn off ENCAL signal
1320 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1321 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1322 //Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default; July 26, 2005)
1323 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24);
1324 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1325 //Calibration (3b). send RX reset signal (HTHo corrected May 10, 2005)
1326 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00401E, 24);
1327 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1328 //Calibration (3c). turn-on RX Gm-C filter auto-tuning
1329 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24);
1330 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1331 udelay(150); // Sleep 150 us
1332 //Calibration (3e). turn off ENCAL signal
1333 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1334 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1335
1336 //----- Calibration (4). TX LO leakage calibration
1337 //Calibration (4a). TX LO leakage calibration
1338 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24);
1339 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1340 udelay(150); // Sleep 150 us
1341
1342 //----- Calibration (5). RX DC offset calibration
1343 //Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode
1344 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1345 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1346 //Calibration (5b). turn off AGC servo-loop & RSSI
1347 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEBFFC2, 24);
1348 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1349
1350 //; for LNA=11 --------
1351 //Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111
1352 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x343FCC, 24);
1353 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1354 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1355 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1356 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1357 msleep(2); // Sleep 2ms
1358 //Calibration (5f). turn off ENCAL signal
1359 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1360 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1361
1362 //; for LNA=10 --------
1363 //Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111
1364 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x342FCC, 24);
1365 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1366 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1367 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1368 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1369 msleep(2); // Sleep 2ms
1370 //Calibration (5f). turn off ENCAL signal
1371 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1372 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1373
1374 //; for LNA=01 --------
1375 //Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111
1376 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x341FCC, 24);
1377 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1378 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1379 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1380 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1381 msleep(2); // Sleep 2ms
1382 //Calibration (5f). turn off ENCAL signal
1383 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1384 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1385
1386 //; for LNA=00 --------
1387 //Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111
1388 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x340FCC, 24);
1389 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1390 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1391 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1392 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1393 msleep(2); // Sleep 2ms
1394 //Calibration (5f). turn off ENCAL signal
1395 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1396 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1397 //Calibration (5g). turn on AGC servo-loop
1398 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEFFFC2, 24);
1399 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1400
1401 //; ----- Calibration (7). Switch RF chip to normal mode
1402 //0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode
1403 // msleep(10); // @@ 20060721
1404 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24);
1405 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1406 msleep(5); // Sleep 5 ms
1407
1408 // //write back
1409 // Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
1410 // pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix
1411 // Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1412 // msleep(1); // Sleep 1 ms
1413 break;
1414 }
1415 }
1416
1417 void BBProcessor_AL7230_2400( phw_data_t pHwData)
1418 {
1419 struct wb35_reg *reg = &pHwData->reg;
1420 u32 pltmp[12];
1421
1422 pltmp[0] = 0x16A8337A; // 0x16a5215f; // 0x1000 AGC_Ctrl1
1423 pltmp[1] = 0x9AFF9AA6; // 0x9aff9ca6; // 0x1004 AGC_Ctrl2
1424 pltmp[2] = 0x55D00A04; // 0x55d00a04; // 0x1008 AGC_Ctrl3
1425 pltmp[3] = 0xFFF72031; // 0xFfFf2138; // 0x100c AGC_Ctrl4
1426 reg->BB0C = 0xFFF72031;
1427 pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
1428 pltmp[5] = 0x00CAA333; // 0x00eaa333; // 0x1014 AGC_Ctrl6
1429 pltmp[6] = 0xF2211111; // 0x11111111; // 0x1018 AGC_Ctrl7
1430 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1431 pltmp[8] = 0x06443440; // 0x1020 AGC_Ctrl9
1432 pltmp[9] = 0xA8002A79; // 0xa9002A79; // 0x1024 AGC_Ctrl10
1433 pltmp[10] = 0x40000528; // 20050927 0x40000228
1434 pltmp[11] = 0x232D7F30; // 0x23457f30;// 0x102c A_ACQ_Ctrl
1435 reg->BB2C = 0x232D7F30;
1436 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1437
1438 pltmp[0] = 0x00002c54; // 0x1030 B_ACQ_Ctrl
1439 reg->BB30 = 0x00002c54;
1440 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1441 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1442 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1443 reg->BB3C = 0x00000000;
1444 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1445 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1446 pltmp[6] = 0x00332C1B; // 0x00453B24; // 0x1048 11b TX RC filter
1447 pltmp[7] = 0x0A00FEFF; // 0x0E00FEFF; // 0x104c 11b TX RC filter
1448 pltmp[8] = 0x2B106208; // 0x1050 MODE_Ctrl
1449 reg->BB50 = 0x2B106208;
1450 pltmp[9] = 0; // 0x1054
1451 reg->BB54 = 0x00000000;
1452 pltmp[10] = 0x52524242; // 0x64645252; // 0x1058 IQ_Alpha
1453 reg->BB58 = 0x52524242;
1454 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1455 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1456
1457 }
1458
1459 void BBProcessor_AL7230_5000( phw_data_t pHwData)
1460 {
1461 struct wb35_reg *reg = &pHwData->reg;
1462 u32 pltmp[12];
1463
1464 pltmp[0] = 0x16AA6678; // 0x1000 AGC_Ctrl1
1465 pltmp[1] = 0x9AFFA0B2; // 0x1004 AGC_Ctrl2
1466 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1467 pltmp[3] = 0xEFFF233E; // 0x100c AGC_Ctrl4
1468 reg->BB0C = 0xEFFF233E;
1469 pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
1470 pltmp[5] = 0x00CAA333; // 0x1014 AGC_Ctrl6
1471 pltmp[6] = 0xF2432111; // 0x1018 AGC_Ctrl7
1472 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1473 pltmp[8] = 0x05C43440; // 0x1020 AGC_Ctrl9
1474 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1475 pltmp[10] = 0x40000528; // 20050927 0x40000228
1476 pltmp[11] = 0x232FDF30;// 0x102c A_ACQ_Ctrl
1477 reg->BB2C = 0x232FDF30;
1478 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1479
1480 pltmp[0] = 0x80002C7C; // 0x1030 B_ACQ_Ctrl
1481 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1482 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1483 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1484 reg->BB3C = 0x00000000;
1485 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1486 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1487 pltmp[6] = 0x00332C1B; // 0x1048 11b TX RC filter
1488 pltmp[7] = 0x0A00FEFF; // 0x104c 11b TX RC filter
1489 pltmp[8] = 0x2B107208; // 0x1050 MODE_Ctrl
1490 reg->BB50 = 0x2B107208;
1491 pltmp[9] = 0; // 0x1054
1492 reg->BB54 = 0x00000000;
1493 pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
1494 reg->BB58 = 0x52524242;
1495 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1496 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1497
1498 }
1499
1500 //=============================================================================================================
1501 // BBProcessorPowerupInit --
1502 //
1503 // Description:
1504 // Initialize the Baseband processor.
1505 //
1506 // Arguments:
1507 // pHwData - Handle of the USB Device.
1508 //
1509 // Return values:
1510 // None.
1511 //=============================================================================================================
1512 void
1513 BBProcessor_initial( phw_data_t pHwData )
1514 {
1515 struct wb35_reg *reg = &pHwData->reg;
1516 u32 i, pltmp[12];
1517
1518 switch( pHwData->phy_type )
1519 {
1520 case RF_MAXIM_V1: // Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1521
1522 pltmp[0] = 0x16F47E77; // 0x1000 AGC_Ctrl1
1523 pltmp[1] = 0x9AFFAEA4; // 0x1004 AGC_Ctrl2
1524 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1525 pltmp[3] = 0xEFFF1A34; // 0x100c AGC_Ctrl4
1526 reg->BB0C = 0xEFFF1A34;
1527 pltmp[4] = 0x0FABE0B7; // 0x1010 AGC_Ctrl5
1528 pltmp[5] = 0x00CAA332; // 0x1014 AGC_Ctrl6
1529 pltmp[6] = 0xF6632111; // 0x1018 AGC_Ctrl7
1530 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1531 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1532 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1533 pltmp[10] = (pHwData->phy_type==3) ? 0x40000a28 : 0x40000228; // 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0)
1534 pltmp[11] = 0x232FDF30; // 0x102c A_ACQ_Ctrl
1535 reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1536 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1537
1538 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1539 reg->BB30 = 0x00002C54;
1540 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1541 pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
1542 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1543 reg->BB3C = 0x00000000;
1544 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1545 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1546 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1547 pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
1548 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1549 reg->BB50 = 0x27106208;
1550 pltmp[9] = 0; // 0x1054
1551 reg->BB54 = 0x00000000;
1552 pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
1553 reg->BB58 = 0x64646464;
1554 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1555 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1556
1557 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1558 break;
1559
1560 //------------------------------------------------------------------
1561 //[20040722 WK]
1562 //Only for baseband version 2
1563 // case RF_MAXIM_317:
1564 case RF_MAXIM_2825:
1565 case RF_MAXIM_2827:
1566 case RF_MAXIM_2828:
1567
1568 pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1
1569 pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
1570 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1571 pltmp[3] = 0xefff1a34; // 0x100c AGC_Ctrl4
1572 reg->BB0C = 0xefff1a34;
1573 pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
1574 pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
1575 pltmp[6] = 0xf6632111; // 0x1018 AGC_Ctrl7
1576 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1577 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1578 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1579 pltmp[10] = 0x40000528; // 0x40000128; Modify for 33's 1.0.95
1580 pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
1581 reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
1582 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1583
1584 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1585 reg->BB30 = 0x00002C54;
1586 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1587 pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
1588 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1589 reg->BB3C = 0x00000000;
1590 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1591 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1592 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1593 pltmp[7] = 0x0D00FDFF; // 0x104c 11b TX RC filter
1594 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1595 reg->BB50 = 0x27106208;
1596 pltmp[9] = 0; // 0x1054
1597 reg->BB54 = 0x00000000;
1598 pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
1599 reg->BB58 = 0x64646464;
1600 pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
1601 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1602
1603 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1604 break;
1605
1606 case RF_MAXIM_2829:
1607
1608 pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1
1609 pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
1610 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1611 pltmp[3] = 0xf4ff1632; // 0xefff1a34; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95
1612 reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95
1613 pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
1614 pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
1615 pltmp[6] = 0xf8632112; // 0xf6632111; // 0x1018 AGC_Ctrl7 Modify for 33's 1.0.95
1616 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1617 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1618 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1619 pltmp[10] = 0x40000528; // 0x40000128; modify for 33's 1.0.95
1620 pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
1621 reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
1622 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1623
1624 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1625 reg->BB30 = 0x00002C54;
1626 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1627 pltmp[2] = 0x5b2c8769; // 0x5B6C8769; // 0x1038 B_TXRX_Ctrl Modify for 33's 1.0.95
1628 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1629 reg->BB3C = 0x00000000;
1630 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1631 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1632 pltmp[6] = 0x002c2617; // 0x00453B24; // 0x1048 11b TX RC filter Modify for 33's 1.0.95
1633 pltmp[7] = 0x0800feff; // 0x0D00FDFF; // 0x104c 11b TX RC filter Modify for 33's 1.0.95
1634 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1635 reg->BB50 = 0x27106208;
1636 pltmp[9] = 0; // 0x1054
1637 reg->BB54 = 0x00000000;
1638 pltmp[10] = 0x64644a4a; // 0x64646464; // 0x1058 IQ_Alpha Modify for 33's 1.0.95
1639 reg->BB58 = 0x64646464;
1640 pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
1641 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1642
1643 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1644 break;
1645
1646 case RF_AIROHA_2230:
1647
1648 pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77
1649 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1650 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1651 pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
1652 reg->BB0C = 0xFFFd203c;
1653 pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
1654 pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
1655 pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
1656 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1657 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1658 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1659 pltmp[10] = 0X40000528; //0x40000228
1660 pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
1661 reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1662 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1663
1664 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1665 reg->BB30 = 0x00002C54;
1666 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1667 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
1668 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1669 reg->BB3C = 0x00000000;
1670 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1671 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1672 pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
1673 reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
1674 pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
1675 reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2
1676 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1677 reg->BB50 = 0x27106200;
1678 pltmp[9] = 0; // 0x1054
1679 reg->BB54 = 0x00000000;
1680 pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
1681 reg->BB58 = 0x52524242;
1682 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1683 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1684
1685 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1686 break;
1687
1688 case RF_AIROHA_2230S: // 20060420 Add this
1689
1690 pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77
1691 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1692 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1693 pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
1694 reg->BB0C = 0xFFFd203c;
1695 pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
1696 pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
1697 pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
1698 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1699 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1700 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1701 pltmp[10] = 0X40000528; //0x40000228
1702 pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
1703 reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1704 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1705
1706 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1707 reg->BB30 = 0x00002C54;
1708 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1709 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
1710 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1711 reg->BB3C = 0x00000000;
1712 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1713 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1714 pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
1715 reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
1716 pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
1717 reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1
1718 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1719 reg->BB50 = 0x27106200;
1720 pltmp[9] = 0; // 0x1054
1721 reg->BB54 = 0x00000000;
1722 pltmp[10] = 0x52523232; // 20060419 0x52524242; // 0x1058 IQ_Alpha
1723 reg->BB58 = 0x52523232; // 20060419 0x52524242;
1724 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1725 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1726
1727 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1728 break;
1729
1730 case RF_AIROHA_7230:
1731 /*
1732 pltmp[0] = 0x16a84a77; // 0x1000 AGC_Ctrl1
1733 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1734 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1735 pltmp[3] = 0xFFFb203a; // 0x100c AGC_Ctrl4
1736 reg->BB0c = 0xFFFb203a;
1737 pltmp[4] = 0x0FBFDCB7; // 0x1010 AGC_Ctrl5
1738 pltmp[5] = 0x00caa333; // 0x1014 AGC_Ctrl6
1739 pltmp[6] = 0xf6632112; // 0x1018 AGC_Ctrl7
1740 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1741 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1742 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1743 pltmp[10] = 0x40000228;
1744 pltmp[11] = 0x232A9F30;// 0x102c A_ACQ_Ctrl
1745 reg->BB2c = 0x232A9F30;
1746 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1747
1748 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1749 reg->BB30 = 0x00002C54;
1750 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1751 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1752 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1753 reg->BB3c = 0x00000000;
1754 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1755 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1756 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1757 pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
1758 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1759 reg->BB50 = 0x27106200;
1760 pltmp[9] = 0; // 0x1054
1761 reg->BB54 = 0x00000000;
1762 pltmp[10] = 0x64645252; // 0x1058 IQ_Alpha
1763 reg->BB58 = 0x64645252;
1764 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1765 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1766 */
1767 BBProcessor_AL7230_2400( pHwData );
1768
1769 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1770 break;
1771
1772 case RF_WB_242:
1773 case RF_WB_242_1: // 20060619.5 Add
1774
1775 pltmp[0] = 0x16A8525D; // 0x1000 AGC_Ctrl1
1776 pltmp[1] = 0x9AFF9ABA; // 0x1004 AGC_Ctrl2
1777 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1778 pltmp[3] = 0xEEE91C32; // 0x100c AGC_Ctrl4
1779 reg->BB0C = 0xEEE91C32;
1780 pltmp[4] = 0x0FACDCC5; // 0x1010 AGC_Ctrl5
1781 pltmp[5] = 0x000AA344; // 0x1014 AGC_Ctrl6
1782 pltmp[6] = 0x22222221; // 0x1018 AGC_Ctrl7
1783 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1784 pltmp[8] = 0x04CC3440; // 20051018 0x03CB3440; // 0x1020 AGC_Ctrl9 20051014 0x03C33440
1785 pltmp[9] = 0xA9002A79; // 0x1024 AGC_Ctrl10
1786 pltmp[10] = 0x40000528; // 0x1028
1787 pltmp[11] = 0x23457F30; // 0x102c A_ACQ_Ctrl
1788 reg->BB2C = 0x23457F30;
1789 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1790
1791 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1792 reg->BB30 = 0x00002C54;
1793 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1794 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1795 pltmp[3] = pHwData->BB3c_cal; // 0x103c 11a TX LS filter
1796 reg->BB3C = pHwData->BB3c_cal;
1797 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1798 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1799 pltmp[6] = BB48_DEFAULT_WB242_11G; // 0x1048 11b TX RC filter 20060613.2
1800 reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2
1801 pltmp[7] = BB4C_DEFAULT_WB242_11G; // 0x104c 11b TX RC filter 20060613.2
1802 reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2
1803 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1804 reg->BB50 = 0x27106208;
1805 pltmp[9] = pHwData->BB54_cal; // 0x1054
1806 reg->BB54 = pHwData->BB54_cal;
1807 pltmp[10] = 0x52523131; // 0x1058 IQ_Alpha
1808 reg->BB58 = 0x52523131;
1809 pltmp[11] = 0xAA0AC000; // 20060825 0xAA2AC000; // 0x105c DC_Cancel
1810 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1811
1812 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1813 break;
1814 }
1815
1816 // Fill the LNA table
1817 reg->LNAValue[0] = (u8)(reg->BB0C & 0xff);
1818 reg->LNAValue[1] = 0;
1819 reg->LNAValue[2] = (u8)((reg->BB0C & 0xff00)>>8);
1820 reg->LNAValue[3] = 0;
1821
1822 // Fill SQ3 table
1823 for( i=0; i<MAX_SQ3_FILTER_SIZE; i++ )
1824 reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6
1825 }
1826
1827 void set_tx_power_per_channel_max2829( phw_data_t pHwData, ChanInfo Channel)
1828 {
1829 RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify
1830 }
1831
1832 void set_tx_power_per_channel_al2230( phw_data_t pHwData, ChanInfo Channel )
1833 {
1834 u8 index = 100;
1835
1836 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) // 20060620.1 Add
1837 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1838
1839 RFSynthesizer_SetPowerIndex( pHwData, index );
1840 }
1841
1842 void set_tx_power_per_channel_al7230( phw_data_t pHwData, ChanInfo Channel)
1843 {
1844 u8 i, index = 100;
1845
1846 switch ( Channel.band )
1847 {
1848 case BAND_TYPE_DSSS:
1849 case BAND_TYPE_OFDM_24:
1850 {
1851 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1852 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1853 }
1854 break;
1855 case BAND_TYPE_OFDM_5:
1856 {
1857 for (i =0; i<35; i++)
1858 {
1859 if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo)
1860 {
1861 if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff)
1862 index = pHwData->TxVgaFor50[i].TxVgaValue;
1863 break;
1864 }
1865 }
1866 }
1867 break;
1868 }
1869 RFSynthesizer_SetPowerIndex( pHwData, index );
1870 }
1871
1872 void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel)
1873 {
1874 u8 index = 100;
1875
1876 switch ( Channel.band )
1877 {
1878 case BAND_TYPE_DSSS:
1879 case BAND_TYPE_OFDM_24:
1880 {
1881 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1882 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1883 }
1884 break;
1885 case BAND_TYPE_OFDM_5:
1886 break;
1887 }
1888 RFSynthesizer_SetPowerIndex( pHwData, index );
1889 }
1890
1891 //=============================================================================================================
1892 // RFSynthesizer_SwitchingChannel --
1893 //
1894 // Description:
1895 // Swithch the RF channel.
1896 //
1897 // Arguments:
1898 // pHwData - Handle of the USB Device.
1899 // Channel - The channel no.
1900 //
1901 // Return values:
1902 // None.
1903 //=============================================================================================================
1904 void
1905 RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel )
1906 {
1907 struct wb35_reg *reg = &pHwData->reg;
1908 u32 pltmp[16]; // The 16 is the maximum capability of hardware
1909 u32 count, ltmp;
1910 u8 i, j, number;
1911 u8 ChnlTmp;
1912
1913 switch( pHwData->phy_type )
1914 {
1915 case RF_MAXIM_2825:
1916 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1917
1918 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1919 {
1920 for( i=0; i<3; i++ )
1921 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_channel_data_24[Channel.ChanNo-1][i], 18);
1922 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1923 }
1924 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1925 break;
1926
1927 case RF_MAXIM_2827:
1928
1929 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1930 {
1931 for( i=0; i<3; i++ )
1932 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_24[Channel.ChanNo-1][i], 18);
1933 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1934 }
1935 else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64
1936 {
1937 ChnlTmp = (Channel.ChanNo - 36) / 4;
1938 for( i=0; i<3; i++ )
1939 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_50[ChnlTmp][i], 18);
1940 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1941 }
1942 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1943 break;
1944
1945 case RF_MAXIM_2828:
1946
1947 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1948 {
1949 for( i=0; i<3; i++ )
1950 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_24[Channel.ChanNo-1][i], 18);
1951 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1952 }
1953 else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64
1954 {
1955 ChnlTmp = (Channel.ChanNo - 36) / 4;
1956 for ( i = 0; i < 3; i++)
1957 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_50[ChnlTmp][i], 18);
1958 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1959 }
1960 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1961 break;
1962
1963 case RF_MAXIM_2829:
1964
1965 if( Channel.band <= BAND_TYPE_OFDM_24)
1966 {
1967 for( i=0; i<3; i++ )
1968 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_24[Channel.ChanNo-1][i], 18);
1969 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1970 }
1971 else if( Channel.band == BAND_TYPE_OFDM_5 )
1972 {
1973 count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]);
1974
1975 for( i=0; i<count; i++ )
1976 {
1977 if( max2829_channel_data_50[i][0] == Channel.ChanNo )
1978 {
1979 for( j=0; j<3; j++ )
1980 pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_50[i][j+1], 18);
1981 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1982
1983 if( (max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946 )
1984 {
1985 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A906, 18);
1986 Wb35Reg_Write( pHwData, 0x0864, ltmp );
1987 }
1988 else // 0x2A9C6
1989 {
1990 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A986, 18);
1991 Wb35Reg_Write( pHwData, 0x0864, ltmp );
1992 }
1993 }
1994 }
1995 }
1996 set_tx_power_per_channel_max2829( pHwData, Channel );
1997 break;
1998
1999 case RF_AIROHA_2230:
2000 case RF_AIROHA_2230S: // 20060420 Add this
2001
2002 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2003 {
2004 for( i=0; i<2; i++ )
2005 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_channel_data_24[Channel.ChanNo-1][i], 20);
2006 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT );
2007 }
2008 set_tx_power_per_channel_al2230( pHwData, Channel );
2009 break;
2010
2011 case RF_AIROHA_7230:
2012
2013 //Start to fill RF parameters, PLL_ON should be pulled low.
2014 //Wb35Reg_Write( pHwData, 0x03dc, 0x00000000 );
2015 //WBDEBUG(("* PLL_ON low\n"));
2016
2017 //Channel independent registers
2018 if( Channel.band != pHwData->band)
2019 {
2020 if (Channel.band <= BAND_TYPE_OFDM_24)
2021 {
2022 //Update BB register
2023 BBProcessor_AL7230_2400(pHwData);
2024
2025 number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]);
2026 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
2027 }
2028 else
2029 {
2030 //Update BB register
2031 BBProcessor_AL7230_5000(pHwData);
2032
2033 number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]);
2034 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
2035 }
2036
2037 // Write to register. number must less and equal than 16
2038 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, number, NO_INCREMENT );
2039 #ifdef _PE_STATE_DUMP_
2040 WBDEBUG(("Band changed\n"));
2041 #endif
2042 }
2043
2044 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2045 {
2046 for( i=0; i<2; i++ )
2047 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff);
2048 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT );
2049 }
2050 else if( Channel.band == BAND_TYPE_OFDM_5 )
2051 {
2052 //Update Reg12
2053 if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165))
2054 {
2055 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c;
2056 Wb35Reg_Write( pHwData, 0x0864, ltmp );
2057 }
2058 else //reg12 = 0x00147c at Channel 4920 ~ 5320
2059 {
2060 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c;
2061 Wb35Reg_Write( pHwData, 0x0864, ltmp );
2062 }
2063
2064 count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]);
2065
2066 for (i=0; i<count; i++)
2067 {
2068 if (al7230_channel_data_5[i][0] == Channel.ChanNo)
2069 {
2070 for( j=0; j<3; j++ )
2071 pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | ( al7230_channel_data_5[i][j+1]&0xffffff);
2072 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
2073 }
2074 }
2075 }
2076 set_tx_power_per_channel_al7230(pHwData, Channel);
2077 break;
2078
2079 case RF_WB_242:
2080 case RF_WB_242_1: // 20060619.5 Add
2081
2082 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2083 {
2084 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_channel_data_24[Channel.ChanNo-1][0], 24);
2085 Wb35Reg_Write( pHwData, 0x864, ltmp );
2086 }
2087 set_tx_power_per_channel_wb242(pHwData, Channel);
2088 break;
2089 }
2090
2091 if( Channel.band <= BAND_TYPE_OFDM_24 )
2092 {
2093 // BB: select 2.4 GHz, bit[12-11]=00
2094 reg->BB50 &= ~(BIT(11)|BIT(12));
2095 Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl
2096 // MAC: select 2.4 GHz, bit[5]=0
2097 reg->M78_ERPInformation &= ~BIT(5);
2098 Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation );
2099 // enable 11b Baseband
2100 reg->BB30 &= ~BIT(31);
2101 Wb35Reg_Write( pHwData, 0x1030, reg->BB30 );
2102 }
2103 else if( (Channel.band == BAND_TYPE_OFDM_5) )
2104 {
2105 // BB: select 5 GHz
2106 reg->BB50 &= ~(BIT(11)|BIT(12));
2107 if (Channel.ChanNo <=64 )
2108 reg->BB50 |= BIT(12); // 10-5.25GHz
2109 else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124))
2110 reg->BB50 |= BIT(11); // 01-5.48GHz
2111 else if ((Channel.ChanNo >=128) && (Channel.ChanNo <= 161))
2112 reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz
2113 else //Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25
2114 reg->BB50 |= BIT(12);
2115 Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl
2116
2117 //(1) M78 should alway use 2.4G setting when using RF_AIROHA_7230
2118 //(2) BB30 has been updated previously.
2119 if (pHwData->phy_type != RF_AIROHA_7230)
2120 {
2121 // MAC: select 5 GHz, bit[5]=1
2122 reg->M78_ERPInformation |= BIT(5);
2123 Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation );
2124
2125 // disable 11b Baseband
2126 reg->BB30 |= BIT(31);
2127 Wb35Reg_Write( pHwData, 0x1030, reg->BB30 );
2128 }
2129 }
2130 }
2131
2132 //Set the tx power directly from DUT GUI, not from the EEPROM. Return the current setting
2133 u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex )
2134 {
2135 u32 Band = pHwData->band;
2136 u8 index=0;
2137
2138 if( pHwData->power_index == PowerIndex ) // 20060620.1 Add
2139 return PowerIndex;
2140
2141 if (RF_MAXIM_2825 == pHwData->phy_type)
2142 {
2143 // Channel 1 - 13
2144 index = RFSynthesizer_SetMaxim2825Power( pHwData, PowerIndex );
2145 }
2146 else if (RF_MAXIM_2827 == pHwData->phy_type)
2147 {
2148 if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13
2149 index = RFSynthesizer_SetMaxim2827_24Power( pHwData, PowerIndex );
2150 else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64
2151 index = RFSynthesizer_SetMaxim2827_50Power( pHwData, PowerIndex );
2152 }
2153 else if (RF_MAXIM_2828 == pHwData->phy_type)
2154 {
2155 if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13
2156 index = RFSynthesizer_SetMaxim2828_24Power( pHwData, PowerIndex );
2157 else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64
2158 index = RFSynthesizer_SetMaxim2828_50Power( pHwData, PowerIndex );
2159 }
2160 else if( RF_AIROHA_2230 == pHwData->phy_type )
2161 {
2162 //Power index: 0 ~ 63 // Channel 1 - 14
2163 index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex );
2164 index = (u8)al2230_txvga_data[index][1];
2165 }
2166 else if( RF_AIROHA_2230S == pHwData->phy_type ) // 20060420 Add this
2167 {
2168 //Power index: 0 ~ 63 // Channel 1 - 14
2169 index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex );
2170 index = (u8)al2230_txvga_data[index][1];
2171 }
2172 else if( RF_AIROHA_7230 == pHwData->phy_type )
2173 {
2174 //Power index: 0 ~ 63
2175 index = RFSynthesizer_SetAiroha7230Power( pHwData, PowerIndex );
2176 index = (u8)al7230_txvga_data[index][1];
2177 }
2178 else if( (RF_WB_242 == pHwData->phy_type) ||
2179 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
2180 {
2181 //Power index: 0 ~ 19 for original. New range is 0 ~ 33
2182 index = RFSynthesizer_SetWinbond242Power( pHwData, PowerIndex );
2183 index = (u8)w89rf242_txvga_data[index][1];
2184 }
2185
2186 pHwData->power_index = index; // Backup current
2187 return index;
2188 }
2189
2190 //-- Sub function
2191 u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t pHwData, u8 index )
2192 {
2193 u32 PowerData;
2194 if( index > 1 ) index = 1;
2195 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_24[index], 18);
2196 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2197 return index;
2198 }
2199 //--
2200 u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t pHwData, u8 index )
2201 {
2202 u32 PowerData;
2203 if( index > 1 ) index = 1;
2204 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_50[index], 18);
2205 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2206 return index;
2207 }
2208 //--
2209 u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t pHwData, u8 index )
2210 {
2211 u32 PowerData;
2212 if( index > 1 ) index = 1;
2213 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_24[index], 18);
2214 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2215 return index;
2216 }
2217 //--
2218 u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t pHwData, u8 index )
2219 {
2220 u32 PowerData;
2221 if( index > 1 ) index = 1;
2222 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_50[index], 18);
2223 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2224 return index;
2225 }
2226 //--
2227 u8 RFSynthesizer_SetMaxim2825Power( phw_data_t pHwData, u8 index )
2228 {
2229 u32 PowerData;
2230 if( index > 1 ) index = 1;
2231 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_power_data_24[index], 18);
2232 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2233 return index;
2234 }
2235 //--
2236 u8 RFSynthesizer_SetAiroha2230Power( phw_data_t pHwData, u8 index )
2237 {
2238 u32 PowerData;
2239 u8 i,count;
2240
2241 count = sizeof(al2230_txvga_data) / sizeof(al2230_txvga_data[0]);
2242 for (i=0; i<count; i++)
2243 {
2244 if (al2230_txvga_data[i][1] >= index)
2245 break;
2246 }
2247 if (i == count)
2248 i--;
2249
2250 PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_txvga_data[i][0], 20);
2251 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2252 return i;
2253 }
2254 //--
2255 u8 RFSynthesizer_SetAiroha7230Power( phw_data_t pHwData, u8 index )
2256 {
2257 u32 PowerData;
2258 u8 i,count;
2259
2260 //PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( airoha_power_data_24[index], 20);
2261 count = sizeof(al7230_txvga_data) / sizeof(al7230_txvga_data[0]);
2262 for (i=0; i<count; i++)
2263 {
2264 if (al7230_txvga_data[i][1] >= index)
2265 break;
2266 }
2267 if (i == count)
2268 i--;
2269 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0]&0xffffff);
2270 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2271 return i;
2272 }
2273
2274 u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index )
2275 {
2276 u32 PowerData;
2277 u8 i,count;
2278
2279 count = sizeof(w89rf242_txvga_data) / sizeof(w89rf242_txvga_data[0]);
2280 for (i=0; i<count; i++)
2281 {
2282 if (w89rf242_txvga_data[i][1] >= index)
2283 break;
2284 }
2285 if (i == count)
2286 i--;
2287
2288 // Set TxVga into RF
2289 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_txvga_data[i][0], 24);
2290 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2291
2292 // Update BB48 BB4C BB58 for high precision txvga
2293 Wb35Reg_Write( pHwData, 0x1048, w89rf242_txvga_data[i][2] );
2294 Wb35Reg_Write( pHwData, 0x104c, w89rf242_txvga_data[i][3] );
2295 Wb35Reg_Write( pHwData, 0x1058, w89rf242_txvga_data[i][4] );
2296
2297 // Rf vga 0 ~ 3 for temperature compensate. It will affect the scan Bss.
2298 // The i value equals to 8 or 7 usually. So It's not necessary to setup this RF register.
2299 // if( i <= 3 )
2300 // PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x000024, 24 );
2301 // else
2302 // PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x001824, 24 );
2303 // Wb35Reg_Write( pHwData, 0x0864, PowerData );
2304 return i;
2305 }
2306
2307 //===========================================================================================================
2308 // Dxx_initial --
2309 // Mxx_initial --
2310 //
2311 // Routine Description:
2312 // Initial the hardware setting and module variable
2313 //
2314 //===========================================================================================================
2315 void Dxx_initial( phw_data_t pHwData )
2316 {
2317 struct wb35_reg *reg = &pHwData->reg;
2318
2319 // Old IC:Single mode only.
2320 // New IC: operation decide by Software set bit[4]. 1:multiple 0: single
2321 reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA
2322 //Txon, Rxon, single Rx for old 8k ASIC
2323 if( !HAL_USB_MODE_BURST( pHwData ) )
2324 reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA
2325
2326 Wb35Reg_WriteSync( pHwData, 0x0400, reg->D00_DmaControl );
2327 }
2328
2329 void Mxx_initial( phw_data_t pHwData )
2330 {
2331 struct wb35_reg *reg = &pHwData->reg;
2332 u32 tmp;
2333 u32 pltmp[11];
2334 u16 i;
2335
2336
2337 //======================================================
2338 // Initial Mxx register
2339 //======================================================
2340
2341 // M00 bit set
2342 #ifdef _IBSS_BEACON_SEQ_STICK_
2343 reg->M00_MacControl = 0; // Solve beacon sequence number stop by software
2344 #else
2345 reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware
2346 #endif
2347
2348 // M24 disable enter power save, BB RxOn and enable NAV attack
2349 reg->M24_MacControl = 0x08040042;
2350 pltmp[0] = reg->M24_MacControl;
2351
2352 pltmp[1] = 0; // Skip M28, because no initialize value is required.
2353
2354 // M2C CWmin and CWmax setting
2355 pHwData->cwmin = DEFAULT_CWMIN;
2356 pHwData->cwmax = DEFAULT_CWMAX;
2357 reg->M2C_MacControl = DEFAULT_CWMIN << 10;
2358 reg->M2C_MacControl |= DEFAULT_CWMAX;
2359 pltmp[2] = reg->M2C_MacControl;
2360
2361 // M30 BSSID
2362 pltmp[3] = *(u32 *)pHwData->bssid;
2363
2364 // M34
2365 pHwData->AID = DEFAULT_AID;
2366 tmp = *(u16 *)(pHwData->bssid+4);
2367 tmp |= DEFAULT_AID << 16;
2368 pltmp[4] = tmp;
2369
2370 // M38
2371 reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT;
2372 pltmp[5] = reg->M38_MacControl;
2373
2374 // M3C
2375 tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ;
2376 reg->M3C_MacControl = tmp;
2377 pltmp[6] = tmp;
2378
2379 // M40
2380 pHwData->slot_time_select = DEFAULT_SLOT_TIME;
2381 tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME;
2382 reg->M40_MacControl = tmp;
2383 pltmp[7] = tmp;
2384
2385 // M44
2386 tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; // *1024
2387 reg->M44_MacControl = tmp;
2388 pltmp[8] = tmp;
2389
2390 // M48
2391 pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL;
2392 pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME;
2393 tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME;
2394 reg->M48_MacControl = tmp;
2395 pltmp[9] = tmp;
2396
2397 //M4C
2398 reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24);
2399 pltmp[10] = reg->M4C_MacStatus;
2400
2401 // Burst write
2402 //Wb35Reg_BurstWrite( pHwData, 0x0824, pltmp, 11, AUTO_INCREMENT );
2403 for( i=0; i<11; i++ )
2404 Wb35Reg_WriteSync( pHwData, 0x0824 + i*4, pltmp[i] );
2405
2406 // M60
2407 Wb35Reg_WriteSync( pHwData, 0x0860, 0x12481248 );
2408 reg->M60_MacControl = 0x12481248;
2409
2410 // M68
2411 Wb35Reg_WriteSync( pHwData, 0x0868, 0x00050900 ); // 20051018 0x000F0F00 ); // 940930 0x00131300
2412 reg->M68_MacControl = 0x00050900;
2413
2414 // M98
2415 Wb35Reg_WriteSync( pHwData, 0x0898, 0xffff8888 );
2416 reg->M98_MacControl = 0xffff8888;
2417 }
2418
2419
2420 void Uxx_power_off_procedure( phw_data_t pHwData )
2421 {
2422 // SW, PMU reset and turn off clock
2423 Wb35Reg_WriteSync( pHwData, 0x03b0, 3 );
2424 Wb35Reg_WriteSync( pHwData, 0x03f0, 0xf9 );
2425 }
2426
2427 //Decide the TxVga of every channel
2428 void GetTxVgaFromEEPROM( phw_data_t pHwData )
2429 {
2430 u32 i, j, ltmp;
2431 u16 Value[MAX_TXVGA_EEPROM];
2432 u8 *pctmp;
2433 u8 ctmp=0;
2434
2435 // Get the entire TxVga setting in EEPROM
2436 for( i=0; i<MAX_TXVGA_EEPROM; i++ )
2437 {
2438 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 + 0x00010000*i );
2439 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
2440 Value[i] = (u16)( ltmp & 0xffff ); // Get 16 bit available
2441 Value[i] = cpu_to_le16( Value[i] ); // [7:0]2412 [7:0]2417 ....
2442 }
2443
2444 // Adjust the filed which fills with reserved value.
2445 pctmp = (u8 *)Value;
2446 for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ )
2447 {
2448 if( pctmp[i] != 0xff )
2449 ctmp = pctmp[i];
2450 else
2451 pctmp[i] = ctmp;
2452 }
2453
2454 // Adjust WB_242 to WB_242_1 TxVga scale
2455 if( pHwData->phy_type == RF_WB_242 )
2456 {
2457 for( i=0; i<4; i++ ) // Only 2412 2437 2462 2484 case must be modified
2458 {
2459 for( j=0; j<(sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])); j++ )
2460 {
2461 if( pctmp[i] < (u8)w89rf242_txvga_old_mapping[j][1] )
2462 {
2463 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j][0];
2464 break;
2465 }
2466 }
2467
2468 if( j == (sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])) )
2469 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0];
2470 }
2471 }
2472
2473 // 20060621 Add
2474 memcpy( pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM*2 ); //MAX_TXVGA_EEPROM is u16 count
2475 EEPROMTxVgaAdjust( pHwData );
2476 }
2477
2478 // This function will affect the TxVga parameter in HAL. If hal_set_current_channel
2479 // or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect.
2480 // TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35
2481 // This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
2482 void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add
2483 {
2484 u8 * pTxVga = pHwData->TxVgaSettingInEEPROM;
2485 s16 i, stmp;
2486
2487 //-- 2.4G -- 20060704.2 Request from Tiger
2488 //channel 1 ~ 5
2489 stmp = pTxVga[1] - pTxVga[0];
2490 for( i=0; i<5; i++ )
2491 pHwData->TxVgaFor24[i] = pTxVga[0] + stmp*i/4;
2492 //channel 6 ~ 10
2493 stmp = pTxVga[2] - pTxVga[1];
2494 for( i=5; i<10; i++ )
2495 pHwData->TxVgaFor24[i] = pTxVga[1] + stmp*(i-5)/4;
2496 //channel 11 ~ 13
2497 stmp = pTxVga[3] - pTxVga[2];
2498 for( i=10; i<13; i++ )
2499 pHwData->TxVgaFor24[i] = pTxVga[2] + stmp*(i-10)/2;
2500 //channel 14
2501 pHwData->TxVgaFor24[13] = pTxVga[3];
2502
2503 //-- 5G --
2504 if( pHwData->phy_type == RF_AIROHA_7230 )
2505 {
2506 //channel 184
2507 pHwData->TxVgaFor50[0].ChanNo = 184;
2508 pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4];
2509 //channel 196
2510 pHwData->TxVgaFor50[3].ChanNo = 196;
2511 pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5];
2512 //interpolate
2513 pHwData->TxVgaFor50[1].ChanNo = 188;
2514 pHwData->TxVgaFor50[2].ChanNo = 192;
2515 stmp = pTxVga[5] - pTxVga[4];
2516 pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp/3;
2517 pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp*2/3;
2518
2519 //channel 16
2520 pHwData->TxVgaFor50[6].ChanNo = 16;
2521 pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6];
2522 pHwData->TxVgaFor50[4].ChanNo = 8;
2523 pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6];
2524 pHwData->TxVgaFor50[5].ChanNo = 12;
2525 pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6];
2526
2527 //channel 36
2528 pHwData->TxVgaFor50[8].ChanNo = 36;
2529 pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7];
2530 pHwData->TxVgaFor50[7].ChanNo = 34;
2531 pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7];
2532 pHwData->TxVgaFor50[9].ChanNo = 38;
2533 pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7];
2534
2535 //channel 40
2536 pHwData->TxVgaFor50[10].ChanNo = 40;
2537 pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8];
2538 //channel 48
2539 pHwData->TxVgaFor50[14].ChanNo = 48;
2540 pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9];
2541 //interpolate
2542 pHwData->TxVgaFor50[11].ChanNo = 42;
2543 pHwData->TxVgaFor50[12].ChanNo = 44;
2544 pHwData->TxVgaFor50[13].ChanNo = 46;
2545 stmp = pTxVga[9] - pTxVga[8];
2546 pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp/4;
2547 pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp*2/4;
2548 pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp*3/4;
2549
2550 //channel 52
2551 pHwData->TxVgaFor50[15].ChanNo = 52;
2552 pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10];
2553 //channel 64
2554 pHwData->TxVgaFor50[18].ChanNo = 64;
2555 pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11];
2556 //interpolate
2557 pHwData->TxVgaFor50[16].ChanNo = 56;
2558 pHwData->TxVgaFor50[17].ChanNo = 60;
2559 stmp = pTxVga[11] - pTxVga[10];
2560 pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp/3;
2561 pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp*2/3;
2562
2563 //channel 100
2564 pHwData->TxVgaFor50[19].ChanNo = 100;
2565 pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12];
2566 //channel 112
2567 pHwData->TxVgaFor50[22].ChanNo = 112;
2568 pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13];
2569 //interpolate
2570 pHwData->TxVgaFor50[20].ChanNo = 104;
2571 pHwData->TxVgaFor50[21].ChanNo = 108;
2572 stmp = pTxVga[13] - pTxVga[12];
2573 pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp/3;
2574 pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp*2/3;
2575
2576 //channel 128
2577 pHwData->TxVgaFor50[26].ChanNo = 128;
2578 pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14];
2579 //interpolate
2580 pHwData->TxVgaFor50[23].ChanNo = 116;
2581 pHwData->TxVgaFor50[24].ChanNo = 120;
2582 pHwData->TxVgaFor50[25].ChanNo = 124;
2583 stmp = pTxVga[14] - pTxVga[13];
2584 pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp/4;
2585 pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp*2/4;
2586 pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp*3/4;
2587
2588 //channel 140
2589 pHwData->TxVgaFor50[29].ChanNo = 140;
2590 pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15];
2591 //interpolate
2592 pHwData->TxVgaFor50[27].ChanNo = 132;
2593 pHwData->TxVgaFor50[28].ChanNo = 136;
2594 stmp = pTxVga[15] - pTxVga[14];
2595 pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp/3;
2596 pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp*2/3;
2597
2598 //channel 149
2599 pHwData->TxVgaFor50[30].ChanNo = 149;
2600 pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16];
2601 //channel 165
2602 pHwData->TxVgaFor50[34].ChanNo = 165;
2603 pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17];
2604 //interpolate
2605 pHwData->TxVgaFor50[31].ChanNo = 153;
2606 pHwData->TxVgaFor50[32].ChanNo = 157;
2607 pHwData->TxVgaFor50[33].ChanNo = 161;
2608 stmp = pTxVga[17] - pTxVga[16];
2609 pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp/4;
2610 pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp*2/4;
2611 pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp*3/4;
2612 }
2613
2614 #ifdef _PE_STATE_DUMP_
2615 WBDEBUG((" TxVgaFor24 : \n"));
2616 DataDmp((u8 *)pHwData->TxVgaFor24, 14 ,0);
2617 WBDEBUG((" TxVgaFor50 : \n"));
2618 DataDmp((u8 *)pHwData->TxVgaFor50, 70 ,0);
2619 #endif
2620 }
2621
2622 void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
2623 {
2624 struct wb35_reg *reg = &pHwData->reg;
2625 unsigned char Is11bRate;
2626
2627 Is11bRate = (rate % 6) ? 1 : 0;
2628 switch( pHwData->phy_type )
2629 {
2630 case RF_AIROHA_2230:
2631 case RF_AIROHA_2230S: // 20060420 Add this
2632 if( Is11bRate )
2633 {
2634 if( (reg->BB48 != BB48_DEFAULT_AL2230_11B) &&
2635 (reg->BB4C != BB4C_DEFAULT_AL2230_11B) )
2636 {
2637 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11B );
2638 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B );
2639 }
2640 }
2641 else
2642 {
2643 if( (reg->BB48 != BB48_DEFAULT_AL2230_11G) &&
2644 (reg->BB4C != BB4C_DEFAULT_AL2230_11G) )
2645 {
2646 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11G );
2647 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G );
2648 }
2649 }
2650 break;
2651
2652 case RF_WB_242: // 20060623 The fix only for old TxVGA setting
2653 if( Is11bRate )
2654 {
2655 if( (reg->BB48 != BB48_DEFAULT_WB242_11B) &&
2656 (reg->BB4C != BB4C_DEFAULT_WB242_11B) )
2657 {
2658 reg->BB48 = BB48_DEFAULT_WB242_11B;
2659 reg->BB4C = BB4C_DEFAULT_WB242_11B;
2660 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11B );
2661 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11B );
2662 }
2663 }
2664 else
2665 {
2666 if( (reg->BB48 != BB48_DEFAULT_WB242_11G) &&
2667 (reg->BB4C != BB4C_DEFAULT_WB242_11G) )
2668 {
2669 reg->BB48 = BB48_DEFAULT_WB242_11G;
2670 reg->BB4C = BB4C_DEFAULT_WB242_11G;
2671 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11G );
2672 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11G );
2673 }
2674 }
2675 break;
2676 }
2677 }
2678
2679
2680
2681
2682
2683
2684
Linux for Ginger Game Console