?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Save sram context after changing MPU, DSP or core clocks
[linux-ginger.git] / drivers / net / atl1e / atl1e_main.c
blob955da733c2ad9957320aafa545351b771c40056a
1 /*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include "atl1e.h"
23
24 #define DRV_VERSION "1.0.0.7-NAPI"
25
26 char atl1e_driver_name[] = "ATL1E";
27 char atl1e_driver_version[] = DRV_VERSION;
28 #define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
29 /*
30 * atl1e_pci_tbl - PCI Device ID Table
31 *
32 * Wildcard entries (PCI_ANY_ID) should come last
33 * Last entry must be all 0s
34 *
35 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
36 * Class, Class Mask, private data (not used) }
37 */
38 static struct pci_device_id atl1e_pci_tbl[] = {
39 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1E)},
40 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, 0x1066)},
41 /* required last entry */
42 { 0 }
43 };
44 MODULE_DEVICE_TABLE(pci, atl1e_pci_tbl);
45
46 MODULE_AUTHOR("Atheros Corporation, <xiong.huang@atheros.com>, Jie Yang <jie.yang@atheros.com>");
47 MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
48 MODULE_LICENSE("GPL");
49 MODULE_VERSION(DRV_VERSION);
50
51 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
52
53 static const u16
54 atl1e_rx_page_vld_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
55 {
56 {REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD},
57 {REG_HOST_RXF1_PAGE0_VLD, REG_HOST_RXF1_PAGE1_VLD},
58 {REG_HOST_RXF2_PAGE0_VLD, REG_HOST_RXF2_PAGE1_VLD},
59 {REG_HOST_RXF3_PAGE0_VLD, REG_HOST_RXF3_PAGE1_VLD}
60 };
61
62 static const u16 atl1e_rx_page_hi_addr_regs[AT_MAX_RECEIVE_QUEUE] =
63 {
64 REG_RXF0_BASE_ADDR_HI,
65 REG_RXF1_BASE_ADDR_HI,
66 REG_RXF2_BASE_ADDR_HI,
67 REG_RXF3_BASE_ADDR_HI
68 };
69
70 static const u16
71 atl1e_rx_page_lo_addr_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
72 {
73 {REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO},
74 {REG_HOST_RXF1_PAGE0_LO, REG_HOST_RXF1_PAGE1_LO},
75 {REG_HOST_RXF2_PAGE0_LO, REG_HOST_RXF2_PAGE1_LO},
76 {REG_HOST_RXF3_PAGE0_LO, REG_HOST_RXF3_PAGE1_LO}
77 };
78
79 static const u16
80 atl1e_rx_page_write_offset_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
81 {
82 {REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO},
83 {REG_HOST_RXF1_MB0_LO, REG_HOST_RXF1_MB1_LO},
84 {REG_HOST_RXF2_MB0_LO, REG_HOST_RXF2_MB1_LO},
85 {REG_HOST_RXF3_MB0_LO, REG_HOST_RXF3_MB1_LO}
86 };
87
88 static const u16 atl1e_pay_load_size[] = {
89 128, 256, 512, 1024, 2048, 4096,
90 };
91
92 /*
93 * atl1e_irq_enable - Enable default interrupt generation settings
94 * @adapter: board private structure
95 */
96 static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
97 {
98 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
99 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
100 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
101 AT_WRITE_FLUSH(&adapter->hw);
102 }
103 }
104
105 /*
106 * atl1e_irq_disable - Mask off interrupt generation on the NIC
107 * @adapter: board private structure
108 */
109 static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
110 {
111 atomic_inc(&adapter->irq_sem);
112 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
113 AT_WRITE_FLUSH(&adapter->hw);
114 synchronize_irq(adapter->pdev->irq);
115 }
116
117 /*
118 * atl1e_irq_reset - reset interrupt confiure on the NIC
119 * @adapter: board private structure
120 */
121 static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
122 {
123 atomic_set(&adapter->irq_sem, 0);
124 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
125 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
126 AT_WRITE_FLUSH(&adapter->hw);
127 }
128
129 /*
130 * atl1e_phy_config - Timer Call-back
131 * @data: pointer to netdev cast into an unsigned long
132 */
133 static void atl1e_phy_config(unsigned long data)
134 {
135 struct atl1e_adapter *adapter = (struct atl1e_adapter *) data;
136 struct atl1e_hw *hw = &adapter->hw;
137 unsigned long flags;
138
139 spin_lock_irqsave(&adapter->mdio_lock, flags);
140 atl1e_restart_autoneg(hw);
141 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
142 }
143
144 void atl1e_reinit_locked(struct atl1e_adapter *adapter)
145 {
146
147 WARN_ON(in_interrupt());
148 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
149 msleep(1);
150 atl1e_down(adapter);
151 atl1e_up(adapter);
152 clear_bit(__AT_RESETTING, &adapter->flags);
153 }
154
155 static void atl1e_reset_task(struct work_struct *work)
156 {
157 struct atl1e_adapter *adapter;
158 adapter = container_of(work, struct atl1e_adapter, reset_task);
159
160 atl1e_reinit_locked(adapter);
161 }
162
163 static int atl1e_check_link(struct atl1e_adapter *adapter)
164 {
165 struct atl1e_hw *hw = &adapter->hw;
166 struct net_device *netdev = adapter->netdev;
167 struct pci_dev *pdev = adapter->pdev;
168 int err = 0;
169 u16 speed, duplex, phy_data;
170
171 /* MII_BMSR must read twise */
172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
173 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
174 if ((phy_data & BMSR_LSTATUS) == 0) {
175 /* link down */
176 if (netif_carrier_ok(netdev)) { /* old link state: Up */
177 u32 value;
178 /* disable rx */
179 value = AT_READ_REG(hw, REG_MAC_CTRL);
180 value &= ~MAC_CTRL_RX_EN;
181 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
182 adapter->link_speed = SPEED_0;
183 netif_carrier_off(netdev);
184 netif_stop_queue(netdev);
185 }
186 } else {
187 /* Link Up */
188 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
189 if (unlikely(err))
190 return err;
191
192 /* link result is our setting */
193 if (adapter->link_speed != speed ||
194 adapter->link_duplex != duplex) {
195 adapter->link_speed = speed;
196 adapter->link_duplex = duplex;
197 atl1e_setup_mac_ctrl(adapter);
198 dev_info(&pdev->dev,
199 "%s: %s NIC Link is Up<%d Mbps %s>\n",
200 atl1e_driver_name, netdev->name,
201 adapter->link_speed,
202 adapter->link_duplex == FULL_DUPLEX ?
203 "Full Duplex" : "Half Duplex");
204 }
205
206 if (!netif_carrier_ok(netdev)) {
207 /* Link down -> Up */
208 netif_carrier_on(netdev);
209 netif_wake_queue(netdev);
210 }
211 }
212 return 0;
213 }
214
215 /*
216 * atl1e_link_chg_task - deal with link change event Out of interrupt context
217 * @netdev: network interface device structure
218 */
219 static void atl1e_link_chg_task(struct work_struct *work)
220 {
221 struct atl1e_adapter *adapter;
222 unsigned long flags;
223
224 adapter = container_of(work, struct atl1e_adapter, link_chg_task);
225 spin_lock_irqsave(&adapter->mdio_lock, flags);
226 atl1e_check_link(adapter);
227 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
228 }
229
230 static void atl1e_link_chg_event(struct atl1e_adapter *adapter)
231 {
232 struct net_device *netdev = adapter->netdev;
233 struct pci_dev *pdev = adapter->pdev;
234 u16 phy_data = 0;
235 u16 link_up = 0;
236
237 spin_lock(&adapter->mdio_lock);
238 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
239 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
240 spin_unlock(&adapter->mdio_lock);
241 link_up = phy_data & BMSR_LSTATUS;
242 /* notify upper layer link down ASAP */
243 if (!link_up) {
244 if (netif_carrier_ok(netdev)) {
245 /* old link state: Up */
246 dev_info(&pdev->dev, "%s: %s NIC Link is Down\n",
247 atl1e_driver_name, netdev->name);
248 adapter->link_speed = SPEED_0;
249 netif_stop_queue(netdev);
250 }
251 }
252 schedule_work(&adapter->link_chg_task);
253 }
254
255 static void atl1e_del_timer(struct atl1e_adapter *adapter)
256 {
257 del_timer_sync(&adapter->phy_config_timer);
258 }
259
260 static void atl1e_cancel_work(struct atl1e_adapter *adapter)
261 {
262 cancel_work_sync(&adapter->reset_task);
263 cancel_work_sync(&adapter->link_chg_task);
264 }
265
266 /*
267 * atl1e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 */
270 static void atl1e_tx_timeout(struct net_device *netdev)
271 {
272 struct atl1e_adapter *adapter = netdev_priv(netdev);
273
274 /* Do the reset outside of interrupt context */
275 schedule_work(&adapter->reset_task);
276 }
277
278 /*
279 * atl1e_set_multi - Multicast and Promiscuous mode set
280 * @netdev: network interface device structure
281 *
282 * The set_multi entry point is called whenever the multicast address
283 * list or the network interface flags are updated. This routine is
284 * responsible for configuring the hardware for proper multicast,
285 * promiscuous mode, and all-multi behavior.
286 */
287 static void atl1e_set_multi(struct net_device *netdev)
288 {
289 struct atl1e_adapter *adapter = netdev_priv(netdev);
290 struct atl1e_hw *hw = &adapter->hw;
291 struct dev_mc_list *mc_ptr;
292 u32 mac_ctrl_data = 0;
293 u32 hash_value;
294
295 /* Check for Promiscuous and All Multicast modes */
296 mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
297
298 if (netdev->flags & IFF_PROMISC) {
299 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
300 } else if (netdev->flags & IFF_ALLMULTI) {
301 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
302 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
303 } else {
304 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
305 }
306
307 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
308
309 /* clear the old settings from the multicast hash table */
310 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
311 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
312
313 /* comoute mc addresses' hash value ,and put it into hash table */
314 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
315 hash_value = atl1e_hash_mc_addr(hw, mc_ptr->dmi_addr);
316 atl1e_hash_set(hw, hash_value);
317 }
318 }
319
320 static void atl1e_vlan_rx_register(struct net_device *netdev,
321 struct vlan_group *grp)
322 {
323 struct atl1e_adapter *adapter = netdev_priv(netdev);
324 struct pci_dev *pdev = adapter->pdev;
325 u32 mac_ctrl_data = 0;
326
327 dev_dbg(&pdev->dev, "atl1e_vlan_rx_register\n");
328
329 atl1e_irq_disable(adapter);
330
331 adapter->vlgrp = grp;
332 mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
333
334 if (grp) {
335 /* enable VLAN tag insert/strip */
336 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
337 } else {
338 /* disable VLAN tag insert/strip */
339 mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
340 }
341
342 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
343 atl1e_irq_enable(adapter);
344 }
345
346 static void atl1e_restore_vlan(struct atl1e_adapter *adapter)
347 {
348 struct pci_dev *pdev = adapter->pdev;
349
350 dev_dbg(&pdev->dev, "atl1e_restore_vlan !");
351 atl1e_vlan_rx_register(adapter->netdev, adapter->vlgrp);
352 }
353 /*
354 * atl1e_set_mac - Change the Ethernet Address of the NIC
355 * @netdev: network interface device structure
356 * @p: pointer to an address structure
357 *
358 * Returns 0 on success, negative on failure
359 */
360 static int atl1e_set_mac_addr(struct net_device *netdev, void *p)
361 {
362 struct atl1e_adapter *adapter = netdev_priv(netdev);
363 struct sockaddr *addr = p;
364
365 if (!is_valid_ether_addr(addr->sa_data))
366 return -EADDRNOTAVAIL;
367
368 if (netif_running(netdev))
369 return -EBUSY;
370
371 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
372 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
373
374 atl1e_hw_set_mac_addr(&adapter->hw);
375
376 return 0;
377 }
378
379 /*
380 * atl1e_change_mtu - Change the Maximum Transfer Unit
381 * @netdev: network interface device structure
382 * @new_mtu: new value for maximum frame size
383 *
384 * Returns 0 on success, negative on failure
385 */
386 static int atl1e_change_mtu(struct net_device *netdev, int new_mtu)
387 {
388 struct atl1e_adapter *adapter = netdev_priv(netdev);
389 int old_mtu = netdev->mtu;
390 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
391
392 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
393 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
394 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
395 return -EINVAL;
396 }
397 /* set MTU */
398 if (old_mtu != new_mtu && netif_running(netdev)) {
399 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
400 msleep(1);
401 netdev->mtu = new_mtu;
402 adapter->hw.max_frame_size = new_mtu;
403 adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
404 atl1e_down(adapter);
405 atl1e_up(adapter);
406 clear_bit(__AT_RESETTING, &adapter->flags);
407 }
408 return 0;
409 }
410
411 /*
412 * caller should hold mdio_lock
413 */
414 static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
415 {
416 struct atl1e_adapter *adapter = netdev_priv(netdev);
417 u16 result;
418
419 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
420 return result;
421 }
422
423 static void atl1e_mdio_write(struct net_device *netdev, int phy_id,
424 int reg_num, int val)
425 {
426 struct atl1e_adapter *adapter = netdev_priv(netdev);
427
428 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
429 }
430
431 /*
432 * atl1e_mii_ioctl -
433 * @netdev:
434 * @ifreq:
435 * @cmd:
436 */
437 static int atl1e_mii_ioctl(struct net_device *netdev,
438 struct ifreq *ifr, int cmd)
439 {
440 struct atl1e_adapter *adapter = netdev_priv(netdev);
441 struct pci_dev *pdev = adapter->pdev;
442 struct mii_ioctl_data *data = if_mii(ifr);
443 unsigned long flags;
444 int retval = 0;
445
446 if (!netif_running(netdev))
447 return -EINVAL;
448
449 spin_lock_irqsave(&adapter->mdio_lock, flags);
450 switch (cmd) {
451 case SIOCGMIIPHY:
452 data->phy_id = 0;
453 break;
454
455 case SIOCGMIIREG:
456 if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
457 &data->val_out)) {
458 retval = -EIO;
459 goto out;
460 }
461 break;
462
463 case SIOCSMIIREG:
464 if (data->reg_num & ~(0x1F)) {
465 retval = -EFAULT;
466 goto out;
467 }
468
469 dev_dbg(&pdev->dev, "<atl1e_mii_ioctl> write %x %x",
470 data->reg_num, data->val_in);
471 if (atl1e_write_phy_reg(&adapter->hw,
472 data->reg_num, data->val_in)) {
473 retval = -EIO;
474 goto out;
475 }
476 break;
477
478 default:
479 retval = -EOPNOTSUPP;
480 break;
481 }
482 out:
483 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
484 return retval;
485
486 }
487
488 /*
489 * atl1e_ioctl -
490 * @netdev:
491 * @ifreq:
492 * @cmd:
493 */
494 static int atl1e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
495 {
496 switch (cmd) {
497 case SIOCGMIIPHY:
498 case SIOCGMIIREG:
499 case SIOCSMIIREG:
500 return atl1e_mii_ioctl(netdev, ifr, cmd);
501 default:
502 return -EOPNOTSUPP;
503 }
504 }
505
506 static void atl1e_setup_pcicmd(struct pci_dev *pdev)
507 {
508 u16 cmd;
509
510 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
511 cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
512 cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
513 pci_write_config_word(pdev, PCI_COMMAND, cmd);
514
515 /*
516 * some motherboards BIOS(PXE/EFI) driver may set PME
517 * while they transfer control to OS (Windows/Linux)
518 * so we should clear this bit before NIC work normally
519 */
520 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
521 msleep(1);
522 }
523
524 /*
525 * atl1e_alloc_queues - Allocate memory for all rings
526 * @adapter: board private structure to initialize
527 *
528 */
529 static int __devinit atl1e_alloc_queues(struct atl1e_adapter *adapter)
530 {
531 return 0;
532 }
533
534 /*
535 * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
536 * @adapter: board private structure to initialize
537 *
538 * atl1e_sw_init initializes the Adapter private data structure.
539 * Fields are initialized based on PCI device information and
540 * OS network device settings (MTU size).
541 */
542 static int __devinit atl1e_sw_init(struct atl1e_adapter *adapter)
543 {
544 struct atl1e_hw *hw = &adapter->hw;
545 struct pci_dev *pdev = adapter->pdev;
546 u32 phy_status_data = 0;
547
548 adapter->wol = 0;
549 adapter->link_speed = SPEED_0; /* hardware init */
550 adapter->link_duplex = FULL_DUPLEX;
551 adapter->num_rx_queues = 1;
552
553 /* PCI config space info */
554 hw->vendor_id = pdev->vendor;
555 hw->device_id = pdev->device;
556 hw->subsystem_vendor_id = pdev->subsystem_vendor;
557 hw->subsystem_id = pdev->subsystem_device;
558
559 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
560 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
561
562 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
563 /* nic type */
564 if (hw->revision_id >= 0xF0) {
565 hw->nic_type = athr_l2e_revB;
566 } else {
567 if (phy_status_data & PHY_STATUS_100M)
568 hw->nic_type = athr_l1e;
569 else
570 hw->nic_type = athr_l2e_revA;
571 }
572
573 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
574
575 if (phy_status_data & PHY_STATUS_EMI_CA)
576 hw->emi_ca = true;
577 else
578 hw->emi_ca = false;
579
580 hw->phy_configured = false;
581 hw->preamble_len = 7;
582 hw->max_frame_size = adapter->netdev->mtu;
583 hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
584 VLAN_HLEN + ETH_FCS_LEN + 7) >> 3;
585
586 hw->rrs_type = atl1e_rrs_disable;
587 hw->indirect_tab = 0;
588 hw->base_cpu = 0;
589
590 /* need confirm */
591
592 hw->ict = 50000; /* 100ms */
593 hw->smb_timer = 200000; /* 200ms */
594 hw->tpd_burst = 5;
595 hw->rrd_thresh = 1;
596 hw->tpd_thresh = adapter->tx_ring.count / 2;
597 hw->rx_count_down = 4; /* 2us resolution */
598 hw->tx_count_down = hw->imt * 4 / 3;
599 hw->dmar_block = atl1e_dma_req_1024;
600 hw->dmaw_block = atl1e_dma_req_1024;
601 hw->dmar_dly_cnt = 15;
602 hw->dmaw_dly_cnt = 4;
603
604 if (atl1e_alloc_queues(adapter)) {
605 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
606 return -ENOMEM;
607 }
608
609 atomic_set(&adapter->irq_sem, 1);
610 spin_lock_init(&adapter->mdio_lock);
611 spin_lock_init(&adapter->tx_lock);
612
613 set_bit(__AT_DOWN, &adapter->flags);
614
615 return 0;
616 }
617
618 /*
619 * atl1e_clean_tx_ring - Free Tx-skb
620 * @adapter: board private structure
621 */
622 static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
623 {
624 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
625 &adapter->tx_ring;
626 struct atl1e_tx_buffer *tx_buffer = NULL;
627 struct pci_dev *pdev = adapter->pdev;
628 u16 index, ring_count;
629
630 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
631 return;
632
633 ring_count = tx_ring->count;
634 /* first unmmap dma */
635 for (index = 0; index < ring_count; index++) {
636 tx_buffer = &tx_ring->tx_buffer[index];
637 if (tx_buffer->dma) {
638 if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
639 pci_unmap_single(pdev, tx_buffer->dma,
640 tx_buffer->length, PCI_DMA_TODEVICE);
641 else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
642 pci_unmap_page(pdev, tx_buffer->dma,
643 tx_buffer->length, PCI_DMA_TODEVICE);
644 tx_buffer->dma = 0;
645 }
646 }
647 /* second free skb */
648 for (index = 0; index < ring_count; index++) {
649 tx_buffer = &tx_ring->tx_buffer[index];
650 if (tx_buffer->skb) {
651 dev_kfree_skb_any(tx_buffer->skb);
652 tx_buffer->skb = NULL;
653 }
654 }
655 /* Zero out Tx-buffers */
656 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
657 ring_count);
658 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
659 ring_count);
660 }
661
662 /*
663 * atl1e_clean_rx_ring - Free rx-reservation skbs
664 * @adapter: board private structure
665 */
666 static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
667 {
668 struct atl1e_rx_ring *rx_ring =
669 (struct atl1e_rx_ring *)&adapter->rx_ring;
670 struct atl1e_rx_page_desc *rx_page_desc = rx_ring->rx_page_desc;
671 u16 i, j;
672
673
674 if (adapter->ring_vir_addr == NULL)
675 return;
676 /* Zero out the descriptor ring */
677 for (i = 0; i < adapter->num_rx_queues; i++) {
678 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
679 if (rx_page_desc[i].rx_page[j].addr != NULL) {
680 memset(rx_page_desc[i].rx_page[j].addr, 0,
681 rx_ring->real_page_size);
682 }
683 }
684 }
685 }
686
687 static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
688 {
689 *ring_size = ((u32)(adapter->tx_ring.count *
690 sizeof(struct atl1e_tpd_desc) + 7
691 /* tx ring, qword align */
692 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE *
693 adapter->num_rx_queues + 31
694 /* rx ring, 32 bytes align */
695 + (1 + AT_PAGE_NUM_PER_QUEUE * adapter->num_rx_queues) *
696 sizeof(u32) + 3));
697 /* tx, rx cmd, dword align */
698 }
699
700 static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
701 {
702 struct atl1e_tx_ring *tx_ring = NULL;
703 struct atl1e_rx_ring *rx_ring = NULL;
704
705 tx_ring = &adapter->tx_ring;
706 rx_ring = &adapter->rx_ring;
707
708 rx_ring->real_page_size = adapter->rx_ring.page_size
709 + adapter->hw.max_frame_size
710 + ETH_HLEN + VLAN_HLEN
711 + ETH_FCS_LEN;
712 rx_ring->real_page_size = roundup(rx_ring->real_page_size, 32);
713 atl1e_cal_ring_size(adapter, &adapter->ring_size);
714
715 adapter->ring_vir_addr = NULL;
716 adapter->rx_ring.desc = NULL;
717 rwlock_init(&adapter->tx_ring.tx_lock);
718
719 return;
720 }
721
722 /*
723 * Read / Write Ptr Initialize:
724 */
725 static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
726 {
727 struct atl1e_tx_ring *tx_ring = NULL;
728 struct atl1e_rx_ring *rx_ring = NULL;
729 struct atl1e_rx_page_desc *rx_page_desc = NULL;
730 int i, j;
731
732 tx_ring = &adapter->tx_ring;
733 rx_ring = &adapter->rx_ring;
734 rx_page_desc = rx_ring->rx_page_desc;
735
736 tx_ring->next_to_use = 0;
737 atomic_set(&tx_ring->next_to_clean, 0);
738
739 for (i = 0; i < adapter->num_rx_queues; i++) {
740 rx_page_desc[i].rx_using = 0;
741 rx_page_desc[i].rx_nxseq = 0;
742 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
743 *rx_page_desc[i].rx_page[j].write_offset_addr = 0;
744 rx_page_desc[i].rx_page[j].read_offset = 0;
745 }
746 }
747 }
748
749 /*
750 * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
751 * @adapter: board private structure
752 *
753 * Free all transmit software resources
754 */
755 static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
756 {
757 struct pci_dev *pdev = adapter->pdev;
758
759 atl1e_clean_tx_ring(adapter);
760 atl1e_clean_rx_ring(adapter);
761
762 if (adapter->ring_vir_addr) {
763 pci_free_consistent(pdev, adapter->ring_size,
764 adapter->ring_vir_addr, adapter->ring_dma);
765 adapter->ring_vir_addr = NULL;
766 }
767
768 if (adapter->tx_ring.tx_buffer) {
769 kfree(adapter->tx_ring.tx_buffer);
770 adapter->tx_ring.tx_buffer = NULL;
771 }
772 }
773
774 /*
775 * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
776 * @adapter: board private structure
777 *
778 * Return 0 on success, negative on failure
779 */
780 static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
781 {
782 struct pci_dev *pdev = adapter->pdev;
783 struct atl1e_tx_ring *tx_ring;
784 struct atl1e_rx_ring *rx_ring;
785 struct atl1e_rx_page_desc *rx_page_desc;
786 int size, i, j;
787 u32 offset = 0;
788 int err = 0;
789
790 if (adapter->ring_vir_addr != NULL)
791 return 0; /* alloced already */
792
793 tx_ring = &adapter->tx_ring;
794 rx_ring = &adapter->rx_ring;
795
796 /* real ring DMA buffer */
797
798 size = adapter->ring_size;
799 adapter->ring_vir_addr = pci_alloc_consistent(pdev,
800 adapter->ring_size, &adapter->ring_dma);
801
802 if (adapter->ring_vir_addr == NULL) {
803 dev_err(&pdev->dev, "pci_alloc_consistent failed, "
804 "size = D%d", size);
805 return -ENOMEM;
806 }
807
808 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
809
810 rx_page_desc = rx_ring->rx_page_desc;
811
812 /* Init TPD Ring */
813 tx_ring->dma = roundup(adapter->ring_dma, 8);
814 offset = tx_ring->dma - adapter->ring_dma;
815 tx_ring->desc = (struct atl1e_tpd_desc *)
816 (adapter->ring_vir_addr + offset);
817 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
818 tx_ring->tx_buffer = kzalloc(size, GFP_KERNEL);
819 if (tx_ring->tx_buffer == NULL) {
820 dev_err(&pdev->dev, "kzalloc failed , size = D%d", size);
821 err = -ENOMEM;
822 goto failed;
823 }
824
825 /* Init RXF-Pages */
826 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
827 offset = roundup(offset, 32);
828
829 for (i = 0; i < adapter->num_rx_queues; i++) {
830 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
831 rx_page_desc[i].rx_page[j].dma =
832 adapter->ring_dma + offset;
833 rx_page_desc[i].rx_page[j].addr =
834 adapter->ring_vir_addr + offset;
835 offset += rx_ring->real_page_size;
836 }
837 }
838
839 /* Init CMB dma address */
840 tx_ring->cmb_dma = adapter->ring_dma + offset;
841 tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset);
842 offset += sizeof(u32);
843
844 for (i = 0; i < adapter->num_rx_queues; i++) {
845 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
846 rx_page_desc[i].rx_page[j].write_offset_dma =
847 adapter->ring_dma + offset;
848 rx_page_desc[i].rx_page[j].write_offset_addr =
849 adapter->ring_vir_addr + offset;
850 offset += sizeof(u32);
851 }
852 }
853
854 if (unlikely(offset > adapter->ring_size)) {
855 dev_err(&pdev->dev, "offset(%d) > ring size(%d) !!\n",
856 offset, adapter->ring_size);
857 err = -1;
858 goto failed;
859 }
860
861 return 0;
862 failed:
863 if (adapter->ring_vir_addr != NULL) {
864 pci_free_consistent(pdev, adapter->ring_size,
865 adapter->ring_vir_addr, adapter->ring_dma);
866 adapter->ring_vir_addr = NULL;
867 }
868 return err;
869 }
870
871 static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
872 {
873
874 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
875 struct atl1e_rx_ring *rx_ring =
876 (struct atl1e_rx_ring *)&adapter->rx_ring;
877 struct atl1e_tx_ring *tx_ring =
878 (struct atl1e_tx_ring *)&adapter->tx_ring;
879 struct atl1e_rx_page_desc *rx_page_desc = NULL;
880 int i, j;
881
882 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
883 (u32)((adapter->ring_dma & AT_DMA_HI_ADDR_MASK) >> 32));
884 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
885 (u32)((tx_ring->dma) & AT_DMA_LO_ADDR_MASK));
886 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
887 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
888 (u32)((tx_ring->cmb_dma) & AT_DMA_LO_ADDR_MASK));
889
890 rx_page_desc = rx_ring->rx_page_desc;
891 /* RXF Page Physical address / Page Length */
892 for (i = 0; i < AT_MAX_RECEIVE_QUEUE; i++) {
893 AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
894 (u32)((adapter->ring_dma &
895 AT_DMA_HI_ADDR_MASK) >> 32));
896 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
897 u32 page_phy_addr;
898 u32 offset_phy_addr;
899
900 page_phy_addr = rx_page_desc[i].rx_page[j].dma;
901 offset_phy_addr =
902 rx_page_desc[i].rx_page[j].write_offset_dma;
903
904 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
905 page_phy_addr & AT_DMA_LO_ADDR_MASK);
906 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
907 offset_phy_addr & AT_DMA_LO_ADDR_MASK);
908 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
909 }
910 }
911 /* Page Length */
912 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
913 /* Load all of base address above */
914 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
915
916 return;
917 }
918
919 static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
920 {
921 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
922 u32 dev_ctrl_data = 0;
923 u32 max_pay_load = 0;
924 u32 jumbo_thresh = 0;
925 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
926
927 /* configure TXQ param */
928 if (hw->nic_type != athr_l2e_revB) {
929 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
930 if (hw->max_frame_size <= 1500) {
931 jumbo_thresh = hw->max_frame_size + extra_size;
932 } else if (hw->max_frame_size < 6*1024) {
933 jumbo_thresh =
934 (hw->max_frame_size + extra_size) * 2 / 3;
935 } else {
936 jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
937 }
938 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
939 }
940
941 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
942
943 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
944 DEVICE_CTRL_MAX_PAYLOAD_MASK;
945
946 hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
947
948 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
949 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
950 hw->dmar_block = min(max_pay_load, hw->dmar_block);
951
952 if (hw->nic_type != athr_l2e_revB)
953 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
954 atl1e_pay_load_size[hw->dmar_block]);
955 /* enable TXQ */
956 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
957 (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
958 << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
959 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
960 return;
961 }
962
963 static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
964 {
965 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
966 u32 rxf_len = 0;
967 u32 rxf_low = 0;
968 u32 rxf_high = 0;
969 u32 rxf_thresh_data = 0;
970 u32 rxq_ctrl_data = 0;
971
972 if (hw->nic_type != athr_l2e_revB) {
973 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
974 (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
975 RXQ_JMBOSZ_TH_SHIFT |
976 (1 & RXQ_JMBO_LKAH_MASK) <<
977 RXQ_JMBO_LKAH_SHIFT));
978
979 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
980 rxf_high = rxf_len * 4 / 5;
981 rxf_low = rxf_len / 5;
982 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
983 << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
984 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
985 << RXQ_RXF_PAUSE_TH_LO_SHIFT);
986
987 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
988 }
989
990 /* RRS */
991 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
992 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
993
994 if (hw->rrs_type & atl1e_rrs_ipv4)
995 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4;
996
997 if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
998 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4_TCP;
999
1000 if (hw->rrs_type & atl1e_rrs_ipv6)
1001 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6;
1002
1003 if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
1004 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6_TCP;
1005
1006 if (hw->rrs_type != atl1e_rrs_disable)
1007 rxq_ctrl_data |=
1008 (RXQ_CTRL_HASH_ENABLE | RXQ_CTRL_RSS_MODE_MQUESINT);
1009
1010 rxq_ctrl_data |= RXQ_CTRL_IPV6_XSUM_VERIFY_EN | RXQ_CTRL_PBA_ALIGN_32 |
1011 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
1012
1013 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1014 return;
1015 }
1016
1017 static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
1018 {
1019 struct atl1e_hw *hw = &adapter->hw;
1020 u32 dma_ctrl_data = 0;
1021
1022 dma_ctrl_data = DMA_CTRL_RXCMB_EN;
1023 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1024 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1025 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1026 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1027 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
1028 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1029 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1030 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1031 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1032
1033 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1034 return;
1035 }
1036
1037 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
1038 {
1039 u32 value;
1040 struct atl1e_hw *hw = &adapter->hw;
1041 struct net_device *netdev = adapter->netdev;
1042
1043 /* Config MAC CTRL Register */
1044 value = MAC_CTRL_TX_EN |
1045 MAC_CTRL_RX_EN ;
1046
1047 if (FULL_DUPLEX == adapter->link_duplex)
1048 value |= MAC_CTRL_DUPLX;
1049
1050 value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
1051 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1052 MAC_CTRL_SPEED_SHIFT);
1053 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1054
1055 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1056 value |= (((u32)adapter->hw.preamble_len &
1057 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1058
1059 if (adapter->vlgrp)
1060 value |= MAC_CTRL_RMV_VLAN;
1061
1062 value |= MAC_CTRL_BC_EN;
1063 if (netdev->flags & IFF_PROMISC)
1064 value |= MAC_CTRL_PROMIS_EN;
1065 if (netdev->flags & IFF_ALLMULTI)
1066 value |= MAC_CTRL_MC_ALL_EN;
1067
1068 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
1069 }
1070
1071 /*
1072 * atl1e_configure - Configure Transmit&Receive Unit after Reset
1073 * @adapter: board private structure
1074 *
1075 * Configure the Tx /Rx unit of the MAC after a reset.
1076 */
1077 static int atl1e_configure(struct atl1e_adapter *adapter)
1078 {
1079 struct atl1e_hw *hw = &adapter->hw;
1080 struct pci_dev *pdev = adapter->pdev;
1081
1082 u32 intr_status_data = 0;
1083
1084 /* clear interrupt status */
1085 AT_WRITE_REG(hw, REG_ISR, ~0);
1086
1087 /* 1. set MAC Address */
1088 atl1e_hw_set_mac_addr(hw);
1089
1090 /* 2. Init the Multicast HASH table done by set_muti */
1091
1092 /* 3. Clear any WOL status */
1093 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1094
1095 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
1096 * TPD Ring/SMB/RXF0 Page CMBs, they use the same
1097 * High 32bits memory */
1098 atl1e_configure_des_ring(adapter);
1099
1100 /* 5. set Interrupt Moderator Timer */
1101 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
1102 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
1103 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
1104 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
1105
1106 /* 6. rx/tx threshold to trig interrupt */
1107 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
1108 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
1109 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
1110 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
1111
1112 /* 7. set Interrupt Clear Timer */
1113 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
1114
1115 /* 8. set MTU */
1116 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1117 VLAN_HLEN + ETH_FCS_LEN);
1118
1119 /* 9. config TXQ early tx threshold */
1120 atl1e_configure_tx(adapter);
1121
1122 /* 10. config RXQ */
1123 atl1e_configure_rx(adapter);
1124
1125 /* 11. config DMA Engine */
1126 atl1e_configure_dma(adapter);
1127
1128 /* 12. smb timer to trig interrupt */
1129 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
1130
1131 intr_status_data = AT_READ_REG(hw, REG_ISR);
1132 if (unlikely((intr_status_data & ISR_PHY_LINKDOWN) != 0)) {
1133 dev_err(&pdev->dev, "atl1e_configure failed,"
1134 "PCIE phy link down\n");
1135 return -1;
1136 }
1137
1138 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
1139 return 0;
1140 }
1141
1142 /*
1143 * atl1e_get_stats - Get System Network Statistics
1144 * @netdev: network interface device structure
1145 *
1146 * Returns the address of the device statistics structure.
1147 * The statistics are actually updated from the timer callback.
1148 */
1149 static struct net_device_stats *atl1e_get_stats(struct net_device *netdev)
1150 {
1151 struct atl1e_adapter *adapter = netdev_priv(netdev);
1152 struct atl1e_hw_stats *hw_stats = &adapter->hw_stats;
1153 struct net_device_stats *net_stats = &netdev->stats;
1154
1155 net_stats->rx_packets = hw_stats->rx_ok;
1156 net_stats->tx_packets = hw_stats->tx_ok;
1157 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1158 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1159 net_stats->multicast = hw_stats->rx_mcast;
1160 net_stats->collisions = hw_stats->tx_1_col +
1161 hw_stats->tx_2_col * 2 +
1162 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1163
1164 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1165 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1166 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1167 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1168 net_stats->rx_length_errors = hw_stats->rx_len_err;
1169 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1170 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1171 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1172
1173 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1174
1175 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1176 hw_stats->tx_underrun + hw_stats->tx_trunc;
1177 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1178 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1179 net_stats->tx_window_errors = hw_stats->tx_late_col;
1180
1181 return net_stats;
1182 }
1183
1184 static void atl1e_update_hw_stats(struct atl1e_adapter *adapter)
1185 {
1186 u16 hw_reg_addr = 0;
1187 unsigned long *stats_item = NULL;
1188
1189 /* update rx status */
1190 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1191 stats_item = &adapter->hw_stats.rx_ok;
1192 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1193 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1194 stats_item++;
1195 hw_reg_addr += 4;
1196 }
1197 /* update tx status */
1198 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1199 stats_item = &adapter->hw_stats.tx_ok;
1200 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1201 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1202 stats_item++;
1203 hw_reg_addr += 4;
1204 }
1205 }
1206
1207 static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
1208 {
1209 u16 phy_data;
1210
1211 spin_lock(&adapter->mdio_lock);
1212 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
1213 spin_unlock(&adapter->mdio_lock);
1214 }
1215
1216 static bool atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
1217 {
1218 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
1219 &adapter->tx_ring;
1220 struct atl1e_tx_buffer *tx_buffer = NULL;
1221 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
1222 u16 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1223
1224 while (next_to_clean != hw_next_to_clean) {
1225 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
1226 if (tx_buffer->dma) {
1227 if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
1228 pci_unmap_single(adapter->pdev, tx_buffer->dma,
1229 tx_buffer->length, PCI_DMA_TODEVICE);
1230 else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
1231 pci_unmap_page(adapter->pdev, tx_buffer->dma,
1232 tx_buffer->length, PCI_DMA_TODEVICE);
1233 tx_buffer->dma = 0;
1234 }
1235
1236 if (tx_buffer->skb) {
1237 dev_kfree_skb_irq(tx_buffer->skb);
1238 tx_buffer->skb = NULL;
1239 }
1240
1241 if (++next_to_clean == tx_ring->count)
1242 next_to_clean = 0;
1243 }
1244
1245 atomic_set(&tx_ring->next_to_clean, next_to_clean);
1246
1247 if (netif_queue_stopped(adapter->netdev) &&
1248 netif_carrier_ok(adapter->netdev)) {
1249 netif_wake_queue(adapter->netdev);
1250 }
1251
1252 return true;
1253 }
1254
1255 /*
1256 * atl1e_intr - Interrupt Handler
1257 * @irq: interrupt number
1258 * @data: pointer to a network interface device structure
1259 * @pt_regs: CPU registers structure
1260 */
1261 static irqreturn_t atl1e_intr(int irq, void *data)
1262 {
1263 struct net_device *netdev = data;
1264 struct atl1e_adapter *adapter = netdev_priv(netdev);
1265 struct pci_dev *pdev = adapter->pdev;
1266 struct atl1e_hw *hw = &adapter->hw;
1267 int max_ints = AT_MAX_INT_WORK;
1268 int handled = IRQ_NONE;
1269 u32 status;
1270
1271 do {
1272 status = AT_READ_REG(hw, REG_ISR);
1273 if ((status & IMR_NORMAL_MASK) == 0 ||
1274 (status & ISR_DIS_INT) != 0) {
1275 if (max_ints != AT_MAX_INT_WORK)
1276 handled = IRQ_HANDLED;
1277 break;
1278 }
1279 /* link event */
1280 if (status & ISR_GPHY)
1281 atl1e_clear_phy_int(adapter);
1282 /* Ack ISR */
1283 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1284
1285 handled = IRQ_HANDLED;
1286 /* check if PCIE PHY Link down */
1287 if (status & ISR_PHY_LINKDOWN) {
1288 dev_err(&pdev->dev,
1289 "pcie phy linkdown %x\n", status);
1290 if (netif_running(adapter->netdev)) {
1291 /* reset MAC */
1292 atl1e_irq_reset(adapter);
1293 schedule_work(&adapter->reset_task);
1294 break;
1295 }
1296 }
1297
1298 /* check if DMA read/write error */
1299 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
1300 dev_err(&pdev->dev,
1301 "PCIE DMA RW error (status = 0x%x)\n",
1302 status);
1303 atl1e_irq_reset(adapter);
1304 schedule_work(&adapter->reset_task);
1305 break;
1306 }
1307
1308 if (status & ISR_SMB)
1309 atl1e_update_hw_stats(adapter);
1310
1311 /* link event */
1312 if (status & (ISR_GPHY | ISR_MANUAL)) {
1313 netdev->stats.tx_carrier_errors++;
1314 atl1e_link_chg_event(adapter);
1315 break;
1316 }
1317
1318 /* transmit event */
1319 if (status & ISR_TX_EVENT)
1320 atl1e_clean_tx_irq(adapter);
1321
1322 if (status & ISR_RX_EVENT) {
1323 /*
1324 * disable rx interrupts, without
1325 * the synchronize_irq bit
1326 */
1327 AT_WRITE_REG(hw, REG_IMR,
1328 IMR_NORMAL_MASK & ~ISR_RX_EVENT);
1329 AT_WRITE_FLUSH(hw);
1330 if (likely(napi_schedule_prep(
1331 &adapter->napi)))
1332 __napi_schedule(&adapter->napi);
1333 }
1334 } while (--max_ints > 0);
1335 /* re-enable Interrupt*/
1336 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1337
1338 return handled;
1339 }
1340
1341 static inline void atl1e_rx_checksum(struct atl1e_adapter *adapter,
1342 struct sk_buff *skb, struct atl1e_recv_ret_status *prrs)
1343 {
1344 u8 *packet = (u8 *)(prrs + 1);
1345 struct iphdr *iph;
1346 u16 head_len = ETH_HLEN;
1347 u16 pkt_flags;
1348 u16 err_flags;
1349
1350 skb->ip_summed = CHECKSUM_NONE;
1351 pkt_flags = prrs->pkt_flag;
1352 err_flags = prrs->err_flag;
1353 if (((pkt_flags & RRS_IS_IPV4) || (pkt_flags & RRS_IS_IPV6)) &&
1354 ((pkt_flags & RRS_IS_TCP) || (pkt_flags & RRS_IS_UDP))) {
1355 if (pkt_flags & RRS_IS_IPV4) {
1356 if (pkt_flags & RRS_IS_802_3)
1357 head_len += 8;
1358 iph = (struct iphdr *) (packet + head_len);
1359 if (iph->frag_off != 0 && !(pkt_flags & RRS_IS_IP_DF))
1360 goto hw_xsum;
1361 }
1362 if (!(err_flags & (RRS_ERR_IP_CSUM | RRS_ERR_L4_CSUM))) {
1363 skb->ip_summed = CHECKSUM_UNNECESSARY;
1364 return;
1365 }
1366 }
1367
1368 hw_xsum :
1369 return;
1370 }
1371
1372 static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter,
1373 u8 que)
1374 {
1375 struct atl1e_rx_page_desc *rx_page_desc =
1376 (struct atl1e_rx_page_desc *) adapter->rx_ring.rx_page_desc;
1377 u8 rx_using = rx_page_desc[que].rx_using;
1378
1379 return (struct atl1e_rx_page *)&(rx_page_desc[que].rx_page[rx_using]);
1380 }
1381
1382 static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que,
1383 int *work_done, int work_to_do)
1384 {
1385 struct pci_dev *pdev = adapter->pdev;
1386 struct net_device *netdev = adapter->netdev;
1387 struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *)
1388 &adapter->rx_ring;
1389 struct atl1e_rx_page_desc *rx_page_desc =
1390 (struct atl1e_rx_page_desc *) rx_ring->rx_page_desc;
1391 struct sk_buff *skb = NULL;
1392 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter, que);
1393 u32 packet_size, write_offset;
1394 struct atl1e_recv_ret_status *prrs;
1395
1396 write_offset = *(rx_page->write_offset_addr);
1397 if (likely(rx_page->read_offset < write_offset)) {
1398 do {
1399 if (*work_done >= work_to_do)
1400 break;
1401 (*work_done)++;
1402 /* get new packet's rrs */
1403 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
1404 rx_page->read_offset);
1405 /* check sequence number */
1406 if (prrs->seq_num != rx_page_desc[que].rx_nxseq) {
1407 dev_err(&pdev->dev,
1408 "rx sequence number"
1409 " error (rx=%d) (expect=%d)\n",
1410 prrs->seq_num,
1411 rx_page_desc[que].rx_nxseq);
1412 rx_page_desc[que].rx_nxseq++;
1413 /* just for debug use */
1414 AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
1415 (((u32)prrs->seq_num) << 16) |
1416 rx_page_desc[que].rx_nxseq);
1417 goto fatal_err;
1418 }
1419 rx_page_desc[que].rx_nxseq++;
1420
1421 /* error packet */
1422 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
1423 if (prrs->err_flag & (RRS_ERR_BAD_CRC |
1424 RRS_ERR_DRIBBLE | RRS_ERR_CODE |
1425 RRS_ERR_TRUNC)) {
1426 /* hardware error, discard this packet*/
1427 dev_err(&pdev->dev,
1428 "rx packet desc error %x\n",
1429 *((u32 *)prrs + 1));
1430 goto skip_pkt;
1431 }
1432 }
1433
1434 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1435 RRS_PKT_SIZE_MASK) - 4; /* CRC */
1436 skb = netdev_alloc_skb(netdev,
1437 packet_size + NET_IP_ALIGN);
1438 if (skb == NULL) {
1439 dev_warn(&pdev->dev, "%s: Memory squeeze,"
1440 "deferring packet.\n", netdev->name);
1441 goto skip_pkt;
1442 }
1443 skb_reserve(skb, NET_IP_ALIGN);
1444 skb->dev = netdev;
1445 memcpy(skb->data, (u8 *)(prrs + 1), packet_size);
1446 skb_put(skb, packet_size);
1447 skb->protocol = eth_type_trans(skb, netdev);
1448 atl1e_rx_checksum(adapter, skb, prrs);
1449
1450 if (unlikely(adapter->vlgrp &&
1451 (prrs->pkt_flag & RRS_IS_VLAN_TAG))) {
1452 u16 vlan_tag = (prrs->vtag >> 4) |
1453 ((prrs->vtag & 7) << 13) |
1454 ((prrs->vtag & 8) << 9);
1455 dev_dbg(&pdev->dev,
1456 "RXD VLAN TAG<RRD>=0x%04x\n",
1457 prrs->vtag);
1458 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
1459 vlan_tag);
1460 } else {
1461 netif_receive_skb(skb);
1462 }
1463
1464 skip_pkt:
1465 /* skip current packet whether it's ok or not. */
1466 rx_page->read_offset +=
1467 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1468 RRS_PKT_SIZE_MASK) +
1469 sizeof(struct atl1e_recv_ret_status) + 31) &
1470 0xFFFFFFE0);
1471
1472 if (rx_page->read_offset >= rx_ring->page_size) {
1473 /* mark this page clean */
1474 u16 reg_addr;
1475 u8 rx_using;
1476
1477 rx_page->read_offset =
1478 *(rx_page->write_offset_addr) = 0;
1479 rx_using = rx_page_desc[que].rx_using;
1480 reg_addr =
1481 atl1e_rx_page_vld_regs[que][rx_using];
1482 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
1483 rx_page_desc[que].rx_using ^= 1;
1484 rx_page = atl1e_get_rx_page(adapter, que);
1485 }
1486 write_offset = *(rx_page->write_offset_addr);
1487 } while (rx_page->read_offset < write_offset);
1488 }
1489
1490 return;
1491
1492 fatal_err:
1493 if (!test_bit(__AT_DOWN, &adapter->flags))
1494 schedule_work(&adapter->reset_task);
1495 }
1496
1497 /*
1498 * atl1e_clean - NAPI Rx polling callback
1499 * @adapter: board private structure
1500 */
1501 static int atl1e_clean(struct napi_struct *napi, int budget)
1502 {
1503 struct atl1e_adapter *adapter =
1504 container_of(napi, struct atl1e_adapter, napi);
1505 struct pci_dev *pdev = adapter->pdev;
1506 u32 imr_data;
1507 int work_done = 0;
1508
1509 /* Keep link state information with original netdev */
1510 if (!netif_carrier_ok(adapter->netdev))
1511 goto quit_polling;
1512
1513 atl1e_clean_rx_irq(adapter, 0, &work_done, budget);
1514
1515 /* If no Tx and not enough Rx work done, exit the polling mode */
1516 if (work_done < budget) {
1517 quit_polling:
1518 napi_complete(napi);
1519 imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
1520 AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
1521 /* test debug */
1522 if (test_bit(__AT_DOWN, &adapter->flags)) {
1523 atomic_dec(&adapter->irq_sem);
1524 dev_err(&pdev->dev,
1525 "atl1e_clean is called when AT_DOWN\n");
1526 }
1527 /* reenable RX intr */
1528 /*atl1e_irq_enable(adapter); */
1529
1530 }
1531 return work_done;
1532 }
1533
1534 #ifdef CONFIG_NET_POLL_CONTROLLER
1535
1536 /*
1537 * Polling 'interrupt' - used by things like netconsole to send skbs
1538 * without having to re-enable interrupts. It's not called while
1539 * the interrupt routine is executing.
1540 */
1541 static void atl1e_netpoll(struct net_device *netdev)
1542 {
1543 struct atl1e_adapter *adapter = netdev_priv(netdev);
1544
1545 disable_irq(adapter->pdev->irq);
1546 atl1e_intr(adapter->pdev->irq, netdev);
1547 enable_irq(adapter->pdev->irq);
1548 }
1549 #endif
1550
1551 static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
1552 {
1553 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1554 u16 next_to_use = 0;
1555 u16 next_to_clean = 0;
1556
1557 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1558 next_to_use = tx_ring->next_to_use;
1559
1560 return (u16)(next_to_clean > next_to_use) ?
1561 (next_to_clean - next_to_use - 1) :
1562 (tx_ring->count + next_to_clean - next_to_use - 1);
1563 }
1564
1565 /*
1566 * get next usable tpd
1567 * Note: should call atl1e_tdp_avail to make sure
1568 * there is enough tpd to use
1569 */
1570 static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
1571 {
1572 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1573 u16 next_to_use = 0;
1574
1575 next_to_use = tx_ring->next_to_use;
1576 if (++tx_ring->next_to_use == tx_ring->count)
1577 tx_ring->next_to_use = 0;
1578
1579 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
1580 return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
1581 }
1582
1583 static struct atl1e_tx_buffer *
1584 atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
1585 {
1586 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1587
1588 return &tx_ring->tx_buffer[tpd - tx_ring->desc];
1589 }
1590
1591 /* Calculate the transmit packet descript needed*/
1592 static u16 atl1e_cal_tdp_req(const struct sk_buff *skb)
1593 {
1594 int i = 0;
1595 u16 tpd_req = 1;
1596 u16 fg_size = 0;
1597 u16 proto_hdr_len = 0;
1598
1599 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1600 fg_size = skb_shinfo(skb)->frags[i].size;
1601 tpd_req += ((fg_size + MAX_TX_BUF_LEN - 1) >> MAX_TX_BUF_SHIFT);
1602 }
1603
1604 if (skb_is_gso(skb)) {
1605 if (skb->protocol == htons(ETH_P_IP) ||
1606 (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) {
1607 proto_hdr_len = skb_transport_offset(skb) +
1608 tcp_hdrlen(skb);
1609 if (proto_hdr_len < skb_headlen(skb)) {
1610 tpd_req += ((skb_headlen(skb) - proto_hdr_len +
1611 MAX_TX_BUF_LEN - 1) >>
1612 MAX_TX_BUF_SHIFT);
1613 }
1614 }
1615
1616 }
1617 return tpd_req;
1618 }
1619
1620 static int atl1e_tso_csum(struct atl1e_adapter *adapter,
1621 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1622 {
1623 struct pci_dev *pdev = adapter->pdev;
1624 u8 hdr_len;
1625 u32 real_len;
1626 unsigned short offload_type;
1627 int err;
1628
1629 if (skb_is_gso(skb)) {
1630 if (skb_header_cloned(skb)) {
1631 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1632 if (unlikely(err))
1633 return -1;
1634 }
1635 offload_type = skb_shinfo(skb)->gso_type;
1636
1637 if (offload_type & SKB_GSO_TCPV4) {
1638 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
1639 + ntohs(ip_hdr(skb)->tot_len));
1640
1641 if (real_len < skb->len)
1642 pskb_trim(skb, real_len);
1643
1644 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1645 if (unlikely(skb->len == hdr_len)) {
1646 /* only xsum need */
1647 dev_warn(&pdev->dev,
1648 "IPV4 tso with zero data??\n");
1649 goto check_sum;
1650 } else {
1651 ip_hdr(skb)->check = 0;
1652 ip_hdr(skb)->tot_len = 0;
1653 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
1654 ip_hdr(skb)->saddr,
1655 ip_hdr(skb)->daddr,
1656 0, IPPROTO_TCP, 0);
1657 tpd->word3 |= (ip_hdr(skb)->ihl &
1658 TDP_V4_IPHL_MASK) <<
1659 TPD_V4_IPHL_SHIFT;
1660 tpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
1661 TPD_TCPHDRLEN_MASK) <<
1662 TPD_TCPHDRLEN_SHIFT;
1663 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1664 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1665 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1666 }
1667 return 0;
1668 }
1669
1670 if (offload_type & SKB_GSO_TCPV6) {
1671 real_len = (((unsigned char *)ipv6_hdr(skb) - skb->data)
1672 + ntohs(ipv6_hdr(skb)->payload_len));
1673 if (real_len < skb->len)
1674 pskb_trim(skb, real_len);
1675
1676 /* check payload == 0 byte ? */
1677 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1678 if (unlikely(skb->len == hdr_len)) {
1679 /* only xsum need */
1680 dev_warn(&pdev->dev,
1681 "IPV6 tso with zero data??\n");
1682 goto check_sum;
1683 } else {
1684 tcp_hdr(skb)->check = ~csum_ipv6_magic(
1685 &ipv6_hdr(skb)->saddr,
1686 &ipv6_hdr(skb)->daddr,
1687 0, IPPROTO_TCP, 0);
1688 tpd->word3 |= 1 << TPD_IP_VERSION_SHIFT;
1689 hdr_len >>= 1;
1690 tpd->word3 |= (hdr_len & TPD_V6_IPHLLO_MASK) <<
1691 TPD_V6_IPHLLO_SHIFT;
1692 tpd->word3 |= ((hdr_len >> 3) &
1693 TPD_V6_IPHLHI_MASK) <<
1694 TPD_V6_IPHLHI_SHIFT;
1695 tpd->word3 |= (tcp_hdrlen(skb) >> 2 &
1696 TPD_TCPHDRLEN_MASK) <<
1697 TPD_TCPHDRLEN_SHIFT;
1698 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1699 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1700 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1701 }
1702 }
1703 return 0;
1704 }
1705
1706 check_sum:
1707 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1708 u8 css, cso;
1709
1710 cso = skb_transport_offset(skb);
1711 if (unlikely(cso & 0x1)) {
1712 dev_err(&adapter->pdev->dev,
1713 "pay load offset should not ant event number\n");
1714 return -1;
1715 } else {
1716 css = cso + skb->csum_offset;
1717 tpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
1718 TPD_PLOADOFFSET_SHIFT;
1719 tpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
1720 TPD_CCSUMOFFSET_SHIFT;
1721 tpd->word3 |= 1 << TPD_CC_SEGMENT_EN_SHIFT;
1722 }
1723 }
1724
1725 return 0;
1726 }
1727
1728 static void atl1e_tx_map(struct atl1e_adapter *adapter,
1729 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1730 {
1731 struct atl1e_tpd_desc *use_tpd = NULL;
1732 struct atl1e_tx_buffer *tx_buffer = NULL;
1733 u16 buf_len = skb->len - skb->data_len;
1734 u16 map_len = 0;
1735 u16 mapped_len = 0;
1736 u16 hdr_len = 0;
1737 u16 nr_frags;
1738 u16 f;
1739 int segment;
1740
1741 nr_frags = skb_shinfo(skb)->nr_frags;
1742 segment = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
1743 if (segment) {
1744 /* TSO */
1745 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1746 use_tpd = tpd;
1747
1748 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1749 tx_buffer->length = map_len;
1750 tx_buffer->dma = pci_map_single(adapter->pdev,
1751 skb->data, hdr_len, PCI_DMA_TODEVICE);
1752 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
1753 mapped_len += map_len;
1754 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1755 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1756 ((cpu_to_le32(tx_buffer->length) &
1757 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1758 }
1759
1760 while (mapped_len < buf_len) {
1761 /* mapped_len == 0, means we should use the first tpd,
1762 which is given by caller */
1763 if (mapped_len == 0) {
1764 use_tpd = tpd;
1765 } else {
1766 use_tpd = atl1e_get_tpd(adapter);
1767 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1768 }
1769 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1770 tx_buffer->skb = NULL;
1771
1772 tx_buffer->length = map_len =
1773 ((buf_len - mapped_len) >= MAX_TX_BUF_LEN) ?
1774 MAX_TX_BUF_LEN : (buf_len - mapped_len);
1775 tx_buffer->dma =
1776 pci_map_single(adapter->pdev, skb->data + mapped_len,
1777 map_len, PCI_DMA_TODEVICE);
1778 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
1779 mapped_len += map_len;
1780 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1781 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1782 ((cpu_to_le32(tx_buffer->length) &
1783 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1784 }
1785
1786 for (f = 0; f < nr_frags; f++) {
1787 struct skb_frag_struct *frag;
1788 u16 i;
1789 u16 seg_num;
1790
1791 frag = &skb_shinfo(skb)->frags[f];
1792 buf_len = frag->size;
1793
1794 seg_num = (buf_len + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1795 for (i = 0; i < seg_num; i++) {
1796 use_tpd = atl1e_get_tpd(adapter);
1797 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1798
1799 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1800 BUG_ON(tx_buffer->skb);
1801
1802 tx_buffer->skb = NULL;
1803 tx_buffer->length =
1804 (buf_len > MAX_TX_BUF_LEN) ?
1805 MAX_TX_BUF_LEN : buf_len;
1806 buf_len -= tx_buffer->length;
1807
1808 tx_buffer->dma =
1809 pci_map_page(adapter->pdev, frag->page,
1810 frag->page_offset +
1811 (i * MAX_TX_BUF_LEN),
1812 tx_buffer->length,
1813 PCI_DMA_TODEVICE);
1814 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_PAGE);
1815 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1816 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1817 ((cpu_to_le32(tx_buffer->length) &
1818 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1819 }
1820 }
1821
1822 if ((tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK)
1823 /* note this one is a tcp header */
1824 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
1825 /* The last tpd */
1826
1827 use_tpd->word3 |= 1 << TPD_EOP_SHIFT;
1828 /* The last buffer info contain the skb address,
1829 so it will be free after unmap */
1830 tx_buffer->skb = skb;
1831 }
1832
1833 static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count,
1834 struct atl1e_tpd_desc *tpd)
1835 {
1836 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1837 /* Force memory writes to complete before letting h/w
1838 * know there are new descriptors to fetch. (Only
1839 * applicable for weak-ordered memory model archs,
1840 * such as IA-64). */
1841 wmb();
1842 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
1843 }
1844
1845 static netdev_tx_t atl1e_xmit_frame(struct sk_buff *skb,
1846 struct net_device *netdev)
1847 {
1848 struct atl1e_adapter *adapter = netdev_priv(netdev);
1849 unsigned long flags;
1850 u16 tpd_req = 1;
1851 struct atl1e_tpd_desc *tpd;
1852
1853 if (test_bit(__AT_DOWN, &adapter->flags)) {
1854 dev_kfree_skb_any(skb);
1855 return NETDEV_TX_OK;
1856 }
1857
1858 if (unlikely(skb->len <= 0)) {
1859 dev_kfree_skb_any(skb);
1860 return NETDEV_TX_OK;
1861 }
1862 tpd_req = atl1e_cal_tdp_req(skb);
1863 if (!spin_trylock_irqsave(&adapter->tx_lock, flags))
1864 return NETDEV_TX_LOCKED;
1865
1866 if (atl1e_tpd_avail(adapter) < tpd_req) {
1867 /* no enough descriptor, just stop queue */
1868 netif_stop_queue(netdev);
1869 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1870 return NETDEV_TX_BUSY;
1871 }
1872
1873 tpd = atl1e_get_tpd(adapter);
1874
1875 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1876 u16 vlan_tag = vlan_tx_tag_get(skb);
1877 u16 atl1e_vlan_tag;
1878
1879 tpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
1880 AT_VLAN_TAG_TO_TPD_TAG(vlan_tag, atl1e_vlan_tag);
1881 tpd->word2 |= (atl1e_vlan_tag & TPD_VLANTAG_MASK) <<
1882 TPD_VLAN_SHIFT;
1883 }
1884
1885 if (skb->protocol == htons(ETH_P_8021Q))
1886 tpd->word3 |= 1 << TPD_VL_TAGGED_SHIFT;
1887
1888 if (skb_network_offset(skb) != ETH_HLEN)
1889 tpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; /* 802.3 frame */
1890
1891 /* do TSO and check sum */
1892 if (atl1e_tso_csum(adapter, skb, tpd) != 0) {
1893 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1894 dev_kfree_skb_any(skb);
1895 return NETDEV_TX_OK;
1896 }
1897
1898 atl1e_tx_map(adapter, skb, tpd);
1899 atl1e_tx_queue(adapter, tpd_req, tpd);
1900
1901 netdev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1902 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1903 return NETDEV_TX_OK;
1904 }
1905
1906 static void atl1e_free_irq(struct atl1e_adapter *adapter)
1907 {
1908 struct net_device *netdev = adapter->netdev;
1909
1910 free_irq(adapter->pdev->irq, netdev);
1911
1912 if (adapter->have_msi)
1913 pci_disable_msi(adapter->pdev);
1914 }
1915
1916 static int atl1e_request_irq(struct atl1e_adapter *adapter)
1917 {
1918 struct pci_dev *pdev = adapter->pdev;
1919 struct net_device *netdev = adapter->netdev;
1920 int flags = 0;
1921 int err = 0;
1922
1923 adapter->have_msi = true;
1924 err = pci_enable_msi(adapter->pdev);
1925 if (err) {
1926 dev_dbg(&pdev->dev,
1927 "Unable to allocate MSI interrupt Error: %d\n", err);
1928 adapter->have_msi = false;
1929 } else
1930 netdev->irq = pdev->irq;
1931
1932
1933 if (!adapter->have_msi)
1934 flags |= IRQF_SHARED;
1935 err = request_irq(adapter->pdev->irq, &atl1e_intr, flags,
1936 netdev->name, netdev);
1937 if (err) {
1938 dev_dbg(&pdev->dev,
1939 "Unable to allocate interrupt Error: %d\n", err);
1940 if (adapter->have_msi)
1941 pci_disable_msi(adapter->pdev);
1942 return err;
1943 }
1944 dev_dbg(&pdev->dev, "atl1e_request_irq OK\n");
1945 return err;
1946 }
1947
1948 int atl1e_up(struct atl1e_adapter *adapter)
1949 {
1950 struct net_device *netdev = adapter->netdev;
1951 int err = 0;
1952 u32 val;
1953
1954 /* hardware has been reset, we need to reload some things */
1955 err = atl1e_init_hw(&adapter->hw);
1956 if (err) {
1957 err = -EIO;
1958 return err;
1959 }
1960 atl1e_init_ring_ptrs(adapter);
1961 atl1e_set_multi(netdev);
1962 atl1e_restore_vlan(adapter);
1963
1964 if (atl1e_configure(adapter)) {
1965 err = -EIO;
1966 goto err_up;
1967 }
1968
1969 clear_bit(__AT_DOWN, &adapter->flags);
1970 napi_enable(&adapter->napi);
1971 atl1e_irq_enable(adapter);
1972 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1973 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1974 val | MASTER_CTRL_MANUAL_INT);
1975
1976 err_up:
1977 return err;
1978 }
1979
1980 void atl1e_down(struct atl1e_adapter *adapter)
1981 {
1982 struct net_device *netdev = adapter->netdev;
1983
1984 /* signal that we're down so the interrupt handler does not
1985 * reschedule our watchdog timer */
1986 set_bit(__AT_DOWN, &adapter->flags);
1987
1988 #ifdef NETIF_F_LLTX
1989 netif_stop_queue(netdev);
1990 #else
1991 netif_tx_disable(netdev);
1992 #endif
1993
1994 /* reset MAC to disable all RX/TX */
1995 atl1e_reset_hw(&adapter->hw);
1996 msleep(1);
1997
1998 napi_disable(&adapter->napi);
1999 atl1e_del_timer(adapter);
2000 atl1e_irq_disable(adapter);
2001
2002 netif_carrier_off(netdev);
2003 adapter->link_speed = SPEED_0;
2004 adapter->link_duplex = -1;
2005 atl1e_clean_tx_ring(adapter);
2006 atl1e_clean_rx_ring(adapter);
2007 }
2008
2009 /*
2010 * atl1e_open - Called when a network interface is made active
2011 * @netdev: network interface device structure
2012 *
2013 * Returns 0 on success, negative value on failure
2014 *
2015 * The open entry point is called when a network interface is made
2016 * active by the system (IFF_UP). At this point all resources needed
2017 * for transmit and receive operations are allocated, the interrupt
2018 * handler is registered with the OS, the watchdog timer is started,
2019 * and the stack is notified that the interface is ready.
2020 */
2021 static int atl1e_open(struct net_device *netdev)
2022 {
2023 struct atl1e_adapter *adapter = netdev_priv(netdev);
2024 int err;
2025
2026 /* disallow open during test */
2027 if (test_bit(__AT_TESTING, &adapter->flags))
2028 return -EBUSY;
2029
2030 /* allocate rx/tx dma buffer & descriptors */
2031 atl1e_init_ring_resources(adapter);
2032 err = atl1e_setup_ring_resources(adapter);
2033 if (unlikely(err))
2034 return err;
2035
2036 err = atl1e_request_irq(adapter);
2037 if (unlikely(err))
2038 goto err_req_irq;
2039
2040 err = atl1e_up(adapter);
2041 if (unlikely(err))
2042 goto err_up;
2043
2044 return 0;
2045
2046 err_up:
2047 atl1e_free_irq(adapter);
2048 err_req_irq:
2049 atl1e_free_ring_resources(adapter);
2050 atl1e_reset_hw(&adapter->hw);
2051
2052 return err;
2053 }
2054
2055 /*
2056 * atl1e_close - Disables a network interface
2057 * @netdev: network interface device structure
2058 *
2059 * Returns 0, this is not allowed to fail
2060 *
2061 * The close entry point is called when an interface is de-activated
2062 * by the OS. The hardware is still under the drivers control, but
2063 * needs to be disabled. A global MAC reset is issued to stop the
2064 * hardware, and all transmit and receive resources are freed.
2065 */
2066 static int atl1e_close(struct net_device *netdev)
2067 {
2068 struct atl1e_adapter *adapter = netdev_priv(netdev);
2069
2070 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2071 atl1e_down(adapter);
2072 atl1e_free_irq(adapter);
2073 atl1e_free_ring_resources(adapter);
2074
2075 return 0;
2076 }
2077
2078 static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
2079 {
2080 struct net_device *netdev = pci_get_drvdata(pdev);
2081 struct atl1e_adapter *adapter = netdev_priv(netdev);
2082 struct atl1e_hw *hw = &adapter->hw;
2083 u32 ctrl = 0;
2084 u32 mac_ctrl_data = 0;
2085 u32 wol_ctrl_data = 0;
2086 u16 mii_advertise_data = 0;
2087 u16 mii_bmsr_data = 0;
2088 u16 mii_intr_status_data = 0;
2089 u32 wufc = adapter->wol;
2090 u32 i;
2091 #ifdef CONFIG_PM
2092 int retval = 0;
2093 #endif
2094
2095 if (netif_running(netdev)) {
2096 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2097 atl1e_down(adapter);
2098 }
2099 netif_device_detach(netdev);
2100
2101 #ifdef CONFIG_PM
2102 retval = pci_save_state(pdev);
2103 if (retval)
2104 return retval;
2105 #endif
2106
2107 if (wufc) {
2108 /* get link status */
2109 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2110 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2111
2112 mii_advertise_data = MII_AR_10T_HD_CAPS;
2113
2114 if ((atl1e_write_phy_reg(hw, MII_AT001_CR, 0) != 0) ||
2115 (atl1e_write_phy_reg(hw,
2116 MII_ADVERTISE, mii_advertise_data) != 0) ||
2117 (atl1e_phy_commit(hw)) != 0) {
2118 dev_dbg(&pdev->dev, "set phy register failed\n");
2119 goto wol_dis;
2120 }
2121
2122 hw->phy_configured = false; /* re-init PHY when resume */
2123
2124 /* turn on magic packet wol */
2125 if (wufc & AT_WUFC_MAG)
2126 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2127
2128 if (wufc & AT_WUFC_LNKC) {
2129 /* if orignal link status is link, just wait for retrive link */
2130 if (mii_bmsr_data & BMSR_LSTATUS) {
2131 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
2132 msleep(100);
2133 atl1e_read_phy_reg(hw, MII_BMSR,
2134 (u16 *)&mii_bmsr_data);
2135 if (mii_bmsr_data & BMSR_LSTATUS)
2136 break;
2137 }
2138
2139 if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
2140 dev_dbg(&pdev->dev,
2141 "%s: Link may change"
2142 "when suspend\n",
2143 atl1e_driver_name);
2144 }
2145 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2146 /* only link up can wake up */
2147 if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
2148 dev_dbg(&pdev->dev, "%s: read write phy "
2149 "register failed.\n",
2150 atl1e_driver_name);
2151 goto wol_dis;
2152 }
2153 }
2154 /* clear phy interrupt */
2155 atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
2156 /* Config MAC Ctrl register */
2157 mac_ctrl_data = MAC_CTRL_RX_EN;
2158 /* set to 10/100M halt duplex */
2159 mac_ctrl_data |= MAC_CTRL_SPEED_10_100 << MAC_CTRL_SPEED_SHIFT;
2160 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2161 MAC_CTRL_PRMLEN_MASK) <<
2162 MAC_CTRL_PRMLEN_SHIFT);
2163
2164 if (adapter->vlgrp)
2165 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
2166
2167 /* magic packet maybe Broadcast&multicast&Unicast frame */
2168 if (wufc & AT_WUFC_MAG)
2169 mac_ctrl_data |= MAC_CTRL_BC_EN;
2170
2171 dev_dbg(&pdev->dev,
2172 "%s: suspend MAC=0x%x\n",
2173 atl1e_driver_name, mac_ctrl_data);
2174
2175 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2176 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2177 /* pcie patch */
2178 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2179 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2180 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2181 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2182 goto suspend_exit;
2183 }
2184 wol_dis:
2185
2186 /* WOL disabled */
2187 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2188
2189 /* pcie patch */
2190 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2191 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2192 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2193
2194 atl1e_force_ps(hw);
2195 hw->phy_configured = false; /* re-init PHY when resume */
2196
2197 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2198
2199 suspend_exit:
2200
2201 if (netif_running(netdev))
2202 atl1e_free_irq(adapter);
2203
2204 pci_disable_device(pdev);
2205
2206 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2207
2208 return 0;
2209 }
2210
2211 #ifdef CONFIG_PM
2212 static int atl1e_resume(struct pci_dev *pdev)
2213 {
2214 struct net_device *netdev = pci_get_drvdata(pdev);
2215 struct atl1e_adapter *adapter = netdev_priv(netdev);
2216 u32 err;
2217
2218 pci_set_power_state(pdev, PCI_D0);
2219 pci_restore_state(pdev);
2220
2221 err = pci_enable_device(pdev);
2222 if (err) {
2223 dev_err(&pdev->dev, "ATL1e: Cannot enable PCI"
2224 " device from suspend\n");
2225 return err;
2226 }
2227
2228 pci_set_master(pdev);
2229
2230 AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
2231
2232 pci_enable_wake(pdev, PCI_D3hot, 0);
2233 pci_enable_wake(pdev, PCI_D3cold, 0);
2234
2235 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2236
2237 if (netif_running(netdev)) {
2238 err = atl1e_request_irq(adapter);
2239 if (err)
2240 return err;
2241 }
2242
2243 atl1e_reset_hw(&adapter->hw);
2244
2245 if (netif_running(netdev))
2246 atl1e_up(adapter);
2247
2248 netif_device_attach(netdev);
2249
2250 return 0;
2251 }
2252 #endif
2253
2254 static void atl1e_shutdown(struct pci_dev *pdev)
2255 {
2256 atl1e_suspend(pdev, PMSG_SUSPEND);
2257 }
2258
2259 static const struct net_device_ops atl1e_netdev_ops = {
2260 .ndo_open = atl1e_open,
2261 .ndo_stop = atl1e_close,
2262 .ndo_start_xmit = atl1e_xmit_frame,
2263 .ndo_get_stats = atl1e_get_stats,
2264 .ndo_set_multicast_list = atl1e_set_multi,
2265 .ndo_validate_addr = eth_validate_addr,
2266 .ndo_set_mac_address = atl1e_set_mac_addr,
2267 .ndo_change_mtu = atl1e_change_mtu,
2268 .ndo_do_ioctl = atl1e_ioctl,
2269 .ndo_tx_timeout = atl1e_tx_timeout,
2270 .ndo_vlan_rx_register = atl1e_vlan_rx_register,
2271 #ifdef CONFIG_NET_POLL_CONTROLLER
2272 .ndo_poll_controller = atl1e_netpoll,
2273 #endif
2274
2275 };
2276
2277 static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2278 {
2279 SET_NETDEV_DEV(netdev, &pdev->dev);
2280 pci_set_drvdata(pdev, netdev);
2281
2282 netdev->irq = pdev->irq;
2283 netdev->netdev_ops = &atl1e_netdev_ops;
2284
2285 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2286 atl1e_set_ethtool_ops(netdev);
2287
2288 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM |
2289 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2290 netdev->features |= NETIF_F_LLTX;
2291 netdev->features |= NETIF_F_TSO;
2292 netdev->features |= NETIF_F_TSO6;
2293
2294 return 0;
2295 }
2296
2297 /*
2298 * atl1e_probe - Device Initialization Routine
2299 * @pdev: PCI device information struct
2300 * @ent: entry in atl1e_pci_tbl
2301 *
2302 * Returns 0 on success, negative on failure
2303 *
2304 * atl1e_probe initializes an adapter identified by a pci_dev structure.
2305 * The OS initialization, configuring of the adapter private structure,
2306 * and a hardware reset occur.
2307 */
2308 static int __devinit atl1e_probe(struct pci_dev *pdev,
2309 const struct pci_device_id *ent)
2310 {
2311 struct net_device *netdev;
2312 struct atl1e_adapter *adapter = NULL;
2313 static int cards_found;
2314
2315 int err = 0;
2316
2317 err = pci_enable_device(pdev);
2318 if (err) {
2319 dev_err(&pdev->dev, "cannot enable PCI device\n");
2320 return err;
2321 }
2322
2323 /*
2324 * The atl1e chip can DMA to 64-bit addresses, but it uses a single
2325 * shared register for the high 32 bits, so only a single, aligned,
2326 * 4 GB physical address range can be used at a time.
2327 *
2328 * Supporting 64-bit DMA on this hardware is more trouble than it's
2329 * worth. It is far easier to limit to 32-bit DMA than update
2330 * various kernel subsystems to support the mechanics required by a
2331 * fixed-high-32-bit system.
2332 */
2333 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2334 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2335 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2336 goto err_dma;
2337 }
2338
2339 err = pci_request_regions(pdev, atl1e_driver_name);
2340 if (err) {
2341 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2342 goto err_pci_reg;
2343 }
2344
2345 pci_set_master(pdev);
2346
2347 netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
2348 if (netdev == NULL) {
2349 err = -ENOMEM;
2350 dev_err(&pdev->dev, "etherdev alloc failed\n");
2351 goto err_alloc_etherdev;
2352 }
2353
2354 err = atl1e_init_netdev(netdev, pdev);
2355 if (err) {
2356 dev_err(&pdev->dev, "init netdevice failed\n");
2357 goto err_init_netdev;
2358 }
2359 adapter = netdev_priv(netdev);
2360 adapter->bd_number = cards_found;
2361 adapter->netdev = netdev;
2362 adapter->pdev = pdev;
2363 adapter->hw.adapter = adapter;
2364 adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
2365 if (!adapter->hw.hw_addr) {
2366 err = -EIO;
2367 dev_err(&pdev->dev, "cannot map device registers\n");
2368 goto err_ioremap;
2369 }
2370 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2371
2372 /* init mii data */
2373 adapter->mii.dev = netdev;
2374 adapter->mii.mdio_read = atl1e_mdio_read;
2375 adapter->mii.mdio_write = atl1e_mdio_write;
2376 adapter->mii.phy_id_mask = 0x1f;
2377 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2378
2379 netif_napi_add(netdev, &adapter->napi, atl1e_clean, 64);
2380
2381 init_timer(&adapter->phy_config_timer);
2382 adapter->phy_config_timer.function = &atl1e_phy_config;
2383 adapter->phy_config_timer.data = (unsigned long) adapter;
2384
2385 /* get user settings */
2386 atl1e_check_options(adapter);
2387 /*
2388 * Mark all PCI regions associated with PCI device
2389 * pdev as being reserved by owner atl1e_driver_name
2390 * Enables bus-mastering on the device and calls
2391 * pcibios_set_master to do the needed arch specific settings
2392 */
2393 atl1e_setup_pcicmd(pdev);
2394 /* setup the private structure */
2395 err = atl1e_sw_init(adapter);
2396 if (err) {
2397 dev_err(&pdev->dev, "net device private data init failed\n");
2398 goto err_sw_init;
2399 }
2400
2401 /* Init GPHY as early as possible due to power saving issue */
2402 atl1e_phy_init(&adapter->hw);
2403 /* reset the controller to
2404 * put the device in a known good starting state */
2405 err = atl1e_reset_hw(&adapter->hw);
2406 if (err) {
2407 err = -EIO;
2408 goto err_reset;
2409 }
2410
2411 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
2412 err = -EIO;
2413 dev_err(&pdev->dev, "get mac address failed\n");
2414 goto err_eeprom;
2415 }
2416
2417 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2418 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2419 dev_dbg(&pdev->dev, "mac address : %02x-%02x-%02x-%02x-%02x-%02x\n",
2420 adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
2421 adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
2422 adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
2423
2424 INIT_WORK(&adapter->reset_task, atl1e_reset_task);
2425 INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
2426 err = register_netdev(netdev);
2427 if (err) {
2428 dev_err(&pdev->dev, "register netdevice failed\n");
2429 goto err_register;
2430 }
2431
2432 /* assume we have no link for now */
2433 netif_stop_queue(netdev);
2434 netif_carrier_off(netdev);
2435
2436 cards_found++;
2437
2438 return 0;
2439
2440 err_reset:
2441 err_register:
2442 err_sw_init:
2443 err_eeprom:
2444 iounmap(adapter->hw.hw_addr);
2445 err_init_netdev:
2446 err_ioremap:
2447 free_netdev(netdev);
2448 err_alloc_etherdev:
2449 pci_release_regions(pdev);
2450 err_pci_reg:
2451 err_dma:
2452 pci_disable_device(pdev);
2453 return err;
2454 }
2455
2456 /*
2457 * atl1e_remove - Device Removal Routine
2458 * @pdev: PCI device information struct
2459 *
2460 * atl1e_remove is called by the PCI subsystem to alert the driver
2461 * that it should release a PCI device. The could be caused by a
2462 * Hot-Plug event, or because the driver is going to be removed from
2463 * memory.
2464 */
2465 static void __devexit atl1e_remove(struct pci_dev *pdev)
2466 {
2467 struct net_device *netdev = pci_get_drvdata(pdev);
2468 struct atl1e_adapter *adapter = netdev_priv(netdev);
2469
2470 /*
2471 * flush_scheduled work may reschedule our watchdog task, so
2472 * explicitly disable watchdog tasks from being rescheduled
2473 */
2474 set_bit(__AT_DOWN, &adapter->flags);
2475
2476 atl1e_del_timer(adapter);
2477 atl1e_cancel_work(adapter);
2478
2479 unregister_netdev(netdev);
2480 atl1e_free_ring_resources(adapter);
2481 atl1e_force_ps(&adapter->hw);
2482 iounmap(adapter->hw.hw_addr);
2483 pci_release_regions(pdev);
2484 free_netdev(netdev);
2485 pci_disable_device(pdev);
2486 }
2487
2488 /*
2489 * atl1e_io_error_detected - called when PCI error is detected
2490 * @pdev: Pointer to PCI device
2491 * @state: The current pci connection state
2492 *
2493 * This function is called after a PCI bus error affecting
2494 * this device has been detected.
2495 */
2496 static pci_ers_result_t
2497 atl1e_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2498 {
2499 struct net_device *netdev = pci_get_drvdata(pdev);
2500 struct atl1e_adapter *adapter = netdev_priv(netdev);
2501
2502 netif_device_detach(netdev);
2503
2504 if (state == pci_channel_io_perm_failure)
2505 return PCI_ERS_RESULT_DISCONNECT;
2506
2507 if (netif_running(netdev))
2508 atl1e_down(adapter);
2509
2510 pci_disable_device(pdev);
2511
2512 /* Request a slot slot reset. */
2513 return PCI_ERS_RESULT_NEED_RESET;
2514 }
2515
2516 /*
2517 * atl1e_io_slot_reset - called after the pci bus has been reset.
2518 * @pdev: Pointer to PCI device
2519 *
2520 * Restart the card from scratch, as if from a cold-boot. Implementation
2521 * resembles the first-half of the e1000_resume routine.
2522 */
2523 static pci_ers_result_t atl1e_io_slot_reset(struct pci_dev *pdev)
2524 {
2525 struct net_device *netdev = pci_get_drvdata(pdev);
2526 struct atl1e_adapter *adapter = netdev_priv(netdev);
2527
2528 if (pci_enable_device(pdev)) {
2529 dev_err(&pdev->dev,
2530 "ATL1e: Cannot re-enable PCI device after reset.\n");
2531 return PCI_ERS_RESULT_DISCONNECT;
2532 }
2533 pci_set_master(pdev);
2534
2535 pci_enable_wake(pdev, PCI_D3hot, 0);
2536 pci_enable_wake(pdev, PCI_D3cold, 0);
2537
2538 atl1e_reset_hw(&adapter->hw);
2539
2540 return PCI_ERS_RESULT_RECOVERED;
2541 }
2542
2543 /*
2544 * atl1e_io_resume - called when traffic can start flowing again.
2545 * @pdev: Pointer to PCI device
2546 *
2547 * This callback is called when the error recovery driver tells us that
2548 * its OK to resume normal operation. Implementation resembles the
2549 * second-half of the atl1e_resume routine.
2550 */
2551 static void atl1e_io_resume(struct pci_dev *pdev)
2552 {
2553 struct net_device *netdev = pci_get_drvdata(pdev);
2554 struct atl1e_adapter *adapter = netdev_priv(netdev);
2555
2556 if (netif_running(netdev)) {
2557 if (atl1e_up(adapter)) {
2558 dev_err(&pdev->dev,
2559 "ATL1e: can't bring device back up after reset\n");
2560 return;
2561 }
2562 }
2563
2564 netif_device_attach(netdev);
2565 }
2566
2567 static struct pci_error_handlers atl1e_err_handler = {
2568 .error_detected = atl1e_io_error_detected,
2569 .slot_reset = atl1e_io_slot_reset,
2570 .resume = atl1e_io_resume,
2571 };
2572
2573 static struct pci_driver atl1e_driver = {
2574 .name = atl1e_driver_name,
2575 .id_table = atl1e_pci_tbl,
2576 .probe = atl1e_probe,
2577 .remove = __devexit_p(atl1e_remove),
2578 /* Power Managment Hooks */
2579 #ifdef CONFIG_PM
2580 .suspend = atl1e_suspend,
2581 .resume = atl1e_resume,
2582 #endif
2583 .shutdown = atl1e_shutdown,
2584 .err_handler = &atl1e_err_handler
2585 };
2586
2587 /*
2588 * atl1e_init_module - Driver Registration Routine
2589 *
2590 * atl1e_init_module is the first routine called when the driver is
2591 * loaded. All it does is register with the PCI subsystem.
2592 */
2593 static int __init atl1e_init_module(void)
2594 {
2595 return pci_register_driver(&atl1e_driver);
2596 }
2597
2598 /*
2599 * atl1e_exit_module - Driver Exit Cleanup Routine
2600 *
2601 * atl1e_exit_module is called just before the driver is removed
2602 * from memory.
2603 */
2604 static void __exit atl1e_exit_module(void)
2605 {
2606 pci_unregister_driver(&atl1e_driver);
2607 }
2608
2609 module_init(atl1e_init_module);
2610 module_exit(atl1e_exit_module);
Linux for Ginger Game Console