?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Save sram context after changing MPU, DSP or core clocks
[linux-ginger.git] / drivers / net / wan / hd64570.c
blob80114c93bae74c52db4d53c32f3681938022c49d
1 /*
2 * Hitachi SCA HD64570 driver for Linux
3 *
4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * Source of information: Hitachi HD64570 SCA User's Manual
11 *
12 * We use the following SCA memory map:
13 *
14 * Packet buffer descriptor rings - starting from winbase or win0base:
15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
19 *
20 * Packet data buffers - starting from winbase + buff_offset:
21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
25 */
26
27 #include <linux/bitops.h>
28 #include <linux/errno.h>
29 #include <linux/fcntl.h>
30 #include <linux/hdlc.h>
31 #include <linux/in.h>
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/jiffies.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/netdevice.h>
39 #include <linux/skbuff.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/types.h>
43 #include <asm/io.h>
44 #include <asm/system.h>
45 #include <asm/uaccess.h>
46 #include "hd64570.h"
47
48 #define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
49 #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
50 #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
51
52 #define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
53 #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
54 #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
55
56
57 static inline struct net_device *port_to_dev(port_t *port)
58 {
59 return port->dev;
60 }
61
62 static inline int sca_intr_status(card_t *card)
63 {
64 u8 result = 0;
65 u8 isr0 = sca_in(ISR0, card);
66 u8 isr1 = sca_in(ISR1, card);
67
68 if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
69 if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
70 if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
71 if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
72 if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
73 if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
74
75 if (!(result & SCA_INTR_DMAC_TX(0)))
76 if (sca_in(DSR_TX(0), card) & DSR_EOM)
77 result |= SCA_INTR_DMAC_TX(0);
78 if (!(result & SCA_INTR_DMAC_TX(1)))
79 if (sca_in(DSR_TX(1), card) & DSR_EOM)
80 result |= SCA_INTR_DMAC_TX(1);
81
82 return result;
83 }
84
85 static inline port_t* dev_to_port(struct net_device *dev)
86 {
87 return dev_to_hdlc(dev)->priv;
88 }
89
90 static inline u16 next_desc(port_t *port, u16 desc, int transmit)
91 {
92 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
93 : port_to_card(port)->rx_ring_buffers);
94 }
95
96
97 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
98 {
99 u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
100 u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
101
102 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
103 return log_node(port) * (rx_buffs + tx_buffs) +
104 transmit * rx_buffs + desc;
105 }
106
107
108 static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
109 {
110 /* Descriptor offset always fits in 16 bits */
111 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
112 }
113
114
115 static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
116 int transmit)
117 {
118 #ifdef PAGE0_ALWAYS_MAPPED
119 return (pkt_desc __iomem *)(win0base(port_to_card(port))
120 + desc_offset(port, desc, transmit));
121 #else
122 return (pkt_desc __iomem *)(winbase(port_to_card(port))
123 + desc_offset(port, desc, transmit));
124 #endif
125 }
126
127
128 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
129 {
130 return port_to_card(port)->buff_offset +
131 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
132 }
133
134
135 static inline void sca_set_carrier(port_t *port)
136 {
137 if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
138 #ifdef DEBUG_LINK
139 printk(KERN_DEBUG "%s: sca_set_carrier on\n",
140 port_to_dev(port)->name);
141 #endif
142 netif_carrier_on(port_to_dev(port));
143 } else {
144 #ifdef DEBUG_LINK
145 printk(KERN_DEBUG "%s: sca_set_carrier off\n",
146 port_to_dev(port)->name);
147 #endif
148 netif_carrier_off(port_to_dev(port));
149 }
150 }
151
152
153 static void sca_init_port(port_t *port)
154 {
155 card_t *card = port_to_card(port);
156 int transmit, i;
157
158 port->rxin = 0;
159 port->txin = 0;
160 port->txlast = 0;
161
162 #ifndef PAGE0_ALWAYS_MAPPED
163 openwin(card, 0);
164 #endif
165
166 for (transmit = 0; transmit < 2; transmit++) {
167 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
168 u16 buffs = transmit ? card->tx_ring_buffers
169 : card->rx_ring_buffers;
170
171 for (i = 0; i < buffs; i++) {
172 pkt_desc __iomem *desc = desc_address(port, i, transmit);
173 u16 chain_off = desc_offset(port, i + 1, transmit);
174 u32 buff_off = buffer_offset(port, i, transmit);
175
176 writew(chain_off, &desc->cp);
177 writel(buff_off, &desc->bp);
178 writew(0, &desc->len);
179 writeb(0, &desc->stat);
180 }
181
182 /* DMA disable - to halt state */
183 sca_out(0, transmit ? DSR_TX(phy_node(port)) :
184 DSR_RX(phy_node(port)), card);
185 /* software ABORT - to initial state */
186 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
187 DCR_RX(phy_node(port)), card);
188
189 /* current desc addr */
190 sca_out(0, dmac + CPB, card); /* pointer base */
191 sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
192 if (!transmit)
193 sca_outw(desc_offset(port, buffs - 1, transmit),
194 dmac + EDAL, card);
195 else
196 sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
197 card);
198
199 /* clear frame end interrupt counter */
200 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
201 DCR_RX(phy_node(port)), card);
202
203 if (!transmit) { /* Receive */
204 /* set buffer length */
205 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
206 /* Chain mode, Multi-frame */
207 sca_out(0x14, DMR_RX(phy_node(port)), card);
208 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
209 card);
210 /* DMA enable */
211 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
212 } else { /* Transmit */
213 /* Chain mode, Multi-frame */
214 sca_out(0x14, DMR_TX(phy_node(port)), card);
215 /* enable underflow interrupts */
216 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
217 }
218 }
219 sca_set_carrier(port);
220 }
221
222
223 #ifdef NEED_SCA_MSCI_INTR
224 /* MSCI interrupt service */
225 static inline void sca_msci_intr(port_t *port)
226 {
227 u16 msci = get_msci(port);
228 card_t* card = port_to_card(port);
229 u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
230
231 /* Reset MSCI TX underrun and CDCD status bit */
232 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
233
234 if (stat & ST1_UDRN) {
235 /* TX Underrun error detected */
236 port_to_dev(port)->stats.tx_errors++;
237 port_to_dev(port)->stats.tx_fifo_errors++;
238 }
239
240 if (stat & ST1_CDCD)
241 sca_set_carrier(port);
242 }
243 #endif
244
245
246 static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
247 u16 rxin)
248 {
249 struct net_device *dev = port_to_dev(port);
250 struct sk_buff *skb;
251 u16 len;
252 u32 buff;
253 u32 maxlen;
254 u8 page;
255
256 len = readw(&desc->len);
257 skb = dev_alloc_skb(len);
258 if (!skb) {
259 dev->stats.rx_dropped++;
260 return;
261 }
262
263 buff = buffer_offset(port, rxin, 0);
264 page = buff / winsize(card);
265 buff = buff % winsize(card);
266 maxlen = winsize(card) - buff;
267
268 openwin(card, page);
269
270 if (len > maxlen) {
271 memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
272 openwin(card, page + 1);
273 memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
274 } else
275 memcpy_fromio(skb->data, winbase(card) + buff, len);
276
277 #ifndef PAGE0_ALWAYS_MAPPED
278 openwin(card, 0); /* select pkt_desc table page back */
279 #endif
280 skb_put(skb, len);
281 #ifdef DEBUG_PKT
282 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
283 debug_frame(skb);
284 #endif
285 dev->stats.rx_packets++;
286 dev->stats.rx_bytes += skb->len;
287 skb->protocol = hdlc_type_trans(skb, dev);
288 netif_rx(skb);
289 }
290
291
292 /* Receive DMA interrupt service */
293 static inline void sca_rx_intr(port_t *port)
294 {
295 struct net_device *dev = port_to_dev(port);
296 u16 dmac = get_dmac_rx(port);
297 card_t *card = port_to_card(port);
298 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
299
300 /* Reset DSR status bits */
301 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
302 DSR_RX(phy_node(port)), card);
303
304 if (stat & DSR_BOF)
305 /* Dropped one or more frames */
306 dev->stats.rx_over_errors++;
307
308 while (1) {
309 u32 desc_off = desc_offset(port, port->rxin, 0);
310 pkt_desc __iomem *desc;
311 u32 cda = sca_inw(dmac + CDAL, card);
312
313 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
314 break; /* No frame received */
315
316 desc = desc_address(port, port->rxin, 0);
317 stat = readb(&desc->stat);
318 if (!(stat & ST_RX_EOM))
319 port->rxpart = 1; /* partial frame received */
320 else if ((stat & ST_ERROR_MASK) || port->rxpart) {
321 dev->stats.rx_errors++;
322 if (stat & ST_RX_OVERRUN)
323 dev->stats.rx_fifo_errors++;
324 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
325 ST_RX_RESBIT)) || port->rxpart)
326 dev->stats.rx_frame_errors++;
327 else if (stat & ST_RX_CRC)
328 dev->stats.rx_crc_errors++;
329 if (stat & ST_RX_EOM)
330 port->rxpart = 0; /* received last fragment */
331 } else
332 sca_rx(card, port, desc, port->rxin);
333
334 /* Set new error descriptor address */
335 sca_outw(desc_off, dmac + EDAL, card);
336 port->rxin = next_desc(port, port->rxin, 0);
337 }
338
339 /* make sure RX DMA is enabled */
340 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
341 }
342
343
344 /* Transmit DMA interrupt service */
345 static inline void sca_tx_intr(port_t *port)
346 {
347 struct net_device *dev = port_to_dev(port);
348 u16 dmac = get_dmac_tx(port);
349 card_t* card = port_to_card(port);
350 u8 stat;
351
352 spin_lock(&port->lock);
353
354 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
355
356 /* Reset DSR status bits */
357 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
358 DSR_TX(phy_node(port)), card);
359
360 while (1) {
361 pkt_desc __iomem *desc;
362
363 u32 desc_off = desc_offset(port, port->txlast, 1);
364 u32 cda = sca_inw(dmac + CDAL, card);
365 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
366 break; /* Transmitter is/will_be sending this frame */
367
368 desc = desc_address(port, port->txlast, 1);
369 dev->stats.tx_packets++;
370 dev->stats.tx_bytes += readw(&desc->len);
371 writeb(0, &desc->stat); /* Free descriptor */
372 port->txlast = next_desc(port, port->txlast, 1);
373 }
374
375 netif_wake_queue(dev);
376 spin_unlock(&port->lock);
377 }
378
379
380 static irqreturn_t sca_intr(int irq, void* dev_id)
381 {
382 card_t *card = dev_id;
383 int i;
384 u8 stat;
385 int handled = 0;
386 u8 page = sca_get_page(card);
387
388 while((stat = sca_intr_status(card)) != 0) {
389 handled = 1;
390 for (i = 0; i < 2; i++) {
391 port_t *port = get_port(card, i);
392 if (port) {
393 if (stat & SCA_INTR_MSCI(i))
394 sca_msci_intr(port);
395
396 if (stat & SCA_INTR_DMAC_RX(i))
397 sca_rx_intr(port);
398
399 if (stat & SCA_INTR_DMAC_TX(i))
400 sca_tx_intr(port);
401 }
402 }
403 }
404
405 openwin(card, page); /* Restore original page */
406 return IRQ_RETVAL(handled);
407 }
408
409
410 static void sca_set_port(port_t *port)
411 {
412 card_t* card = port_to_card(port);
413 u16 msci = get_msci(port);
414 u8 md2 = sca_in(msci + MD2, card);
415 unsigned int tmc, br = 10, brv = 1024;
416
417
418 if (port->settings.clock_rate > 0) {
419 /* Try lower br for better accuracy*/
420 do {
421 br--;
422 brv >>= 1; /* brv = 2^9 = 512 max in specs */
423
424 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
425 tmc = CLOCK_BASE / brv / port->settings.clock_rate;
426 }while (br > 1 && tmc <= 128);
427
428 if (tmc < 1) {
429 tmc = 1;
430 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
431 brv = 1;
432 } else if (tmc > 255)
433 tmc = 256; /* tmc=0 means 256 - low baud rates */
434
435 port->settings.clock_rate = CLOCK_BASE / brv / tmc;
436 } else {
437 br = 9; /* Minimum clock rate */
438 tmc = 256; /* 8bit = 0 */
439 port->settings.clock_rate = CLOCK_BASE / (256 * 512);
440 }
441
442 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
443 port->txs = (port->txs & ~CLK_BRG_MASK) | br;
444 port->tmc = tmc;
445
446 /* baud divisor - time constant*/
447 sca_out(port->tmc, msci + TMC, card);
448
449 /* Set BRG bits */
450 sca_out(port->rxs, msci + RXS, card);
451 sca_out(port->txs, msci + TXS, card);
452
453 if (port->settings.loopback)
454 md2 |= MD2_LOOPBACK;
455 else
456 md2 &= ~MD2_LOOPBACK;
457
458 sca_out(md2, msci + MD2, card);
459
460 }
461
462
463 static void sca_open(struct net_device *dev)
464 {
465 port_t *port = dev_to_port(dev);
466 card_t* card = port_to_card(port);
467 u16 msci = get_msci(port);
468 u8 md0, md2;
469
470 switch(port->encoding) {
471 case ENCODING_NRZ: md2 = MD2_NRZ; break;
472 case ENCODING_NRZI: md2 = MD2_NRZI; break;
473 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
474 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
475 default: md2 = MD2_MANCHESTER;
476 }
477
478 if (port->settings.loopback)
479 md2 |= MD2_LOOPBACK;
480
481 switch(port->parity) {
482 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
483 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
484 case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
485 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
486 default: md0 = MD0_HDLC | MD0_CRC_NONE;
487 }
488
489 sca_out(CMD_RESET, msci + CMD, card);
490 sca_out(md0, msci + MD0, card);
491 sca_out(0x00, msci + MD1, card); /* no address field check */
492 sca_out(md2, msci + MD2, card);
493 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
494 sca_out(CTL_IDLE, msci + CTL, card);
495
496 /* Allow at least 8 bytes before requesting RX DMA operation */
497 /* TX with higher priority and possibly with shorter transfers */
498 sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
499 sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
500 sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
501
502 /* We're using the following interrupts:
503 - TXINT (DMAC completed all transmisions, underrun or DCD change)
504 - all DMA interrupts
505 */
506 sca_set_carrier(port);
507
508 /* MSCI TX INT and RX INT A IRQ enable */
509 sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
510 sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
511 sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
512 IER0, card); /* TXINT and RXINT */
513 /* enable DMA IRQ */
514 sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
515 IER1, card);
516
517 sca_out(port->tmc, msci + TMC, card); /* Restore registers */
518 sca_out(port->rxs, msci + RXS, card);
519 sca_out(port->txs, msci + TXS, card);
520 sca_out(CMD_TX_ENABLE, msci + CMD, card);
521 sca_out(CMD_RX_ENABLE, msci + CMD, card);
522
523 netif_start_queue(dev);
524 }
525
526
527 static void sca_close(struct net_device *dev)
528 {
529 port_t *port = dev_to_port(dev);
530 card_t* card = port_to_card(port);
531
532 /* reset channel */
533 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
534 /* disable MSCI interrupts */
535 sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
536 IER0, card);
537 /* disable DMA interrupts */
538 sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
539 IER1, card);
540
541 netif_stop_queue(dev);
542 }
543
544
545 static int sca_attach(struct net_device *dev, unsigned short encoding,
546 unsigned short parity)
547 {
548 if (encoding != ENCODING_NRZ &&
549 encoding != ENCODING_NRZI &&
550 encoding != ENCODING_FM_MARK &&
551 encoding != ENCODING_FM_SPACE &&
552 encoding != ENCODING_MANCHESTER)
553 return -EINVAL;
554
555 if (parity != PARITY_NONE &&
556 parity != PARITY_CRC16_PR0 &&
557 parity != PARITY_CRC16_PR1 &&
558 parity != PARITY_CRC16_PR0_CCITT &&
559 parity != PARITY_CRC16_PR1_CCITT)
560 return -EINVAL;
561
562 dev_to_port(dev)->encoding = encoding;
563 dev_to_port(dev)->parity = parity;
564 return 0;
565 }
566
567
568 #ifdef DEBUG_RINGS
569 static void sca_dump_rings(struct net_device *dev)
570 {
571 port_t *port = dev_to_port(dev);
572 card_t *card = port_to_card(port);
573 u16 cnt;
574 #ifndef PAGE0_ALWAYS_MAPPED
575 u8 page = sca_get_page(card);
576
577 openwin(card, 0);
578 #endif
579
580 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
581 sca_inw(get_dmac_rx(port) + CDAL, card),
582 sca_inw(get_dmac_rx(port) + EDAL, card),
583 sca_in(DSR_RX(phy_node(port)), card), port->rxin,
584 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
585 for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
586 printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
587 printk(KERN_CONT "\n");
588
589 printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
590 "last=%u %sactive",
591 sca_inw(get_dmac_tx(port) + CDAL, card),
592 sca_inw(get_dmac_tx(port) + EDAL, card),
593 sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
594 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
595
596 for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
597 printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
598 printk("\n");
599
600 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, ST: %02x %02x %02x %02x,"
601 " FST: %02x CST: %02x %02x\n",
602 sca_in(get_msci(port) + MD0, card),
603 sca_in(get_msci(port) + MD1, card),
604 sca_in(get_msci(port) + MD2, card),
605 sca_in(get_msci(port) + ST0, card),
606 sca_in(get_msci(port) + ST1, card),
607 sca_in(get_msci(port) + ST2, card),
608 sca_in(get_msci(port) + ST3, card),
609 sca_in(get_msci(port) + FST, card),
610 sca_in(get_msci(port) + CST0, card),
611 sca_in(get_msci(port) + CST1, card));
612
613 printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
614 sca_in(ISR1, card), sca_in(ISR2, card));
615
616 #ifndef PAGE0_ALWAYS_MAPPED
617 openwin(card, page); /* Restore original page */
618 #endif
619 }
620 #endif /* DEBUG_RINGS */
621
622
623 static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
624 {
625 port_t *port = dev_to_port(dev);
626 card_t *card = port_to_card(port);
627 pkt_desc __iomem *desc;
628 u32 buff, len;
629 u8 page;
630 u32 maxlen;
631
632 spin_lock_irq(&port->lock);
633
634 desc = desc_address(port, port->txin + 1, 1);
635 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
636
637 #ifdef DEBUG_PKT
638 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
639 debug_frame(skb);
640 #endif
641
642 desc = desc_address(port, port->txin, 1);
643 buff = buffer_offset(port, port->txin, 1);
644 len = skb->len;
645 page = buff / winsize(card);
646 buff = buff % winsize(card);
647 maxlen = winsize(card) - buff;
648
649 openwin(card, page);
650 if (len > maxlen) {
651 memcpy_toio(winbase(card) + buff, skb->data, maxlen);
652 openwin(card, page + 1);
653 memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
654 } else
655 memcpy_toio(winbase(card) + buff, skb->data, len);
656
657 #ifndef PAGE0_ALWAYS_MAPPED
658 openwin(card, 0); /* select pkt_desc table page back */
659 #endif
660 writew(len, &desc->len);
661 writeb(ST_TX_EOM, &desc->stat);
662 dev->trans_start = jiffies;
663
664 port->txin = next_desc(port, port->txin, 1);
665 sca_outw(desc_offset(port, port->txin, 1),
666 get_dmac_tx(port) + EDAL, card);
667
668 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
669
670 desc = desc_address(port, port->txin + 1, 1);
671 if (readb(&desc->stat)) /* allow 1 packet gap */
672 netif_stop_queue(dev);
673
674 spin_unlock_irq(&port->lock);
675
676 dev_kfree_skb(skb);
677 return NETDEV_TX_OK;
678 }
679
680
681 #ifdef NEED_DETECT_RAM
682 static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase,
683 u32 ramsize)
684 {
685 /* Round RAM size to 32 bits, fill from end to start */
686 u32 i = ramsize &= ~3;
687 u32 size = winsize(card);
688
689 openwin(card, (i - 4) / size); /* select last window */
690
691 do {
692 i -= 4;
693 if ((i + 4) % size == 0)
694 openwin(card, i / size);
695 writel(i ^ 0x12345678, rambase + i % size);
696 } while (i > 0);
697
698 for (i = 0; i < ramsize ; i += 4) {
699 if (i % size == 0)
700 openwin(card, i / size);
701
702 if (readl(rambase + i % size) != (i ^ 0x12345678))
703 break;
704 }
705
706 return i;
707 }
708 #endif /* NEED_DETECT_RAM */
709
710
711 static void __devinit sca_init(card_t *card, int wait_states)
712 {
713 sca_out(wait_states, WCRL, card); /* Wait Control */
714 sca_out(wait_states, WCRM, card);
715 sca_out(wait_states, WCRH, card);
716
717 sca_out(0, DMER, card); /* DMA Master disable */
718 sca_out(0x03, PCR, card); /* DMA priority */
719 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
720 sca_out(0, DSR_TX(0), card);
721 sca_out(0, DSR_RX(1), card);
722 sca_out(0, DSR_TX(1), card);
723 sca_out(DMER_DME, DMER, card); /* DMA Master enable */
724 }
Linux for Ginger Game Console