Save sram context after changing MPU, DSP or core clocks
[linux-ginger.git] / drivers / net / wireless / wl12xx / wl1251_rx.h
blob563a3fde40fb8ded986c4dc1f0d0f72917f6b125
1 /*
2 * This file is part of wl1251
4 * Copyright (c) 1998-2007 Texas Instruments Incorporated
5 * Copyright (C) 2008 Nokia Corporation
7 * Contact: Kalle Valo <kalle.valo@nokia.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
25 #ifndef __WL1251_RX_H__
26 #define __WL1251_RX_H__
28 #include <linux/bitops.h>
30 #include "wl1251.h"
33 * RX PATH
35 * The Rx path uses a double buffer and an rx_contro structure, each located
36 * at a fixed address in the device memory. The host keeps track of which
37 * buffer is available and alternates between them on a per packet basis.
38 * The size of each of the two buffers is large enough to hold the longest
39 * 802.3 packet.
40 * The RX path goes like that:
41 * 1) The target generates an interrupt each time a new packet is received.
42 * There are 2 RX interrupts, one for each buffer.
43 * 2) The host reads the received packet from one of the double buffers.
44 * 3) The host triggers a target interrupt.
45 * 4) The target prepares the next RX packet.
48 #define WL1251_RX_MAX_RSSI -30
49 #define WL1251_RX_MIN_RSSI -95
51 #define WL1251_RX_ALIGN_TO 4
52 #define WL1251_RX_ALIGN(len) (((len) + WL1251_RX_ALIGN_TO - 1) & \
53 ~(WL1251_RX_ALIGN_TO - 1))
55 #define SHORT_PREAMBLE_BIT BIT(0)
56 #define OFDM_RATE_BIT BIT(6)
57 #define PBCC_RATE_BIT BIT(7)
59 #define PLCP_HEADER_LENGTH 8
60 #define RX_DESC_PACKETID_SHIFT 11
61 #define RX_MAX_PACKET_ID 3
63 #define RX_DESC_VALID_FCS 0x0001
64 #define RX_DESC_MATCH_RXADDR1 0x0002
65 #define RX_DESC_MCAST 0x0004
66 #define RX_DESC_STAINTIM 0x0008
67 #define RX_DESC_VIRTUAL_BM 0x0010
68 #define RX_DESC_BCAST 0x0020
69 #define RX_DESC_MATCH_SSID 0x0040
70 #define RX_DESC_MATCH_BSSID 0x0080
71 #define RX_DESC_ENCRYPTION_MASK 0x0300
72 #define RX_DESC_MEASURMENT 0x0400
73 #define RX_DESC_SEQNUM_MASK 0x1800
74 #define RX_DESC_MIC_FAIL 0x2000
75 #define RX_DESC_DECRYPT_FAIL 0x4000
77 struct wl1251_rx_descriptor {
78 u32 timestamp; /* In microseconds */
79 u16 length; /* Paylod length, including headers */
80 u16 flags;
83 * 0 - 802.11
84 * 1 - 802.3
85 * 2 - IP
86 * 3 - Raw Codec
88 u8 type;
91 * Received Rate:
92 * 0x0A - 1MBPS
93 * 0x14 - 2MBPS
94 * 0x37 - 5_5MBPS
95 * 0x0B - 6MBPS
96 * 0x0F - 9MBPS
97 * 0x6E - 11MBPS
98 * 0x0A - 12MBPS
99 * 0x0E - 18MBPS
100 * 0xDC - 22MBPS
101 * 0x09 - 24MBPS
102 * 0x0D - 36MBPS
103 * 0x08 - 48MBPS
104 * 0x0C - 54MBPS
106 u8 rate;
108 u8 mod_pre; /* Modulation and preamble */
109 u8 channel;
112 * 0 - 2.4 Ghz
113 * 1 - 5 Ghz
115 u8 band;
117 s8 rssi; /* in dB */
118 u8 rcpi; /* in dB */
119 u8 snr; /* in dB */
120 } __attribute__ ((packed));
122 void wl1251_rx(struct wl1251 *wl);
124 #endif