Save sram context after changing MPU, DSP or core clocks
[linux-ginger.git] / drivers / net / wireless / wl12xx / wl1271_spi.h
blob2c996845864665ed75b014fa041e73b03a5a7fbf
1 /*
2 * This file is part of wl1271
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2009 Nokia Corporation
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
25 #ifndef __WL1271_SPI_H__
26 #define __WL1271_SPI_H__
28 #include "wl1271_reg.h"
30 #define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0
32 #define HW_ACCESS_PART0_SIZE_ADDR 0x1FFC0
33 #define HW_ACCESS_PART0_START_ADDR 0x1FFC4
34 #define HW_ACCESS_PART1_SIZE_ADDR 0x1FFC8
35 #define HW_ACCESS_PART1_START_ADDR 0x1FFCC
37 #define HW_ACCESS_REGISTER_SIZE 4
39 #define HW_ACCESS_PRAM_MAX_RANGE 0x3c000
41 #define WSPI_CMD_READ 0x40000000
42 #define WSPI_CMD_WRITE 0x00000000
43 #define WSPI_CMD_FIXED 0x20000000
44 #define WSPI_CMD_BYTE_LENGTH 0x1FFE0000
45 #define WSPI_CMD_BYTE_LENGTH_OFFSET 17
46 #define WSPI_CMD_BYTE_ADDR 0x0001FFFF
48 #define WSPI_INIT_CMD_CRC_LEN 5
50 #define WSPI_INIT_CMD_START 0x00
51 #define WSPI_INIT_CMD_TX 0x40
52 /* the extra bypass bit is sampled by the TNET as '1' */
53 #define WSPI_INIT_CMD_BYPASS_BIT 0x80
54 #define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
55 #define WSPI_INIT_CMD_EN_FIXEDBUSY 0x80
56 #define WSPI_INIT_CMD_DIS_FIXEDBUSY 0x00
57 #define WSPI_INIT_CMD_IOD 0x40
58 #define WSPI_INIT_CMD_IP 0x20
59 #define WSPI_INIT_CMD_CS 0x10
60 #define WSPI_INIT_CMD_WS 0x08
61 #define WSPI_INIT_CMD_WSPI 0x01
62 #define WSPI_INIT_CMD_END 0x01
64 #define WSPI_INIT_CMD_LEN 8
66 #define HW_ACCESS_WSPI_FIXED_BUSY_LEN \
67 ((WL1271_BUSY_WORD_LEN - 4) / sizeof(u32))
68 #define HW_ACCESS_WSPI_INIT_CMD_MASK 0
71 /* Raw target IO, address is not translated */
72 void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf,
73 size_t len, bool fixed);
74 void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf,
75 size_t len, bool fixed);
77 /* Memory target IO, address is tranlated to partition 0 */
78 void wl1271_spi_mem_read(struct wl1271 *wl, int addr, void *buf, size_t len);
79 void wl1271_spi_mem_write(struct wl1271 *wl, int addr, void *buf, size_t len);
80 u32 wl1271_mem_read32(struct wl1271 *wl, int addr);
81 void wl1271_mem_write32(struct wl1271 *wl, int addr, u32 val);
83 /* Registers IO */
84 void wl1271_spi_reg_read(struct wl1271 *wl, int addr, void *buf, size_t len,
85 bool fixed);
86 void wl1271_spi_reg_write(struct wl1271 *wl, int addr, void *buf, size_t len,
87 bool fixed);
88 u32 wl1271_reg_read32(struct wl1271 *wl, int addr);
89 void wl1271_reg_write32(struct wl1271 *wl, int addr, u32 val);
91 /* INIT and RESET words */
92 void wl1271_spi_reset(struct wl1271 *wl);
93 void wl1271_spi_init(struct wl1271 *wl);
94 int wl1271_set_partition(struct wl1271 *wl,
95 u32 part_start, u32 part_size,
96 u32 reg_start, u32 reg_size);
98 static inline u32 wl1271_read32(struct wl1271 *wl, int addr)
100 wl1271_spi_read(wl, addr, &wl->buffer_32,
101 sizeof(wl->buffer_32), false);
103 return wl->buffer_32;
106 static inline void wl1271_write32(struct wl1271 *wl, int addr, u32 val)
108 wl->buffer_32 = val;
109 wl1271_spi_write(wl, addr, &wl->buffer_32,
110 sizeof(wl->buffer_32), false);
113 #endif /* __WL1271_SPI_H__ */