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Save sram context after changing MPU, DSP or core clocks
[linux-ginger.git] / drivers / usb / gadget / atmel_usba_udc.c
blob4e970cf0e29ae364b34c5e7436906e95db313952
1 /*
2 * Driver for the Atmel USBA high speed USB device controller
3 *
4 * Copyright (C) 2005-2007 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/clk.h>
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/list.h>
18 #include <linux/platform_device.h>
19 #include <linux/usb/ch9.h>
20 #include <linux/usb/gadget.h>
21 #include <linux/usb/atmel_usba_udc.h>
22 #include <linux/delay.h>
23
24 #include <asm/gpio.h>
25 #include <mach/board.h>
26
27 #include "atmel_usba_udc.h"
28
29
30 static struct usba_udc the_udc;
31 static struct usba_ep *usba_ep;
32
33 #ifdef CONFIG_USB_GADGET_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/uaccess.h>
36
37 static int queue_dbg_open(struct inode *inode, struct file *file)
38 {
39 struct usba_ep *ep = inode->i_private;
40 struct usba_request *req, *req_copy;
41 struct list_head *queue_data;
42
43 queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
44 if (!queue_data)
45 return -ENOMEM;
46 INIT_LIST_HEAD(queue_data);
47
48 spin_lock_irq(&ep->udc->lock);
49 list_for_each_entry(req, &ep->queue, queue) {
50 req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
51 if (!req_copy)
52 goto fail;
53 memcpy(req_copy, req, sizeof(*req_copy));
54 list_add_tail(&req_copy->queue, queue_data);
55 }
56 spin_unlock_irq(&ep->udc->lock);
57
58 file->private_data = queue_data;
59 return 0;
60
61 fail:
62 spin_unlock_irq(&ep->udc->lock);
63 list_for_each_entry_safe(req, req_copy, queue_data, queue) {
64 list_del(&req->queue);
65 kfree(req);
66 }
67 kfree(queue_data);
68 return -ENOMEM;
69 }
70
71 /*
72 * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
73 *
74 * b: buffer address
75 * l: buffer length
76 * I/i: interrupt/no interrupt
77 * Z/z: zero/no zero
78 * S/s: short ok/short not ok
79 * s: status
80 * n: nr_packets
81 * F/f: submitted/not submitted to FIFO
82 * D/d: using/not using DMA
83 * L/l: last transaction/not last transaction
84 */
85 static ssize_t queue_dbg_read(struct file *file, char __user *buf,
86 size_t nbytes, loff_t *ppos)
87 {
88 struct list_head *queue = file->private_data;
89 struct usba_request *req, *tmp_req;
90 size_t len, remaining, actual = 0;
91 char tmpbuf[38];
92
93 if (!access_ok(VERIFY_WRITE, buf, nbytes))
94 return -EFAULT;
95
96 mutex_lock(&file->f_dentry->d_inode->i_mutex);
97 list_for_each_entry_safe(req, tmp_req, queue, queue) {
98 len = snprintf(tmpbuf, sizeof(tmpbuf),
99 "%8p %08x %c%c%c %5d %c%c%c\n",
100 req->req.buf, req->req.length,
101 req->req.no_interrupt ? 'i' : 'I',
102 req->req.zero ? 'Z' : 'z',
103 req->req.short_not_ok ? 's' : 'S',
104 req->req.status,
105 req->submitted ? 'F' : 'f',
106 req->using_dma ? 'D' : 'd',
107 req->last_transaction ? 'L' : 'l');
108 len = min(len, sizeof(tmpbuf));
109 if (len > nbytes)
110 break;
111
112 list_del(&req->queue);
113 kfree(req);
114
115 remaining = __copy_to_user(buf, tmpbuf, len);
116 actual += len - remaining;
117 if (remaining)
118 break;
119
120 nbytes -= len;
121 buf += len;
122 }
123 mutex_unlock(&file->f_dentry->d_inode->i_mutex);
124
125 return actual;
126 }
127
128 static int queue_dbg_release(struct inode *inode, struct file *file)
129 {
130 struct list_head *queue_data = file->private_data;
131 struct usba_request *req, *tmp_req;
132
133 list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
134 list_del(&req->queue);
135 kfree(req);
136 }
137 kfree(queue_data);
138 return 0;
139 }
140
141 static int regs_dbg_open(struct inode *inode, struct file *file)
142 {
143 struct usba_udc *udc;
144 unsigned int i;
145 u32 *data;
146 int ret = -ENOMEM;
147
148 mutex_lock(&inode->i_mutex);
149 udc = inode->i_private;
150 data = kmalloc(inode->i_size, GFP_KERNEL);
151 if (!data)
152 goto out;
153
154 spin_lock_irq(&udc->lock);
155 for (i = 0; i < inode->i_size / 4; i++)
156 data[i] = __raw_readl(udc->regs + i * 4);
157 spin_unlock_irq(&udc->lock);
158
159 file->private_data = data;
160 ret = 0;
161
162 out:
163 mutex_unlock(&inode->i_mutex);
164
165 return ret;
166 }
167
168 static ssize_t regs_dbg_read(struct file *file, char __user *buf,
169 size_t nbytes, loff_t *ppos)
170 {
171 struct inode *inode = file->f_dentry->d_inode;
172 int ret;
173
174 mutex_lock(&inode->i_mutex);
175 ret = simple_read_from_buffer(buf, nbytes, ppos,
176 file->private_data,
177 file->f_dentry->d_inode->i_size);
178 mutex_unlock(&inode->i_mutex);
179
180 return ret;
181 }
182
183 static int regs_dbg_release(struct inode *inode, struct file *file)
184 {
185 kfree(file->private_data);
186 return 0;
187 }
188
189 const struct file_operations queue_dbg_fops = {
190 .owner = THIS_MODULE,
191 .open = queue_dbg_open,
192 .llseek = no_llseek,
193 .read = queue_dbg_read,
194 .release = queue_dbg_release,
195 };
196
197 const struct file_operations regs_dbg_fops = {
198 .owner = THIS_MODULE,
199 .open = regs_dbg_open,
200 .llseek = generic_file_llseek,
201 .read = regs_dbg_read,
202 .release = regs_dbg_release,
203 };
204
205 static void usba_ep_init_debugfs(struct usba_udc *udc,
206 struct usba_ep *ep)
207 {
208 struct dentry *ep_root;
209
210 ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
211 if (!ep_root)
212 goto err_root;
213 ep->debugfs_dir = ep_root;
214
215 ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
216 ep, &queue_dbg_fops);
217 if (!ep->debugfs_queue)
218 goto err_queue;
219
220 if (ep->can_dma) {
221 ep->debugfs_dma_status
222 = debugfs_create_u32("dma_status", 0400, ep_root,
223 &ep->last_dma_status);
224 if (!ep->debugfs_dma_status)
225 goto err_dma_status;
226 }
227 if (ep_is_control(ep)) {
228 ep->debugfs_state
229 = debugfs_create_u32("state", 0400, ep_root,
230 &ep->state);
231 if (!ep->debugfs_state)
232 goto err_state;
233 }
234
235 return;
236
237 err_state:
238 if (ep->can_dma)
239 debugfs_remove(ep->debugfs_dma_status);
240 err_dma_status:
241 debugfs_remove(ep->debugfs_queue);
242 err_queue:
243 debugfs_remove(ep_root);
244 err_root:
245 dev_err(&ep->udc->pdev->dev,
246 "failed to create debugfs directory for %s\n", ep->ep.name);
247 }
248
249 static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
250 {
251 debugfs_remove(ep->debugfs_queue);
252 debugfs_remove(ep->debugfs_dma_status);
253 debugfs_remove(ep->debugfs_state);
254 debugfs_remove(ep->debugfs_dir);
255 ep->debugfs_dma_status = NULL;
256 ep->debugfs_dir = NULL;
257 }
258
259 static void usba_init_debugfs(struct usba_udc *udc)
260 {
261 struct dentry *root, *regs;
262 struct resource *regs_resource;
263
264 root = debugfs_create_dir(udc->gadget.name, NULL);
265 if (IS_ERR(root) || !root)
266 goto err_root;
267 udc->debugfs_root = root;
268
269 regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
270 if (!regs)
271 goto err_regs;
272
273 regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
274 CTRL_IOMEM_ID);
275 regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
276 udc->debugfs_regs = regs;
277
278 usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
279
280 return;
281
282 err_regs:
283 debugfs_remove(root);
284 err_root:
285 udc->debugfs_root = NULL;
286 dev_err(&udc->pdev->dev, "debugfs is not available\n");
287 }
288
289 static void usba_cleanup_debugfs(struct usba_udc *udc)
290 {
291 usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
292 debugfs_remove(udc->debugfs_regs);
293 debugfs_remove(udc->debugfs_root);
294 udc->debugfs_regs = NULL;
295 udc->debugfs_root = NULL;
296 }
297 #else
298 static inline void usba_ep_init_debugfs(struct usba_udc *udc,
299 struct usba_ep *ep)
300 {
301
302 }
303
304 static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
305 {
306
307 }
308
309 static inline void usba_init_debugfs(struct usba_udc *udc)
310 {
311
312 }
313
314 static inline void usba_cleanup_debugfs(struct usba_udc *udc)
315 {
316
317 }
318 #endif
319
320 static int vbus_is_present(struct usba_udc *udc)
321 {
322 if (gpio_is_valid(udc->vbus_pin))
323 return gpio_get_value(udc->vbus_pin);
324
325 /* No Vbus detection: Assume always present */
326 return 1;
327 }
328
329 #if defined(CONFIG_ARCH_AT91SAM9RL)
330
331 #include <mach/at91_pmc.h>
332
333 static void toggle_bias(int is_on)
334 {
335 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
336
337 if (is_on)
338 at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
339 else
340 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
341 }
342
343 #else
344
345 static void toggle_bias(int is_on)
346 {
347 }
348
349 #endif /* CONFIG_ARCH_AT91SAM9RL */
350
351 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
352 {
353 unsigned int transaction_len;
354
355 transaction_len = req->req.length - req->req.actual;
356 req->last_transaction = 1;
357 if (transaction_len > ep->ep.maxpacket) {
358 transaction_len = ep->ep.maxpacket;
359 req->last_transaction = 0;
360 } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
361 req->last_transaction = 0;
362
363 DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
364 ep->ep.name, req, transaction_len,
365 req->last_transaction ? ", done" : "");
366
367 memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
368 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
369 req->req.actual += transaction_len;
370 }
371
372 static void submit_request(struct usba_ep *ep, struct usba_request *req)
373 {
374 DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
375 ep->ep.name, req, req->req.length);
376
377 req->req.actual = 0;
378 req->submitted = 1;
379
380 if (req->using_dma) {
381 if (req->req.length == 0) {
382 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
383 return;
384 }
385
386 if (req->req.zero)
387 usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
388 else
389 usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
390
391 usba_dma_writel(ep, ADDRESS, req->req.dma);
392 usba_dma_writel(ep, CONTROL, req->ctrl);
393 } else {
394 next_fifo_transaction(ep, req);
395 if (req->last_transaction) {
396 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
397 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
398 } else {
399 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
400 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
401 }
402 }
403 }
404
405 static void submit_next_request(struct usba_ep *ep)
406 {
407 struct usba_request *req;
408
409 if (list_empty(&ep->queue)) {
410 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
411 return;
412 }
413
414 req = list_entry(ep->queue.next, struct usba_request, queue);
415 if (!req->submitted)
416 submit_request(ep, req);
417 }
418
419 static void send_status(struct usba_udc *udc, struct usba_ep *ep)
420 {
421 ep->state = STATUS_STAGE_IN;
422 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
423 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
424 }
425
426 static void receive_data(struct usba_ep *ep)
427 {
428 struct usba_udc *udc = ep->udc;
429 struct usba_request *req;
430 unsigned long status;
431 unsigned int bytecount, nr_busy;
432 int is_complete = 0;
433
434 status = usba_ep_readl(ep, STA);
435 nr_busy = USBA_BFEXT(BUSY_BANKS, status);
436
437 DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
438
439 while (nr_busy > 0) {
440 if (list_empty(&ep->queue)) {
441 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
442 break;
443 }
444 req = list_entry(ep->queue.next,
445 struct usba_request, queue);
446
447 bytecount = USBA_BFEXT(BYTE_COUNT, status);
448
449 if (status & (1 << 31))
450 is_complete = 1;
451 if (req->req.actual + bytecount >= req->req.length) {
452 is_complete = 1;
453 bytecount = req->req.length - req->req.actual;
454 }
455
456 memcpy_fromio(req->req.buf + req->req.actual,
457 ep->fifo, bytecount);
458 req->req.actual += bytecount;
459
460 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
461
462 if (is_complete) {
463 DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
464 req->req.status = 0;
465 list_del_init(&req->queue);
466 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
467 spin_unlock(&udc->lock);
468 req->req.complete(&ep->ep, &req->req);
469 spin_lock(&udc->lock);
470 }
471
472 status = usba_ep_readl(ep, STA);
473 nr_busy = USBA_BFEXT(BUSY_BANKS, status);
474
475 if (is_complete && ep_is_control(ep)) {
476 send_status(udc, ep);
477 break;
478 }
479 }
480 }
481
482 static void
483 request_complete(struct usba_ep *ep, struct usba_request *req, int status)
484 {
485 struct usba_udc *udc = ep->udc;
486
487 WARN_ON(!list_empty(&req->queue));
488
489 if (req->req.status == -EINPROGRESS)
490 req->req.status = status;
491
492 if (req->mapped) {
493 dma_unmap_single(
494 &udc->pdev->dev, req->req.dma, req->req.length,
495 ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
496 req->req.dma = DMA_ADDR_INVALID;
497 req->mapped = 0;
498 }
499
500 DBG(DBG_GADGET | DBG_REQ,
501 "%s: req %p complete: status %d, actual %u\n",
502 ep->ep.name, req, req->req.status, req->req.actual);
503
504 spin_unlock(&udc->lock);
505 req->req.complete(&ep->ep, &req->req);
506 spin_lock(&udc->lock);
507 }
508
509 static void
510 request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
511 {
512 struct usba_request *req, *tmp_req;
513
514 list_for_each_entry_safe(req, tmp_req, list, queue) {
515 list_del_init(&req->queue);
516 request_complete(ep, req, status);
517 }
518 }
519
520 static int
521 usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
522 {
523 struct usba_ep *ep = to_usba_ep(_ep);
524 struct usba_udc *udc = ep->udc;
525 unsigned long flags, ept_cfg, maxpacket;
526 unsigned int nr_trans;
527
528 DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
529
530 maxpacket = le16_to_cpu(desc->wMaxPacketSize) & 0x7ff;
531
532 if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
533 || ep->index == 0
534 || desc->bDescriptorType != USB_DT_ENDPOINT
535 || maxpacket == 0
536 || maxpacket > ep->fifo_size) {
537 DBG(DBG_ERR, "ep_enable: Invalid argument");
538 return -EINVAL;
539 }
540
541 ep->is_isoc = 0;
542 ep->is_in = 0;
543
544 if (maxpacket <= 8)
545 ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
546 else
547 /* LSB is bit 1, not 0 */
548 ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
549
550 DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
551 ep->ep.name, ept_cfg, maxpacket);
552
553 if (usb_endpoint_dir_in(desc)) {
554 ep->is_in = 1;
555 ept_cfg |= USBA_EPT_DIR_IN;
556 }
557
558 switch (usb_endpoint_type(desc)) {
559 case USB_ENDPOINT_XFER_CONTROL:
560 ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
561 ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
562 break;
563 case USB_ENDPOINT_XFER_ISOC:
564 if (!ep->can_isoc) {
565 DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
566 ep->ep.name);
567 return -EINVAL;
568 }
569
570 /*
571 * Bits 11:12 specify number of _additional_
572 * transactions per microframe.
573 */
574 nr_trans = ((le16_to_cpu(desc->wMaxPacketSize) >> 11) & 3) + 1;
575 if (nr_trans > 3)
576 return -EINVAL;
577
578 ep->is_isoc = 1;
579 ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
580
581 /*
582 * Do triple-buffering on high-bandwidth iso endpoints.
583 */
584 if (nr_trans > 1 && ep->nr_banks == 3)
585 ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
586 else
587 ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
588 ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
589 break;
590 case USB_ENDPOINT_XFER_BULK:
591 ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
592 ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
593 break;
594 case USB_ENDPOINT_XFER_INT:
595 ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
596 ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
597 break;
598 }
599
600 spin_lock_irqsave(&ep->udc->lock, flags);
601
602 if (ep->desc) {
603 spin_unlock_irqrestore(&ep->udc->lock, flags);
604 DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
605 return -EBUSY;
606 }
607
608 ep->desc = desc;
609 ep->ep.maxpacket = maxpacket;
610
611 usba_ep_writel(ep, CFG, ept_cfg);
612 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
613
614 if (ep->can_dma) {
615 u32 ctrl;
616
617 usba_writel(udc, INT_ENB,
618 (usba_readl(udc, INT_ENB)
619 | USBA_BF(EPT_INT, 1 << ep->index)
620 | USBA_BF(DMA_INT, 1 << ep->index)));
621 ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
622 usba_ep_writel(ep, CTL_ENB, ctrl);
623 } else {
624 usba_writel(udc, INT_ENB,
625 (usba_readl(udc, INT_ENB)
626 | USBA_BF(EPT_INT, 1 << ep->index)));
627 }
628
629 spin_unlock_irqrestore(&udc->lock, flags);
630
631 DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
632 (unsigned long)usba_ep_readl(ep, CFG));
633 DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
634 (unsigned long)usba_readl(udc, INT_ENB));
635
636 return 0;
637 }
638
639 static int usba_ep_disable(struct usb_ep *_ep)
640 {
641 struct usba_ep *ep = to_usba_ep(_ep);
642 struct usba_udc *udc = ep->udc;
643 LIST_HEAD(req_list);
644 unsigned long flags;
645
646 DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
647
648 spin_lock_irqsave(&udc->lock, flags);
649
650 if (!ep->desc) {
651 spin_unlock_irqrestore(&udc->lock, flags);
652 /* REVISIT because this driver disables endpoints in
653 * reset_all_endpoints() before calling disconnect(),
654 * most gadget drivers would trigger this non-error ...
655 */
656 if (udc->gadget.speed != USB_SPEED_UNKNOWN)
657 DBG(DBG_ERR, "ep_disable: %s not enabled\n",
658 ep->ep.name);
659 return -EINVAL;
660 }
661 ep->desc = NULL;
662
663 list_splice_init(&ep->queue, &req_list);
664 if (ep->can_dma) {
665 usba_dma_writel(ep, CONTROL, 0);
666 usba_dma_writel(ep, ADDRESS, 0);
667 usba_dma_readl(ep, STATUS);
668 }
669 usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
670 usba_writel(udc, INT_ENB,
671 usba_readl(udc, INT_ENB)
672 & ~USBA_BF(EPT_INT, 1 << ep->index));
673
674 request_complete_list(ep, &req_list, -ESHUTDOWN);
675
676 spin_unlock_irqrestore(&udc->lock, flags);
677
678 return 0;
679 }
680
681 static struct usb_request *
682 usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
683 {
684 struct usba_request *req;
685
686 DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
687
688 req = kzalloc(sizeof(*req), gfp_flags);
689 if (!req)
690 return NULL;
691
692 INIT_LIST_HEAD(&req->queue);
693 req->req.dma = DMA_ADDR_INVALID;
694
695 return &req->req;
696 }
697
698 static void
699 usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
700 {
701 struct usba_request *req = to_usba_req(_req);
702
703 DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
704
705 kfree(req);
706 }
707
708 static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
709 struct usba_request *req, gfp_t gfp_flags)
710 {
711 unsigned long flags;
712 int ret;
713
714 DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
715 ep->ep.name, req->req.length, req->req.dma,
716 req->req.zero ? 'Z' : 'z',
717 req->req.short_not_ok ? 'S' : 's',
718 req->req.no_interrupt ? 'I' : 'i');
719
720 if (req->req.length > 0x10000) {
721 /* Lengths from 0 to 65536 (inclusive) are supported */
722 DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
723 return -EINVAL;
724 }
725
726 req->using_dma = 1;
727
728 if (req->req.dma == DMA_ADDR_INVALID) {
729 req->req.dma = dma_map_single(
730 &udc->pdev->dev, req->req.buf, req->req.length,
731 ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
732 req->mapped = 1;
733 } else {
734 dma_sync_single_for_device(
735 &udc->pdev->dev, req->req.dma, req->req.length,
736 ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
737 req->mapped = 0;
738 }
739
740 req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
741 | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
742 | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
743
744 if (ep->is_in)
745 req->ctrl |= USBA_DMA_END_BUF_EN;
746
747 /*
748 * Add this request to the queue and submit for DMA if
749 * possible. Check if we're still alive first -- we may have
750 * received a reset since last time we checked.
751 */
752 ret = -ESHUTDOWN;
753 spin_lock_irqsave(&udc->lock, flags);
754 if (ep->desc) {
755 if (list_empty(&ep->queue))
756 submit_request(ep, req);
757
758 list_add_tail(&req->queue, &ep->queue);
759 ret = 0;
760 }
761 spin_unlock_irqrestore(&udc->lock, flags);
762
763 return ret;
764 }
765
766 static int
767 usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
768 {
769 struct usba_request *req = to_usba_req(_req);
770 struct usba_ep *ep = to_usba_ep(_ep);
771 struct usba_udc *udc = ep->udc;
772 unsigned long flags;
773 int ret;
774
775 DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
776 ep->ep.name, req, _req->length);
777
778 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || !ep->desc)
779 return -ESHUTDOWN;
780
781 req->submitted = 0;
782 req->using_dma = 0;
783 req->last_transaction = 0;
784
785 _req->status = -EINPROGRESS;
786 _req->actual = 0;
787
788 if (ep->can_dma)
789 return queue_dma(udc, ep, req, gfp_flags);
790
791 /* May have received a reset since last time we checked */
792 ret = -ESHUTDOWN;
793 spin_lock_irqsave(&udc->lock, flags);
794 if (ep->desc) {
795 list_add_tail(&req->queue, &ep->queue);
796
797 if ((!ep_is_control(ep) && ep->is_in) ||
798 (ep_is_control(ep)
799 && (ep->state == DATA_STAGE_IN
800 || ep->state == STATUS_STAGE_IN)))
801 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
802 else
803 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
804 ret = 0;
805 }
806 spin_unlock_irqrestore(&udc->lock, flags);
807
808 return ret;
809 }
810
811 static void
812 usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
813 {
814 req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
815 }
816
817 static int stop_dma(struct usba_ep *ep, u32 *pstatus)
818 {
819 unsigned int timeout;
820 u32 status;
821
822 /*
823 * Stop the DMA controller. When writing both CH_EN
824 * and LINK to 0, the other bits are not affected.
825 */
826 usba_dma_writel(ep, CONTROL, 0);
827
828 /* Wait for the FIFO to empty */
829 for (timeout = 40; timeout; --timeout) {
830 status = usba_dma_readl(ep, STATUS);
831 if (!(status & USBA_DMA_CH_EN))
832 break;
833 udelay(1);
834 }
835
836 if (pstatus)
837 *pstatus = status;
838
839 if (timeout == 0) {
840 dev_err(&ep->udc->pdev->dev,
841 "%s: timed out waiting for DMA FIFO to empty\n",
842 ep->ep.name);
843 return -ETIMEDOUT;
844 }
845
846 return 0;
847 }
848
849 static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
850 {
851 struct usba_ep *ep = to_usba_ep(_ep);
852 struct usba_udc *udc = ep->udc;
853 struct usba_request *req = to_usba_req(_req);
854 unsigned long flags;
855 u32 status;
856
857 DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
858 ep->ep.name, req);
859
860 spin_lock_irqsave(&udc->lock, flags);
861
862 if (req->using_dma) {
863 /*
864 * If this request is currently being transferred,
865 * stop the DMA controller and reset the FIFO.
866 */
867 if (ep->queue.next == &req->queue) {
868 status = usba_dma_readl(ep, STATUS);
869 if (status & USBA_DMA_CH_EN)
870 stop_dma(ep, &status);
871
872 #ifdef CONFIG_USB_GADGET_DEBUG_FS
873 ep->last_dma_status = status;
874 #endif
875
876 usba_writel(udc, EPT_RST, 1 << ep->index);
877
878 usba_update_req(ep, req, status);
879 }
880 }
881
882 /*
883 * Errors should stop the queue from advancing until the
884 * completion function returns.
885 */
886 list_del_init(&req->queue);
887
888 request_complete(ep, req, -ECONNRESET);
889
890 /* Process the next request if any */
891 submit_next_request(ep);
892 spin_unlock_irqrestore(&udc->lock, flags);
893
894 return 0;
895 }
896
897 static int usba_ep_set_halt(struct usb_ep *_ep, int value)
898 {
899 struct usba_ep *ep = to_usba_ep(_ep);
900 struct usba_udc *udc = ep->udc;
901 unsigned long flags;
902 int ret = 0;
903
904 DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
905 value ? "set" : "clear");
906
907 if (!ep->desc) {
908 DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
909 ep->ep.name);
910 return -ENODEV;
911 }
912 if (ep->is_isoc) {
913 DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
914 ep->ep.name);
915 return -ENOTTY;
916 }
917
918 spin_lock_irqsave(&udc->lock, flags);
919
920 /*
921 * We can't halt IN endpoints while there are still data to be
922 * transferred
923 */
924 if (!list_empty(&ep->queue)
925 || ((value && ep->is_in && (usba_ep_readl(ep, STA)
926 & USBA_BF(BUSY_BANKS, -1L))))) {
927 ret = -EAGAIN;
928 } else {
929 if (value)
930 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
931 else
932 usba_ep_writel(ep, CLR_STA,
933 USBA_FORCE_STALL | USBA_TOGGLE_CLR);
934 usba_ep_readl(ep, STA);
935 }
936
937 spin_unlock_irqrestore(&udc->lock, flags);
938
939 return ret;
940 }
941
942 static int usba_ep_fifo_status(struct usb_ep *_ep)
943 {
944 struct usba_ep *ep = to_usba_ep(_ep);
945
946 return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
947 }
948
949 static void usba_ep_fifo_flush(struct usb_ep *_ep)
950 {
951 struct usba_ep *ep = to_usba_ep(_ep);
952 struct usba_udc *udc = ep->udc;
953
954 usba_writel(udc, EPT_RST, 1 << ep->index);
955 }
956
957 static const struct usb_ep_ops usba_ep_ops = {
958 .enable = usba_ep_enable,
959 .disable = usba_ep_disable,
960 .alloc_request = usba_ep_alloc_request,
961 .free_request = usba_ep_free_request,
962 .queue = usba_ep_queue,
963 .dequeue = usba_ep_dequeue,
964 .set_halt = usba_ep_set_halt,
965 .fifo_status = usba_ep_fifo_status,
966 .fifo_flush = usba_ep_fifo_flush,
967 };
968
969 static int usba_udc_get_frame(struct usb_gadget *gadget)
970 {
971 struct usba_udc *udc = to_usba_udc(gadget);
972
973 return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
974 }
975
976 static int usba_udc_wakeup(struct usb_gadget *gadget)
977 {
978 struct usba_udc *udc = to_usba_udc(gadget);
979 unsigned long flags;
980 u32 ctrl;
981 int ret = -EINVAL;
982
983 spin_lock_irqsave(&udc->lock, flags);
984 if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
985 ctrl = usba_readl(udc, CTRL);
986 usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
987 ret = 0;
988 }
989 spin_unlock_irqrestore(&udc->lock, flags);
990
991 return ret;
992 }
993
994 static int
995 usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
996 {
997 struct usba_udc *udc = to_usba_udc(gadget);
998 unsigned long flags;
999
1000 spin_lock_irqsave(&udc->lock, flags);
1001 if (is_selfpowered)
1002 udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
1003 else
1004 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
1005 spin_unlock_irqrestore(&udc->lock, flags);
1006
1007 return 0;
1008 }
1009
1010 static const struct usb_gadget_ops usba_udc_ops = {
1011 .get_frame = usba_udc_get_frame,
1012 .wakeup = usba_udc_wakeup,
1013 .set_selfpowered = usba_udc_set_selfpowered,
1014 };
1015
1016 static struct usb_endpoint_descriptor usba_ep0_desc = {
1017 .bLength = USB_DT_ENDPOINT_SIZE,
1018 .bDescriptorType = USB_DT_ENDPOINT,
1019 .bEndpointAddress = 0,
1020 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1021 .wMaxPacketSize = cpu_to_le16(64),
1022 /* FIXME: I have no idea what to put here */
1023 .bInterval = 1,
1024 };
1025
1026 static void nop_release(struct device *dev)
1027 {
1028
1029 }
1030
1031 static struct usba_udc the_udc = {
1032 .gadget = {
1033 .ops = &usba_udc_ops,
1034 .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
1035 .is_dualspeed = 1,
1036 .name = "atmel_usba_udc",
1037 .dev = {
1038 .init_name = "gadget",
1039 .release = nop_release,
1040 },
1041 },
1042 };
1043
1044 /*
1045 * Called with interrupts disabled and udc->lock held.
1046 */
1047 static void reset_all_endpoints(struct usba_udc *udc)
1048 {
1049 struct usba_ep *ep;
1050 struct usba_request *req, *tmp_req;
1051
1052 usba_writel(udc, EPT_RST, ~0UL);
1053
1054 ep = to_usba_ep(udc->gadget.ep0);
1055 list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
1056 list_del_init(&req->queue);
1057 request_complete(ep, req, -ECONNRESET);
1058 }
1059
1060 /* NOTE: normally, the next call to the gadget driver is in
1061 * charge of disabling endpoints... usually disconnect().
1062 * The exception would be entering a high speed test mode.
1063 *
1064 * FIXME remove this code ... and retest thoroughly.
1065 */
1066 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1067 if (ep->desc) {
1068 spin_unlock(&udc->lock);
1069 usba_ep_disable(&ep->ep);
1070 spin_lock(&udc->lock);
1071 }
1072 }
1073 }
1074
1075 static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
1076 {
1077 struct usba_ep *ep;
1078
1079 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
1080 return to_usba_ep(udc->gadget.ep0);
1081
1082 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
1083 u8 bEndpointAddress;
1084
1085 if (!ep->desc)
1086 continue;
1087 bEndpointAddress = ep->desc->bEndpointAddress;
1088 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
1089 continue;
1090 if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
1091 == (wIndex & USB_ENDPOINT_NUMBER_MASK))
1092 return ep;
1093 }
1094
1095 return NULL;
1096 }
1097
1098 /* Called with interrupts disabled and udc->lock held */
1099 static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
1100 {
1101 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
1102 ep->state = WAIT_FOR_SETUP;
1103 }
1104
1105 static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
1106 {
1107 if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
1108 return 1;
1109 return 0;
1110 }
1111
1112 static inline void set_address(struct usba_udc *udc, unsigned int addr)
1113 {
1114 u32 regval;
1115
1116 DBG(DBG_BUS, "setting address %u...\n", addr);
1117 regval = usba_readl(udc, CTRL);
1118 regval = USBA_BFINS(DEV_ADDR, addr, regval);
1119 usba_writel(udc, CTRL, regval);
1120 }
1121
1122 static int do_test_mode(struct usba_udc *udc)
1123 {
1124 static const char test_packet_buffer[] = {
1125 /* JKJKJKJK * 9 */
1126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1127 /* JJKKJJKK * 8 */
1128 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1129 /* JJKKJJKK * 8 */
1130 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
1131 /* JJJJJJJKKKKKKK * 8 */
1132 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1133 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1134 /* JJJJJJJK * 8 */
1135 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
1136 /* {JKKKKKKK * 10}, JK */
1137 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
1138 };
1139 struct usba_ep *ep;
1140 struct device *dev = &udc->pdev->dev;
1141 int test_mode;
1142
1143 test_mode = udc->test_mode;
1144
1145 /* Start from a clean slate */
1146 reset_all_endpoints(udc);
1147
1148 switch (test_mode) {
1149 case 0x0100:
1150 /* Test_J */
1151 usba_writel(udc, TST, USBA_TST_J_MODE);
1152 dev_info(dev, "Entering Test_J mode...\n");
1153 break;
1154 case 0x0200:
1155 /* Test_K */
1156 usba_writel(udc, TST, USBA_TST_K_MODE);
1157 dev_info(dev, "Entering Test_K mode...\n");
1158 break;
1159 case 0x0300:
1160 /*
1161 * Test_SE0_NAK: Force high-speed mode and set up ep0
1162 * for Bulk IN transfers
1163 */
1164 ep = &usba_ep[0];
1165 usba_writel(udc, TST,
1166 USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
1167 usba_ep_writel(ep, CFG,
1168 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1169 | USBA_EPT_DIR_IN
1170 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1171 | USBA_BF(BK_NUMBER, 1));
1172 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1173 set_protocol_stall(udc, ep);
1174 dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
1175 } else {
1176 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1177 dev_info(dev, "Entering Test_SE0_NAK mode...\n");
1178 }
1179 break;
1180 case 0x0400:
1181 /* Test_Packet */
1182 ep = &usba_ep[0];
1183 usba_ep_writel(ep, CFG,
1184 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1185 | USBA_EPT_DIR_IN
1186 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1187 | USBA_BF(BK_NUMBER, 1));
1188 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1189 set_protocol_stall(udc, ep);
1190 dev_err(dev, "Test_Packet: ep0 not mapped\n");
1191 } else {
1192 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1193 usba_writel(udc, TST, USBA_TST_PKT_MODE);
1194 memcpy_toio(ep->fifo, test_packet_buffer,
1195 sizeof(test_packet_buffer));
1196 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1197 dev_info(dev, "Entering Test_Packet mode...\n");
1198 }
1199 break;
1200 default:
1201 dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
1202 return -EINVAL;
1203 }
1204
1205 return 0;
1206 }
1207
1208 /* Avoid overly long expressions */
1209 static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
1210 {
1211 if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
1212 return true;
1213 return false;
1214 }
1215
1216 static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
1217 {
1218 if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
1219 return true;
1220 return false;
1221 }
1222
1223 static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
1224 {
1225 if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
1226 return true;
1227 return false;
1228 }
1229
1230 static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
1231 struct usb_ctrlrequest *crq)
1232 {
1233 int retval = 0;
1234
1235 switch (crq->bRequest) {
1236 case USB_REQ_GET_STATUS: {
1237 u16 status;
1238
1239 if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
1240 status = cpu_to_le16(udc->devstatus);
1241 } else if (crq->bRequestType
1242 == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
1243 status = cpu_to_le16(0);
1244 } else if (crq->bRequestType
1245 == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
1246 struct usba_ep *target;
1247
1248 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1249 if (!target)
1250 goto stall;
1251
1252 status = 0;
1253 if (is_stalled(udc, target))
1254 status |= cpu_to_le16(1);
1255 } else
1256 goto delegate;
1257
1258 /* Write directly to the FIFO. No queueing is done. */
1259 if (crq->wLength != cpu_to_le16(sizeof(status)))
1260 goto stall;
1261 ep->state = DATA_STAGE_IN;
1262 __raw_writew(status, ep->fifo);
1263 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1264 break;
1265 }
1266
1267 case USB_REQ_CLEAR_FEATURE: {
1268 if (crq->bRequestType == USB_RECIP_DEVICE) {
1269 if (feature_is_dev_remote_wakeup(crq))
1270 udc->devstatus
1271 &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
1272 else
1273 /* Can't CLEAR_FEATURE TEST_MODE */
1274 goto stall;
1275 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1276 struct usba_ep *target;
1277
1278 if (crq->wLength != cpu_to_le16(0)
1279 || !feature_is_ep_halt(crq))
1280 goto stall;
1281 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1282 if (!target)
1283 goto stall;
1284
1285 usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
1286 if (target->index != 0)
1287 usba_ep_writel(target, CLR_STA,
1288 USBA_TOGGLE_CLR);
1289 } else {
1290 goto delegate;
1291 }
1292
1293 send_status(udc, ep);
1294 break;
1295 }
1296
1297 case USB_REQ_SET_FEATURE: {
1298 if (crq->bRequestType == USB_RECIP_DEVICE) {
1299 if (feature_is_dev_test_mode(crq)) {
1300 send_status(udc, ep);
1301 ep->state = STATUS_STAGE_TEST;
1302 udc->test_mode = le16_to_cpu(crq->wIndex);
1303 return 0;
1304 } else if (feature_is_dev_remote_wakeup(crq)) {
1305 udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
1306 } else {
1307 goto stall;
1308 }
1309 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1310 struct usba_ep *target;
1311
1312 if (crq->wLength != cpu_to_le16(0)
1313 || !feature_is_ep_halt(crq))
1314 goto stall;
1315
1316 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1317 if (!target)
1318 goto stall;
1319
1320 usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
1321 } else
1322 goto delegate;
1323
1324 send_status(udc, ep);
1325 break;
1326 }
1327
1328 case USB_REQ_SET_ADDRESS:
1329 if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
1330 goto delegate;
1331
1332 set_address(udc, le16_to_cpu(crq->wValue));
1333 send_status(udc, ep);
1334 ep->state = STATUS_STAGE_ADDR;
1335 break;
1336
1337 default:
1338 delegate:
1339 spin_unlock(&udc->lock);
1340 retval = udc->driver->setup(&udc->gadget, crq);
1341 spin_lock(&udc->lock);
1342 }
1343
1344 return retval;
1345
1346 stall:
1347 pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
1348 "halting endpoint...\n",
1349 ep->ep.name, crq->bRequestType, crq->bRequest,
1350 le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
1351 le16_to_cpu(crq->wLength));
1352 set_protocol_stall(udc, ep);
1353 return -1;
1354 }
1355
1356 static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
1357 {
1358 struct usba_request *req;
1359 u32 epstatus;
1360 u32 epctrl;
1361
1362 restart:
1363 epstatus = usba_ep_readl(ep, STA);
1364 epctrl = usba_ep_readl(ep, CTL);
1365
1366 DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
1367 ep->ep.name, ep->state, epstatus, epctrl);
1368
1369 req = NULL;
1370 if (!list_empty(&ep->queue))
1371 req = list_entry(ep->queue.next,
1372 struct usba_request, queue);
1373
1374 if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1375 if (req->submitted)
1376 next_fifo_transaction(ep, req);
1377 else
1378 submit_request(ep, req);
1379
1380 if (req->last_transaction) {
1381 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1382 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
1383 }
1384 goto restart;
1385 }
1386 if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
1387 usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
1388
1389 switch (ep->state) {
1390 case DATA_STAGE_IN:
1391 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
1392 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1393 ep->state = STATUS_STAGE_OUT;
1394 break;
1395 case STATUS_STAGE_ADDR:
1396 /* Activate our new address */
1397 usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
1398 | USBA_FADDR_EN));
1399 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1400 ep->state = WAIT_FOR_SETUP;
1401 break;
1402 case STATUS_STAGE_IN:
1403 if (req) {
1404 list_del_init(&req->queue);
1405 request_complete(ep, req, 0);
1406 submit_next_request(ep);
1407 }
1408 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1409 ep->state = WAIT_FOR_SETUP;
1410 break;
1411 case STATUS_STAGE_TEST:
1412 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1413 ep->state = WAIT_FOR_SETUP;
1414 if (do_test_mode(udc))
1415 set_protocol_stall(udc, ep);
1416 break;
1417 default:
1418 pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
1419 "halting endpoint...\n",
1420 ep->ep.name, ep->state);
1421 set_protocol_stall(udc, ep);
1422 break;
1423 }
1424
1425 goto restart;
1426 }
1427 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1428 switch (ep->state) {
1429 case STATUS_STAGE_OUT:
1430 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1431 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1432
1433 if (req) {
1434 list_del_init(&req->queue);
1435 request_complete(ep, req, 0);
1436 }
1437 ep->state = WAIT_FOR_SETUP;
1438 break;
1439
1440 case DATA_STAGE_OUT:
1441 receive_data(ep);
1442 break;
1443
1444 default:
1445 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1446 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1447 pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
1448 "halting endpoint...\n",
1449 ep->ep.name, ep->state);
1450 set_protocol_stall(udc, ep);
1451 break;
1452 }
1453
1454 goto restart;
1455 }
1456 if (epstatus & USBA_RX_SETUP) {
1457 union {
1458 struct usb_ctrlrequest crq;
1459 unsigned long data[2];
1460 } crq;
1461 unsigned int pkt_len;
1462 int ret;
1463
1464 if (ep->state != WAIT_FOR_SETUP) {
1465 /*
1466 * Didn't expect a SETUP packet at this
1467 * point. Clean up any pending requests (which
1468 * may be successful).
1469 */
1470 int status = -EPROTO;
1471
1472 /*
1473 * RXRDY and TXCOMP are dropped when SETUP
1474 * packets arrive. Just pretend we received
1475 * the status packet.
1476 */
1477 if (ep->state == STATUS_STAGE_OUT
1478 || ep->state == STATUS_STAGE_IN) {
1479 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1480 status = 0;
1481 }
1482
1483 if (req) {
1484 list_del_init(&req->queue);
1485 request_complete(ep, req, status);
1486 }
1487 }
1488
1489 pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
1490 DBG(DBG_HW, "Packet length: %u\n", pkt_len);
1491 if (pkt_len != sizeof(crq)) {
1492 pr_warning("udc: Invalid packet length %u "
1493 "(expected %zu)\n", pkt_len, sizeof(crq));
1494 set_protocol_stall(udc, ep);
1495 return;
1496 }
1497
1498 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
1499 memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
1500
1501 /* Free up one bank in the FIFO so that we can
1502 * generate or receive a reply right away. */
1503 usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
1504
1505 /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
1506 ep->state, crq.crq.bRequestType,
1507 crq.crq.bRequest); */
1508
1509 if (crq.crq.bRequestType & USB_DIR_IN) {
1510 /*
1511 * The USB 2.0 spec states that "if wLength is
1512 * zero, there is no data transfer phase."
1513 * However, testusb #14 seems to actually
1514 * expect a data phase even if wLength = 0...
1515 */
1516 ep->state = DATA_STAGE_IN;
1517 } else {
1518 if (crq.crq.wLength != cpu_to_le16(0))
1519 ep->state = DATA_STAGE_OUT;
1520 else
1521 ep->state = STATUS_STAGE_IN;
1522 }
1523
1524 ret = -1;
1525 if (ep->index == 0)
1526 ret = handle_ep0_setup(udc, ep, &crq.crq);
1527 else {
1528 spin_unlock(&udc->lock);
1529 ret = udc->driver->setup(&udc->gadget, &crq.crq);
1530 spin_lock(&udc->lock);
1531 }
1532
1533 DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
1534 crq.crq.bRequestType, crq.crq.bRequest,
1535 le16_to_cpu(crq.crq.wLength), ep->state, ret);
1536
1537 if (ret < 0) {
1538 /* Let the host know that we failed */
1539 set_protocol_stall(udc, ep);
1540 }
1541 }
1542 }
1543
1544 static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
1545 {
1546 struct usba_request *req;
1547 u32 epstatus;
1548 u32 epctrl;
1549
1550 epstatus = usba_ep_readl(ep, STA);
1551 epctrl = usba_ep_readl(ep, CTL);
1552
1553 DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
1554
1555 while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1556 DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
1557
1558 if (list_empty(&ep->queue)) {
1559 dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
1560 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1561 return;
1562 }
1563
1564 req = list_entry(ep->queue.next, struct usba_request, queue);
1565
1566 if (req->using_dma) {
1567 /* Send a zero-length packet */
1568 usba_ep_writel(ep, SET_STA,
1569 USBA_TX_PK_RDY);
1570 usba_ep_writel(ep, CTL_DIS,
1571 USBA_TX_PK_RDY);
1572 list_del_init(&req->queue);
1573 submit_next_request(ep);
1574 request_complete(ep, req, 0);
1575 } else {
1576 if (req->submitted)
1577 next_fifo_transaction(ep, req);
1578 else
1579 submit_request(ep, req);
1580
1581 if (req->last_transaction) {
1582 list_del_init(&req->queue);
1583 submit_next_request(ep);
1584 request_complete(ep, req, 0);
1585 }
1586 }
1587
1588 epstatus = usba_ep_readl(ep, STA);
1589 epctrl = usba_ep_readl(ep, CTL);
1590 }
1591 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1592 DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
1593 receive_data(ep);
1594 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1595 }
1596 }
1597
1598 static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
1599 {
1600 struct usba_request *req;
1601 u32 status, control, pending;
1602
1603 status = usba_dma_readl(ep, STATUS);
1604 control = usba_dma_readl(ep, CONTROL);
1605 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1606 ep->last_dma_status = status;
1607 #endif
1608 pending = status & control;
1609 DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
1610
1611 if (status & USBA_DMA_CH_EN) {
1612 dev_err(&udc->pdev->dev,
1613 "DMA_CH_EN is set after transfer is finished!\n");
1614 dev_err(&udc->pdev->dev,
1615 "status=%#08x, pending=%#08x, control=%#08x\n",
1616 status, pending, control);
1617
1618 /*
1619 * try to pretend nothing happened. We might have to
1620 * do something here...
1621 */
1622 }
1623
1624 if (list_empty(&ep->queue))
1625 /* Might happen if a reset comes along at the right moment */
1626 return;
1627
1628 if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
1629 req = list_entry(ep->queue.next, struct usba_request, queue);
1630 usba_update_req(ep, req, status);
1631
1632 list_del_init(&req->queue);
1633 submit_next_request(ep);
1634 request_complete(ep, req, 0);
1635 }
1636 }
1637
1638 static irqreturn_t usba_udc_irq(int irq, void *devid)
1639 {
1640 struct usba_udc *udc = devid;
1641 u32 status;
1642 u32 dma_status;
1643 u32 ep_status;
1644
1645 spin_lock(&udc->lock);
1646
1647 status = usba_readl(udc, INT_STA);
1648 DBG(DBG_INT, "irq, status=%#08x\n", status);
1649
1650 if (status & USBA_DET_SUSPEND) {
1651 toggle_bias(0);
1652 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
1653 DBG(DBG_BUS, "Suspend detected\n");
1654 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1655 && udc->driver && udc->driver->suspend) {
1656 spin_unlock(&udc->lock);
1657 udc->driver->suspend(&udc->gadget);
1658 spin_lock(&udc->lock);
1659 }
1660 }
1661
1662 if (status & USBA_WAKE_UP) {
1663 toggle_bias(1);
1664 usba_writel(udc, INT_CLR, USBA_WAKE_UP);
1665 DBG(DBG_BUS, "Wake Up CPU detected\n");
1666 }
1667
1668 if (status & USBA_END_OF_RESUME) {
1669 usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
1670 DBG(DBG_BUS, "Resume detected\n");
1671 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1672 && udc->driver && udc->driver->resume) {
1673 spin_unlock(&udc->lock);
1674 udc->driver->resume(&udc->gadget);
1675 spin_lock(&udc->lock);
1676 }
1677 }
1678
1679 dma_status = USBA_BFEXT(DMA_INT, status);
1680 if (dma_status) {
1681 int i;
1682
1683 for (i = 1; i < USBA_NR_ENDPOINTS; i++)
1684 if (dma_status & (1 << i))
1685 usba_dma_irq(udc, &usba_ep[i]);
1686 }
1687
1688 ep_status = USBA_BFEXT(EPT_INT, status);
1689 if (ep_status) {
1690 int i;
1691
1692 for (i = 0; i < USBA_NR_ENDPOINTS; i++)
1693 if (ep_status & (1 << i)) {
1694 if (ep_is_control(&usba_ep[i]))
1695 usba_control_irq(udc, &usba_ep[i]);
1696 else
1697 usba_ep_irq(udc, &usba_ep[i]);
1698 }
1699 }
1700
1701 if (status & USBA_END_OF_RESET) {
1702 struct usba_ep *ep0;
1703
1704 usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
1705 reset_all_endpoints(udc);
1706
1707 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1708 && udc->driver->disconnect) {
1709 udc->gadget.speed = USB_SPEED_UNKNOWN;
1710 spin_unlock(&udc->lock);
1711 udc->driver->disconnect(&udc->gadget);
1712 spin_lock(&udc->lock);
1713 }
1714
1715 if (status & USBA_HIGH_SPEED) {
1716 DBG(DBG_BUS, "High-speed bus reset detected\n");
1717 udc->gadget.speed = USB_SPEED_HIGH;
1718 } else {
1719 DBG(DBG_BUS, "Full-speed bus reset detected\n");
1720 udc->gadget.speed = USB_SPEED_FULL;
1721 }
1722
1723 ep0 = &usba_ep[0];
1724 ep0->desc = &usba_ep0_desc;
1725 ep0->state = WAIT_FOR_SETUP;
1726 usba_ep_writel(ep0, CFG,
1727 (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
1728 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
1729 | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
1730 usba_ep_writel(ep0, CTL_ENB,
1731 USBA_EPT_ENABLE | USBA_RX_SETUP);
1732 usba_writel(udc, INT_ENB,
1733 (usba_readl(udc, INT_ENB)
1734 | USBA_BF(EPT_INT, 1)
1735 | USBA_DET_SUSPEND
1736 | USBA_END_OF_RESUME));
1737
1738 /*
1739 * Unclear why we hit this irregularly, e.g. in usbtest,
1740 * but it's clearly harmless...
1741 */
1742 if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
1743 dev_dbg(&udc->pdev->dev,
1744 "ODD: EP0 configuration is invalid!\n");
1745 }
1746
1747 spin_unlock(&udc->lock);
1748
1749 return IRQ_HANDLED;
1750 }
1751
1752 static irqreturn_t usba_vbus_irq(int irq, void *devid)
1753 {
1754 struct usba_udc *udc = devid;
1755 int vbus;
1756
1757 /* debounce */
1758 udelay(10);
1759
1760 spin_lock(&udc->lock);
1761
1762 /* May happen if Vbus pin toggles during probe() */
1763 if (!udc->driver)
1764 goto out;
1765
1766 vbus = gpio_get_value(udc->vbus_pin);
1767 if (vbus != udc->vbus_prev) {
1768 if (vbus) {
1769 toggle_bias(1);
1770 usba_writel(udc, CTRL, USBA_ENABLE_MASK);
1771 usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
1772 } else {
1773 udc->gadget.speed = USB_SPEED_UNKNOWN;
1774 reset_all_endpoints(udc);
1775 toggle_bias(0);
1776 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1777 if (udc->driver->disconnect) {
1778 spin_unlock(&udc->lock);
1779 udc->driver->disconnect(&udc->gadget);
1780 spin_lock(&udc->lock);
1781 }
1782 }
1783 udc->vbus_prev = vbus;
1784 }
1785
1786 out:
1787 spin_unlock(&udc->lock);
1788
1789 return IRQ_HANDLED;
1790 }
1791
1792 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1793 {
1794 struct usba_udc *udc = &the_udc;
1795 unsigned long flags;
1796 int ret;
1797
1798 if (!udc->pdev)
1799 return -ENODEV;
1800
1801 spin_lock_irqsave(&udc->lock, flags);
1802 if (udc->driver) {
1803 spin_unlock_irqrestore(&udc->lock, flags);
1804 return -EBUSY;
1805 }
1806
1807 udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
1808 udc->driver = driver;
1809 udc->gadget.dev.driver = &driver->driver;
1810 spin_unlock_irqrestore(&udc->lock, flags);
1811
1812 clk_enable(udc->pclk);
1813 clk_enable(udc->hclk);
1814
1815 ret = driver->bind(&udc->gadget);
1816 if (ret) {
1817 DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
1818 driver->driver.name, ret);
1819 goto err_driver_bind;
1820 }
1821
1822 DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
1823
1824 udc->vbus_prev = 0;
1825 if (gpio_is_valid(udc->vbus_pin))
1826 enable_irq(gpio_to_irq(udc->vbus_pin));
1827
1828 /* If Vbus is present, enable the controller and wait for reset */
1829 spin_lock_irqsave(&udc->lock, flags);
1830 if (vbus_is_present(udc) && udc->vbus_prev == 0) {
1831 toggle_bias(1);
1832 usba_writel(udc, CTRL, USBA_ENABLE_MASK);
1833 usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
1834 }
1835 spin_unlock_irqrestore(&udc->lock, flags);
1836
1837 return 0;
1838
1839 err_driver_bind:
1840 udc->driver = NULL;
1841 udc->gadget.dev.driver = NULL;
1842 return ret;
1843 }
1844 EXPORT_SYMBOL(usb_gadget_register_driver);
1845
1846 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1847 {
1848 struct usba_udc *udc = &the_udc;
1849 unsigned long flags;
1850
1851 if (!udc->pdev)
1852 return -ENODEV;
1853 if (driver != udc->driver || !driver->unbind)
1854 return -EINVAL;
1855
1856 if (gpio_is_valid(udc->vbus_pin))
1857 disable_irq(gpio_to_irq(udc->vbus_pin));
1858
1859 spin_lock_irqsave(&udc->lock, flags);
1860 udc->gadget.speed = USB_SPEED_UNKNOWN;
1861 reset_all_endpoints(udc);
1862 spin_unlock_irqrestore(&udc->lock, flags);
1863
1864 /* This will also disable the DP pullup */
1865 toggle_bias(0);
1866 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1867
1868 if (udc->driver->disconnect)
1869 udc->driver->disconnect(&udc->gadget);
1870
1871 driver->unbind(&udc->gadget);
1872 udc->gadget.dev.driver = NULL;
1873 udc->driver = NULL;
1874
1875 clk_disable(udc->hclk);
1876 clk_disable(udc->pclk);
1877
1878 DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
1879
1880 return 0;
1881 }
1882 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1883
1884 static int __init usba_udc_probe(struct platform_device *pdev)
1885 {
1886 struct usba_platform_data *pdata = pdev->dev.platform_data;
1887 struct resource *regs, *fifo;
1888 struct clk *pclk, *hclk;
1889 struct usba_udc *udc = &the_udc;
1890 int irq, ret, i;
1891
1892 regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
1893 fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
1894 if (!regs || !fifo || !pdata)
1895 return -ENXIO;
1896
1897 irq = platform_get_irq(pdev, 0);
1898 if (irq < 0)
1899 return irq;
1900
1901 pclk = clk_get(&pdev->dev, "pclk");
1902 if (IS_ERR(pclk))
1903 return PTR_ERR(pclk);
1904 hclk = clk_get(&pdev->dev, "hclk");
1905 if (IS_ERR(hclk)) {
1906 ret = PTR_ERR(hclk);
1907 goto err_get_hclk;
1908 }
1909
1910 spin_lock_init(&udc->lock);
1911 udc->pdev = pdev;
1912 udc->pclk = pclk;
1913 udc->hclk = hclk;
1914 udc->vbus_pin = -ENODEV;
1915
1916 ret = -ENOMEM;
1917 udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
1918 if (!udc->regs) {
1919 dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
1920 goto err_map_regs;
1921 }
1922 dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
1923 (unsigned long)regs->start, udc->regs);
1924 udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
1925 if (!udc->fifo) {
1926 dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
1927 goto err_map_fifo;
1928 }
1929 dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
1930 (unsigned long)fifo->start, udc->fifo);
1931
1932 device_initialize(&udc->gadget.dev);
1933 udc->gadget.dev.parent = &pdev->dev;
1934 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
1935
1936 platform_set_drvdata(pdev, udc);
1937
1938 /* Make sure we start from a clean slate */
1939 clk_enable(pclk);
1940 toggle_bias(0);
1941 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1942 clk_disable(pclk);
1943
1944 usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
1945 GFP_KERNEL);
1946 if (!usba_ep)
1947 goto err_alloc_ep;
1948
1949 the_udc.gadget.ep0 = &usba_ep[0].ep;
1950
1951 INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
1952 usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
1953 usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
1954 usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
1955 usba_ep[0].ep.ops = &usba_ep_ops;
1956 usba_ep[0].ep.name = pdata->ep[0].name;
1957 usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
1958 usba_ep[0].udc = &the_udc;
1959 INIT_LIST_HEAD(&usba_ep[0].queue);
1960 usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
1961 usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
1962 usba_ep[0].index = pdata->ep[0].index;
1963 usba_ep[0].can_dma = pdata->ep[0].can_dma;
1964 usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
1965
1966 for (i = 1; i < pdata->num_ep; i++) {
1967 struct usba_ep *ep = &usba_ep[i];
1968
1969 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
1970 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
1971 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
1972 ep->ep.ops = &usba_ep_ops;
1973 ep->ep.name = pdata->ep[i].name;
1974 ep->ep.maxpacket = pdata->ep[i].fifo_size;
1975 ep->udc = &the_udc;
1976 INIT_LIST_HEAD(&ep->queue);
1977 ep->fifo_size = pdata->ep[i].fifo_size;
1978 ep->nr_banks = pdata->ep[i].nr_banks;
1979 ep->index = pdata->ep[i].index;
1980 ep->can_dma = pdata->ep[i].can_dma;
1981 ep->can_isoc = pdata->ep[i].can_isoc;
1982
1983 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1984 }
1985
1986 ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
1987 if (ret) {
1988 dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
1989 irq, ret);
1990 goto err_request_irq;
1991 }
1992 udc->irq = irq;
1993
1994 ret = device_add(&udc->gadget.dev);
1995 if (ret) {
1996 dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
1997 goto err_device_add;
1998 }
1999
2000 if (gpio_is_valid(pdata->vbus_pin)) {
2001 if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
2002 udc->vbus_pin = pdata->vbus_pin;
2003
2004 ret = request_irq(gpio_to_irq(udc->vbus_pin),
2005 usba_vbus_irq, 0,
2006 "atmel_usba_udc", udc);
2007 if (ret) {
2008 gpio_free(udc->vbus_pin);
2009 udc->vbus_pin = -ENODEV;
2010 dev_warn(&udc->pdev->dev,
2011 "failed to request vbus irq; "
2012 "assuming always on\n");
2013 } else {
2014 disable_irq(gpio_to_irq(udc->vbus_pin));
2015 }
2016 }
2017 }
2018
2019 usba_init_debugfs(udc);
2020 for (i = 1; i < pdata->num_ep; i++)
2021 usba_ep_init_debugfs(udc, &usba_ep[i]);
2022
2023 return 0;
2024
2025 err_device_add:
2026 free_irq(irq, udc);
2027 err_request_irq:
2028 kfree(usba_ep);
2029 err_alloc_ep:
2030 iounmap(udc->fifo);
2031 err_map_fifo:
2032 iounmap(udc->regs);
2033 err_map_regs:
2034 clk_put(hclk);
2035 err_get_hclk:
2036 clk_put(pclk);
2037
2038 platform_set_drvdata(pdev, NULL);
2039
2040 return ret;
2041 }
2042
2043 static int __exit usba_udc_remove(struct platform_device *pdev)
2044 {
2045 struct usba_udc *udc;
2046 int i;
2047 struct usba_platform_data *pdata = pdev->dev.platform_data;
2048
2049 udc = platform_get_drvdata(pdev);
2050
2051 for (i = 1; i < pdata->num_ep; i++)
2052 usba_ep_cleanup_debugfs(&usba_ep[i]);
2053 usba_cleanup_debugfs(udc);
2054
2055 if (gpio_is_valid(udc->vbus_pin))
2056 gpio_free(udc->vbus_pin);
2057
2058 free_irq(udc->irq, udc);
2059 kfree(usba_ep);
2060 iounmap(udc->fifo);
2061 iounmap(udc->regs);
2062 clk_put(udc->hclk);
2063 clk_put(udc->pclk);
2064
2065 device_unregister(&udc->gadget.dev);
2066
2067 return 0;
2068 }
2069
2070 static struct platform_driver udc_driver = {
2071 .remove = __exit_p(usba_udc_remove),
2072 .driver = {
2073 .name = "atmel_usba_udc",
2074 .owner = THIS_MODULE,
2075 },
2076 };
2077
2078 static int __init udc_init(void)
2079 {
2080 return platform_driver_probe(&udc_driver, usba_udc_probe);
2081 }
2082 module_init(udc_init);
2083
2084 static void __exit udc_exit(void)
2085 {
2086 platform_driver_unregister(&udc_driver);
2087 }
2088 module_exit(udc_exit);
2089
2090 MODULE_DESCRIPTION("Atmel USBA UDC driver");
2091 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
2092 MODULE_LICENSE("GPL");
2093 MODULE_ALIAS("platform:atmel_usba_udc");
Linux for Ginger Game Console