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Save sram context after changing MPU, DSP or core clocks
[linux-ginger.git] / drivers / usb / host / isp1760-hcd.c
blob9600a58299db3f8c29ac575fccda0d97dacccbc2
1 /*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
11 */
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/list.h>
16 #include <linux/usb.h>
17 #include <linux/debugfs.h>
18 #include <linux/uaccess.h>
19 #include <linux/io.h>
20 #include <asm/unaligned.h>
21
22 #include "../core/hcd.h"
23 #include "isp1760-hcd.h"
24
25 static struct kmem_cache *qtd_cachep;
26 static struct kmem_cache *qh_cachep;
27
28 struct isp1760_hcd {
29 u32 hcs_params;
30 spinlock_t lock;
31 struct inter_packet_info atl_ints[32];
32 struct inter_packet_info int_ints[32];
33 struct memory_chunk memory_pool[BLOCKS];
34
35 /* periodic schedule support */
36 #define DEFAULT_I_TDPS 1024
37 unsigned periodic_size;
38 unsigned i_thresh;
39 unsigned long reset_done;
40 unsigned long next_statechange;
41 unsigned int devflags;
42 };
43
44 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
45 {
46 return (struct isp1760_hcd *) (hcd->hcd_priv);
47 }
48 static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
49 {
50 return container_of((void *) priv, struct usb_hcd, hcd_priv);
51 }
52
53 /* Section 2.2 Host Controller Capability Registers */
54 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
55 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
56 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
57 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
58 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
59 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
60 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
61
62 /* Section 2.3 Host Controller Operational Registers */
63 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
64 #define CMD_RESET (1<<1) /* reset HC not bus */
65 #define CMD_RUN (1<<0) /* start/stop HC */
66 #define STS_PCD (1<<2) /* port change detect */
67 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
68
69 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
70 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
71 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
72 #define PORT_RESET (1<<8) /* reset port */
73 #define PORT_SUSPEND (1<<7) /* suspend port */
74 #define PORT_RESUME (1<<6) /* resume it */
75 #define PORT_PE (1<<2) /* port enable */
76 #define PORT_CSC (1<<1) /* connect status change */
77 #define PORT_CONNECT (1<<0) /* device connected */
78 #define PORT_RWC_BITS (PORT_CSC)
79
80 struct isp1760_qtd {
81 struct isp1760_qtd *hw_next;
82 u8 packet_type;
83 u8 toggle;
84
85 void *data_buffer;
86 /* the rest is HCD-private */
87 struct list_head qtd_list;
88 struct urb *urb;
89 size_t length;
90
91 /* isp special*/
92 u32 status;
93 #define URB_COMPLETE_NOTIFY (1 << 0)
94 #define URB_ENQUEUED (1 << 1)
95 #define URB_TYPE_ATL (1 << 2)
96 #define URB_TYPE_INT (1 << 3)
97 };
98
99 struct isp1760_qh {
100 /* first part defined by EHCI spec */
101 struct list_head qtd_list;
102 struct isp1760_hcd *priv;
103
104 /* periodic schedule info */
105 unsigned short period; /* polling interval */
106 struct usb_device *dev;
107
108 u32 toggle;
109 u32 ping;
110 };
111
112 #define ehci_port_speed(priv, portsc) (1 << USB_PORT_FEAT_HIGHSPEED)
113
114 static unsigned int isp1760_readl(__u32 __iomem *regs)
115 {
116 return readl(regs);
117 }
118
119 static void isp1760_writel(const unsigned int val, __u32 __iomem *regs)
120 {
121 writel(val, regs);
122 }
123
124 /*
125 * The next two copy via MMIO data to/from the device. memcpy_{to|from}io()
126 * doesn't quite work because some people have to enforce 32-bit access
127 */
128 static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
129 __u32 __iomem *dst, u32 len)
130 {
131 u32 val;
132 u8 *buff8;
133
134 if (!src) {
135 printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
136 return;
137 }
138
139 while (len >= 4) {
140 *src = __raw_readl(dst);
141 len -= 4;
142 src++;
143 dst++;
144 }
145
146 if (!len)
147 return;
148
149 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
150 * allocated.
151 */
152 val = isp1760_readl(dst);
153
154 buff8 = (u8 *)src;
155 while (len) {
156
157 *buff8 = val;
158 val >>= 8;
159 len--;
160 buff8++;
161 }
162 }
163
164 static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src,
165 __u32 __iomem *dst, u32 len)
166 {
167 while (len >= 4) {
168 __raw_writel(*src, dst);
169 len -= 4;
170 src++;
171 dst++;
172 }
173
174 if (!len)
175 return;
176 /* in case we have 3, 2 or 1 by left. The buffer is allocated and the
177 * extra bytes should not be read by the HW
178 */
179
180 __raw_writel(*src, dst);
181 }
182
183 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
184 static void init_memory(struct isp1760_hcd *priv)
185 {
186 int i;
187 u32 payload;
188
189 payload = 0x1000;
190 for (i = 0; i < BLOCK_1_NUM; i++) {
191 priv->memory_pool[i].start = payload;
192 priv->memory_pool[i].size = BLOCK_1_SIZE;
193 priv->memory_pool[i].free = 1;
194 payload += priv->memory_pool[i].size;
195 }
196
197
198 for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) {
199 priv->memory_pool[i].start = payload;
200 priv->memory_pool[i].size = BLOCK_2_SIZE;
201 priv->memory_pool[i].free = 1;
202 payload += priv->memory_pool[i].size;
203 }
204
205
206 for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) {
207 priv->memory_pool[i].start = payload;
208 priv->memory_pool[i].size = BLOCK_3_SIZE;
209 priv->memory_pool[i].free = 1;
210 payload += priv->memory_pool[i].size;
211 }
212
213 BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE);
214 }
215
216 static u32 alloc_mem(struct isp1760_hcd *priv, u32 size)
217 {
218 int i;
219
220 if (!size)
221 return ISP1760_NULL_POINTER;
222
223 for (i = 0; i < BLOCKS; i++) {
224 if (priv->memory_pool[i].size >= size &&
225 priv->memory_pool[i].free) {
226
227 priv->memory_pool[i].free = 0;
228 return priv->memory_pool[i].start;
229 }
230 }
231
232 printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n",
233 size);
234 printk(KERN_ERR "Current memory map:\n");
235 for (i = 0; i < BLOCKS; i++) {
236 printk(KERN_ERR "Pool %2d size %4d status: %d\n",
237 i, priv->memory_pool[i].size,
238 priv->memory_pool[i].free);
239 }
240 /* XXX maybe -ENOMEM could be possible */
241 BUG();
242 return 0;
243 }
244
245 static void free_mem(struct isp1760_hcd *priv, u32 mem)
246 {
247 int i;
248
249 if (mem == ISP1760_NULL_POINTER)
250 return;
251
252 for (i = 0; i < BLOCKS; i++) {
253 if (priv->memory_pool[i].start == mem) {
254
255 BUG_ON(priv->memory_pool[i].free);
256
257 priv->memory_pool[i].free = 1;
258 return ;
259 }
260 }
261
262 printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n",
263 mem);
264 BUG();
265 }
266
267 static void isp1760_init_regs(struct usb_hcd *hcd)
268 {
269 isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG);
270 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
271 HC_ATL_PTD_SKIPMAP_REG);
272 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
273 HC_INT_PTD_SKIPMAP_REG);
274 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
275 HC_ISO_PTD_SKIPMAP_REG);
276
277 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
278 HC_ATL_PTD_DONEMAP_REG);
279 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
280 HC_INT_PTD_DONEMAP_REG);
281 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
282 HC_ISO_PTD_DONEMAP_REG);
283 }
284
285 static int handshake(struct isp1760_hcd *priv, void __iomem *ptr,
286 u32 mask, u32 done, int usec)
287 {
288 u32 result;
289
290 do {
291 result = isp1760_readl(ptr);
292 if (result == ~0)
293 return -ENODEV;
294 result &= mask;
295 if (result == done)
296 return 0;
297 udelay(1);
298 usec--;
299 } while (usec > 0);
300 return -ETIMEDOUT;
301 }
302
303 /* reset a non-running (STS_HALT == 1) controller */
304 static int ehci_reset(struct isp1760_hcd *priv)
305 {
306 int retval;
307 struct usb_hcd *hcd = priv_to_hcd(priv);
308 u32 command = isp1760_readl(hcd->regs + HC_USBCMD);
309
310 command |= CMD_RESET;
311 isp1760_writel(command, hcd->regs + HC_USBCMD);
312 hcd->state = HC_STATE_HALT;
313 priv->next_statechange = jiffies;
314 retval = handshake(priv, hcd->regs + HC_USBCMD,
315 CMD_RESET, 0, 250 * 1000);
316 return retval;
317 }
318
319 static void qh_destroy(struct isp1760_qh *qh)
320 {
321 BUG_ON(!list_empty(&qh->qtd_list));
322 kmem_cache_free(qh_cachep, qh);
323 }
324
325 static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv,
326 gfp_t flags)
327 {
328 struct isp1760_qh *qh;
329
330 qh = kmem_cache_zalloc(qh_cachep, flags);
331 if (!qh)
332 return qh;
333
334 INIT_LIST_HEAD(&qh->qtd_list);
335 qh->priv = priv;
336 return qh;
337 }
338
339 /* magic numbers that can affect system performance */
340 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
341 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
342 #define EHCI_TUNE_RL_TT 0
343 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
344 #define EHCI_TUNE_MULT_TT 1
345 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
346
347 /* one-time init, only for memory state */
348 static int priv_init(struct usb_hcd *hcd)
349 {
350 struct isp1760_hcd *priv = hcd_to_priv(hcd);
351 u32 hcc_params;
352
353 spin_lock_init(&priv->lock);
354
355 /*
356 * hw default: 1K periodic list heads, one per frame.
357 * periodic_size can shrink by USBCMD update if hcc_params allows.
358 */
359 priv->periodic_size = DEFAULT_I_TDPS;
360
361 /* controllers may cache some of the periodic schedule ... */
362 hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS);
363 /* full frame cache */
364 if (HCC_ISOC_CACHE(hcc_params))
365 priv->i_thresh = 8;
366 else /* N microframes cached */
367 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
368
369 return 0;
370 }
371
372 static int isp1760_hc_setup(struct usb_hcd *hcd)
373 {
374 struct isp1760_hcd *priv = hcd_to_priv(hcd);
375 int result;
376 u32 scratch, hwmode;
377
378 /* Setup HW Mode Control: This assumes a level active-low interrupt */
379 hwmode = HW_DATA_BUS_32BIT;
380
381 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
382 hwmode &= ~HW_DATA_BUS_32BIT;
383 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
384 hwmode |= HW_ANA_DIGI_OC;
385 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
386 hwmode |= HW_DACK_POL_HIGH;
387 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
388 hwmode |= HW_DREQ_POL_HIGH;
389 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
390 hwmode |= HW_INTR_HIGH_ACT;
391 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
392 hwmode |= HW_INTR_EDGE_TRIG;
393
394 /*
395 * We have to set this first in case we're in 16-bit mode.
396 * Write it twice to ensure correct upper bits if switching
397 * to 16-bit mode.
398 */
399 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
400 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
401
402 isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG);
403 /* Change bus pattern */
404 scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
405 scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG);
406 if (scratch != 0xdeadbabe) {
407 printk(KERN_ERR "ISP1760: Scratch test failed.\n");
408 return -ENODEV;
409 }
410
411 /* pre reset */
412 isp1760_init_regs(hcd);
413
414 /* reset */
415 isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG);
416 mdelay(100);
417
418 isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG);
419 mdelay(100);
420
421 result = ehci_reset(priv);
422 if (result)
423 return result;
424
425 /* Step 11 passed */
426
427 isp1760_info(priv, "bus width: %d, oc: %s\n",
428 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
429 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
430 "analog" : "digital");
431
432 /* ATL reset */
433 isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL);
434 mdelay(10);
435 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
436
437 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG);
438 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE);
439
440 /*
441 * PORT 1 Control register of the ISP1760 is the OTG control
442 * register on ISP1761. Since there is no OTG or device controller
443 * support in this driver, we use port 1 as a "normal" USB host port on
444 * both chips.
445 */
446 isp1760_writel(PORT1_POWER | PORT1_INIT2,
447 hcd->regs + HC_PORT1_CTRL);
448 mdelay(10);
449
450 priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS);
451
452 return priv_init(hcd);
453 }
454
455 static void isp1760_init_maps(struct usb_hcd *hcd)
456 {
457 /*set last maps, for iso its only 1, else 32 tds bitmap*/
458 isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG);
459 isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG);
460 isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG);
461 }
462
463 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
464 {
465 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG);
466 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
467 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG);
468 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
469 isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG);
470 isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG);
471 /* step 23 passed */
472 }
473
474 static int isp1760_run(struct usb_hcd *hcd)
475 {
476 struct isp1760_hcd *priv = hcd_to_priv(hcd);
477 int retval;
478 u32 temp;
479 u32 command;
480 u32 chipid;
481
482 hcd->uses_new_polling = 1;
483 hcd->poll_rh = 0;
484
485 hcd->state = HC_STATE_RUNNING;
486 isp1760_enable_interrupts(hcd);
487 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
488 isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
489
490 command = isp1760_readl(hcd->regs + HC_USBCMD);
491 command &= ~(CMD_LRESET|CMD_RESET);
492 command |= CMD_RUN;
493 isp1760_writel(command, hcd->regs + HC_USBCMD);
494
495 retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN,
496 250 * 1000);
497 if (retval)
498 return retval;
499
500 /*
501 * XXX
502 * Spec says to write FLAG_CF as last config action, priv code grabs
503 * the semaphore while doing so.
504 */
505 down_write(&ehci_cf_port_reset_rwsem);
506 isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG);
507
508 retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF,
509 250 * 1000);
510 up_write(&ehci_cf_port_reset_rwsem);
511 if (retval)
512 return retval;
513
514 chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
515 isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff,
516 chipid >> 16);
517
518 /* PTD Register Init Part 2, Step 28 */
519 /* enable INTs */
520 isp1760_init_maps(hcd);
521
522 /* GRR this is run-once init(), being done every time the HC starts.
523 * So long as they're part of class devices, we can't do it init()
524 * since the class device isn't created that early.
525 */
526 return 0;
527 }
528
529 static u32 base_to_chip(u32 base)
530 {
531 return ((base - 0x400) >> 3);
532 }
533
534 static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh,
535 struct isp1760_qtd *qtd, struct urb *urb,
536 u32 payload, struct ptd *ptd)
537 {
538 u32 dw0;
539 u32 dw1;
540 u32 dw2;
541 u32 dw3;
542 u32 maxpacket;
543 u32 multi;
544 u32 pid_code;
545 u32 rl = RL_COUNTER;
546 u32 nak = NAK_COUNTER;
547
548 /* according to 3.6.2, max packet len can not be > 0x400 */
549 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
550 multi = 1 + ((maxpacket >> 11) & 0x3);
551 maxpacket &= 0x7ff;
552
553 /* DW0 */
554 dw0 = PTD_VALID;
555 dw0 |= PTD_LENGTH(qtd->length);
556 dw0 |= PTD_MAXPACKET(maxpacket);
557 dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe));
558 dw1 = usb_pipeendpoint(urb->pipe) >> 1;
559
560 /* DW1 */
561 dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe));
562
563 pid_code = qtd->packet_type;
564 dw1 |= PTD_PID_TOKEN(pid_code);
565
566 if (usb_pipebulk(urb->pipe))
567 dw1 |= PTD_TRANS_BULK;
568 else if (usb_pipeint(urb->pipe))
569 dw1 |= PTD_TRANS_INT;
570
571 if (urb->dev->speed != USB_SPEED_HIGH) {
572 /* split transaction */
573
574 dw1 |= PTD_TRANS_SPLIT;
575 if (urb->dev->speed == USB_SPEED_LOW)
576 dw1 |= PTD_SE_USB_LOSPEED;
577
578 dw1 |= PTD_PORT_NUM(urb->dev->ttport);
579 dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum);
580
581 /* SE bit for Split INT transfers */
582 if (usb_pipeint(urb->pipe) &&
583 (urb->dev->speed == USB_SPEED_LOW))
584 dw1 |= 2 << 16;
585
586 dw3 = 0;
587 rl = 0;
588 nak = 0;
589 } else {
590 dw0 |= PTD_MULTI(multi);
591 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe))
592 dw3 = qh->ping;
593 else
594 dw3 = 0;
595 }
596 /* DW2 */
597 dw2 = 0;
598 dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload));
599 dw2 |= PTD_RL_CNT(rl);
600 dw3 |= PTD_NAC_CNT(nak);
601
602 /* DW3 */
603 if (usb_pipecontrol(urb->pipe))
604 dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
605 else
606 dw3 |= qh->toggle;
607
608
609 dw3 |= PTD_ACTIVE;
610 /* Cerr */
611 dw3 |= PTD_CERR(ERR_COUNTER);
612
613 memset(ptd, 0, sizeof(*ptd));
614
615 ptd->dw0 = cpu_to_le32(dw0);
616 ptd->dw1 = cpu_to_le32(dw1);
617 ptd->dw2 = cpu_to_le32(dw2);
618 ptd->dw3 = cpu_to_le32(dw3);
619 }
620
621 static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
622 struct isp1760_qtd *qtd, struct urb *urb,
623 u32 payload, struct ptd *ptd)
624 {
625 u32 maxpacket;
626 u32 multi;
627 u32 numberofusofs;
628 u32 i;
629 u32 usofmask, usof;
630 u32 period;
631
632 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
633 multi = 1 + ((maxpacket >> 11) & 0x3);
634 maxpacket &= 0x7ff;
635 /* length of the data per uframe */
636 maxpacket = multi * maxpacket;
637
638 numberofusofs = urb->transfer_buffer_length / maxpacket;
639 if (urb->transfer_buffer_length % maxpacket)
640 numberofusofs += 1;
641
642 usofmask = 1;
643 usof = 0;
644 for (i = 0; i < numberofusofs; i++) {
645 usof |= usofmask;
646 usofmask <<= 1;
647 }
648
649 if (urb->dev->speed != USB_SPEED_HIGH) {
650 /* split */
651 ptd->dw5 = cpu_to_le32(0x1c);
652
653 if (qh->period >= 32)
654 period = qh->period / 2;
655 else
656 period = qh->period;
657
658 } else {
659
660 if (qh->period >= 8)
661 period = qh->period/8;
662 else
663 period = qh->period;
664
665 if (period >= 32)
666 period = 16;
667
668 if (qh->period >= 8) {
669 /* millisecond period */
670 period = (period << 3);
671 } else {
672 /* usof based tranmsfers */
673 /* minimum 4 usofs */
674 usof = 0x11;
675 }
676 }
677
678 ptd->dw2 |= cpu_to_le32(period);
679 ptd->dw4 = cpu_to_le32(usof);
680 }
681
682 static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
683 struct isp1760_qtd *qtd, struct urb *urb,
684 u32 payload, struct ptd *ptd)
685 {
686 transform_into_atl(priv, qh, qtd, urb, payload, ptd);
687 transform_add_int(priv, qh, qtd, urb, payload, ptd);
688 }
689
690 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
691 u32 token)
692 {
693 int count;
694
695 qtd->data_buffer = databuffer;
696 qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
697 qtd->toggle = GET_DATA_TOGGLE(token);
698
699 if (len > HC_ATL_PL_SIZE)
700 count = HC_ATL_PL_SIZE;
701 else
702 count = len;
703
704 qtd->length = count;
705 return count;
706 }
707
708 static int check_error(struct ptd *ptd)
709 {
710 int error = 0;
711 u32 dw3;
712
713 dw3 = le32_to_cpu(ptd->dw3);
714 if (dw3 & DW3_HALT_BIT)
715 error = -EPIPE;
716
717 if (dw3 & DW3_ERROR_BIT) {
718 printk(KERN_ERR "error bit is set in DW3\n");
719 error = -EPIPE;
720 }
721
722 if (dw3 & DW3_QTD_ACTIVE) {
723 printk(KERN_ERR "transfer active bit is set DW3\n");
724 printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf,
725 (le32_to_cpu(ptd->dw2) >> 25) & 0xf);
726 }
727
728 return error;
729 }
730
731 static void check_int_err_status(u32 dw4)
732 {
733 u32 i;
734
735 dw4 >>= 8;
736
737 for (i = 0; i < 8; i++) {
738 switch (dw4 & 0x7) {
739 case INT_UNDERRUN:
740 printk(KERN_ERR "ERROR: under run , %d\n", i);
741 break;
742
743 case INT_EXACT:
744 printk(KERN_ERR "ERROR: transaction error, %d\n", i);
745 break;
746
747 case INT_BABBLE:
748 printk(KERN_ERR "ERROR: babble error, %d\n", i);
749 break;
750 }
751 dw4 >>= 3;
752 }
753 }
754
755 static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv,
756 u32 payload)
757 {
758 u32 token;
759 struct usb_hcd *hcd = priv_to_hcd(priv);
760
761 token = qtd->packet_type;
762
763 if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) {
764 switch (token) {
765 case IN_PID:
766 break;
767 case OUT_PID:
768 case SETUP_PID:
769 priv_write_copy(priv, qtd->data_buffer,
770 hcd->regs + payload,
771 qtd->length);
772 }
773 }
774 }
775
776 static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload,
777 struct isp1760_hcd *priv, struct isp1760_qh *qh,
778 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
779 {
780 struct ptd ptd;
781 struct usb_hcd *hcd = priv_to_hcd(priv);
782
783 transform_into_atl(priv, qh, qtd, urb, payload, &ptd);
784 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd));
785 enqueue_one_qtd(qtd, priv, payload);
786
787 priv->atl_ints[slot].urb = urb;
788 priv->atl_ints[slot].qh = qh;
789 priv->atl_ints[slot].qtd = qtd;
790 priv->atl_ints[slot].data_buffer = qtd->data_buffer;
791 priv->atl_ints[slot].payload = payload;
792 qtd->status |= URB_ENQUEUED | URB_TYPE_ATL;
793 qtd->status |= slot << 16;
794 }
795
796 static void enqueue_one_int_qtd(u32 int_regs, u32 payload,
797 struct isp1760_hcd *priv, struct isp1760_qh *qh,
798 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
799 {
800 struct ptd ptd;
801 struct usb_hcd *hcd = priv_to_hcd(priv);
802
803 transform_into_int(priv, qh, qtd, urb, payload, &ptd);
804 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd));
805 enqueue_one_qtd(qtd, priv, payload);
806
807 priv->int_ints[slot].urb = urb;
808 priv->int_ints[slot].qh = qh;
809 priv->int_ints[slot].qtd = qtd;
810 priv->int_ints[slot].data_buffer = qtd->data_buffer;
811 priv->int_ints[slot].payload = payload;
812 qtd->status |= URB_ENQUEUED | URB_TYPE_INT;
813 qtd->status |= slot << 16;
814 }
815
816 static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
817 struct isp1760_qtd *qtd)
818 {
819 struct isp1760_hcd *priv = hcd_to_priv(hcd);
820 u32 skip_map, or_map;
821 u32 queue_entry;
822 u32 slot;
823 u32 atl_regs, payload;
824 u32 buffstatus;
825
826 /*
827 * When this function is called from the interrupt handler to enqueue
828 * a follow-up packet, the SKIP register gets written and read back
829 * almost immediately. With ISP1761, this register requires a delay of
830 * 195ns between a write and subsequent read (see section 15.1.1.3).
831 */
832 ndelay(195);
833 skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
834
835 BUG_ON(!skip_map);
836 slot = __ffs(skip_map);
837 queue_entry = 1 << slot;
838
839 atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd);
840
841 payload = alloc_mem(priv, qtd->length);
842
843 enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd);
844
845 or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
846 or_map |= queue_entry;
847 isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
848
849 skip_map &= ~queue_entry;
850 isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
851
852 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
853 buffstatus |= ATL_BUFFER;
854 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
855 }
856
857 static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
858 struct isp1760_qtd *qtd)
859 {
860 struct isp1760_hcd *priv = hcd_to_priv(hcd);
861 u32 skip_map, or_map;
862 u32 queue_entry;
863 u32 slot;
864 u32 int_regs, payload;
865 u32 buffstatus;
866
867 /*
868 * When this function is called from the interrupt handler to enqueue
869 * a follow-up packet, the SKIP register gets written and read back
870 * almost immediately. With ISP1761, this register requires a delay of
871 * 195ns between a write and subsequent read (see section 15.1.1.3).
872 */
873 ndelay(195);
874 skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG);
875
876 BUG_ON(!skip_map);
877 slot = __ffs(skip_map);
878 queue_entry = 1 << slot;
879
880 int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd);
881
882 payload = alloc_mem(priv, qtd->length);
883
884 enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd);
885
886 or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG);
887 or_map |= queue_entry;
888 isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
889
890 skip_map &= ~queue_entry;
891 isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG);
892
893 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
894 buffstatus |= INT_BUFFER;
895 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
896 }
897
898 static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status)
899 __releases(priv->lock)
900 __acquires(priv->lock)
901 {
902 if (!urb->unlinked) {
903 if (status == -EINPROGRESS)
904 status = 0;
905 }
906
907 /* complete() can reenter this HCD */
908 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
909 spin_unlock(&priv->lock);
910 usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status);
911 spin_lock(&priv->lock);
912 }
913
914 static void isp1760_qtd_free(struct isp1760_qtd *qtd)
915 {
916 kmem_cache_free(qtd_cachep, qtd);
917 }
918
919 static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd)
920 {
921 struct isp1760_qtd *tmp_qtd;
922
923 tmp_qtd = qtd->hw_next;
924 list_del(&qtd->qtd_list);
925 isp1760_qtd_free(qtd);
926 return tmp_qtd;
927 }
928
929 /*
930 * Remove this QTD from the QH list and free its memory. If this QTD
931 * isn't the last one than remove also his successor(s).
932 * Returns the QTD which is part of an new URB and should be enqueued.
933 */
934 static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd)
935 {
936 struct isp1760_qtd *tmp_qtd;
937 int last_one;
938
939 do {
940 tmp_qtd = qtd->hw_next;
941 last_one = qtd->status & URB_COMPLETE_NOTIFY;
942 list_del(&qtd->qtd_list);
943 isp1760_qtd_free(qtd);
944 qtd = tmp_qtd;
945 } while (!last_one && qtd);
946
947 return qtd;
948 }
949
950 static void do_atl_int(struct usb_hcd *usb_hcd)
951 {
952 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
953 u32 done_map, skip_map;
954 struct ptd ptd;
955 struct urb *urb = NULL;
956 u32 atl_regs_base;
957 u32 atl_regs;
958 u32 queue_entry;
959 u32 payload;
960 u32 length;
961 u32 or_map;
962 u32 status = -EINVAL;
963 int error;
964 struct isp1760_qtd *qtd;
965 struct isp1760_qh *qh;
966 u32 rl;
967 u32 nakcount;
968
969 done_map = isp1760_readl(usb_hcd->regs +
970 HC_ATL_PTD_DONEMAP_REG);
971 skip_map = isp1760_readl(usb_hcd->regs +
972 HC_ATL_PTD_SKIPMAP_REG);
973
974 or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
975 or_map &= ~done_map;
976 isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
977
978 atl_regs_base = ATL_REGS_OFFSET;
979 while (done_map) {
980 u32 dw1;
981 u32 dw2;
982 u32 dw3;
983
984 status = 0;
985
986 queue_entry = __ffs(done_map);
987 done_map &= ~(1 << queue_entry);
988 skip_map |= 1 << queue_entry;
989
990 atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd);
991
992 urb = priv->atl_ints[queue_entry].urb;
993 qtd = priv->atl_ints[queue_entry].qtd;
994 qh = priv->atl_ints[queue_entry].qh;
995 payload = priv->atl_ints[queue_entry].payload;
996
997 if (!qh) {
998 printk(KERN_ERR "qh is 0\n");
999 continue;
1000 }
1001 isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs +
1002 HC_MEMORY_REG);
1003 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1004 HC_MEMORY_REG);
1005 /*
1006 * write bank1 address twice to ensure the 90ns delay (time
1007 * between BANK0 write and the priv_read_copy() call is at
1008 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns)
1009 */
1010 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1011 HC_MEMORY_REG);
1012
1013 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs +
1014 ISP_BANK(0), sizeof(ptd));
1015
1016 dw1 = le32_to_cpu(ptd.dw1);
1017 dw2 = le32_to_cpu(ptd.dw2);
1018 dw3 = le32_to_cpu(ptd.dw3);
1019 rl = (dw2 >> 25) & 0x0f;
1020 nakcount = (dw3 >> 19) & 0xf;
1021
1022 /* Transfer Error, *but* active and no HALT -> reload */
1023 if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) &&
1024 !(dw3 & DW3_HALT_BIT)) {
1025
1026 /* according to ppriv code, we have to
1027 * reload this one if trasfered bytes != requested bytes
1028 * else act like everything went smooth..
1029 * XXX This just doesn't feel right and hasn't
1030 * triggered so far.
1031 */
1032
1033 length = PTD_XFERRED_LENGTH(dw3);
1034 printk(KERN_ERR "Should reload now.... transfered %d "
1035 "of %zu\n", length, qtd->length);
1036 BUG();
1037 }
1038
1039 if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) {
1040 u32 buffstatus;
1041
1042 /* XXX
1043 * NAKs are handled in HW by the chip. Usually if the
1044 * device is not able to send data fast enough.
1045 * This did not trigger for a long time now.
1046 */
1047 printk(KERN_ERR "Reloading ptd %p/%p... qh %p readed: "
1048 "%d of %zu done: %08x cur: %08x\n", qtd,
1049 urb, qh, PTD_XFERRED_LENGTH(dw3),
1050 qtd->length, done_map,
1051 (1 << queue_entry));
1052
1053 /* RL counter = ERR counter */
1054 dw3 &= ~(0xf << 19);
1055 dw3 |= rl << 19;
1056 dw3 &= ~(3 << (55 - 32));
1057 dw3 |= ERR_COUNTER << (55 - 32);
1058
1059 /*
1060 * It is not needed to write skip map back because it
1061 * is unchanged. Just make sure that this entry is
1062 * unskipped once it gets written to the HW.
1063 */
1064 skip_map &= ~(1 << queue_entry);
1065 or_map = isp1760_readl(usb_hcd->regs +
1066 HC_ATL_IRQ_MASK_OR_REG);
1067 or_map |= 1 << queue_entry;
1068 isp1760_writel(or_map, usb_hcd->regs +
1069 HC_ATL_IRQ_MASK_OR_REG);
1070
1071 ptd.dw3 = cpu_to_le32(dw3);
1072 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
1073 atl_regs, sizeof(ptd));
1074
1075 ptd.dw0 |= cpu_to_le32(PTD_VALID);
1076 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
1077 atl_regs, sizeof(ptd));
1078
1079 buffstatus = isp1760_readl(usb_hcd->regs +
1080 HC_BUFFER_STATUS_REG);
1081 buffstatus |= ATL_BUFFER;
1082 isp1760_writel(buffstatus, usb_hcd->regs +
1083 HC_BUFFER_STATUS_REG);
1084 continue;
1085 }
1086
1087 error = check_error(&ptd);
1088 if (error) {
1089 status = error;
1090 priv->atl_ints[queue_entry].qh->toggle = 0;
1091 priv->atl_ints[queue_entry].qh->ping = 0;
1092 urb->status = -EPIPE;
1093
1094 #if 0
1095 printk(KERN_ERR "Error in %s().\n", __func__);
1096 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1097 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1098 "%08x dw7: %08x\n",
1099 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1100 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1101 #endif
1102 } else {
1103 if (usb_pipetype(urb->pipe) == PIPE_BULK) {
1104 priv->atl_ints[queue_entry].qh->toggle = dw3 &
1105 (1 << 25);
1106 priv->atl_ints[queue_entry].qh->ping = dw3 &
1107 (1 << 26);
1108 }
1109 }
1110
1111 length = PTD_XFERRED_LENGTH(dw3);
1112 if (length) {
1113 switch (DW1_GET_PID(dw1)) {
1114 case IN_PID:
1115 priv_read_copy(priv,
1116 priv->atl_ints[queue_entry].data_buffer,
1117 usb_hcd->regs + payload + ISP_BANK(1),
1118 length);
1119
1120 case OUT_PID:
1121
1122 urb->actual_length += length;
1123
1124 case SETUP_PID:
1125 break;
1126 }
1127 }
1128
1129 priv->atl_ints[queue_entry].data_buffer = NULL;
1130 priv->atl_ints[queue_entry].urb = NULL;
1131 priv->atl_ints[queue_entry].qtd = NULL;
1132 priv->atl_ints[queue_entry].qh = NULL;
1133
1134 free_mem(priv, payload);
1135
1136 isp1760_writel(skip_map, usb_hcd->regs +
1137 HC_ATL_PTD_SKIPMAP_REG);
1138
1139 if (urb->status == -EPIPE) {
1140 /* HALT was received */
1141
1142 qtd = clean_up_qtdlist(qtd);
1143 isp1760_urb_done(priv, urb, urb->status);
1144
1145 } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) {
1146 /* short BULK received */
1147
1148 if (urb->transfer_flags & URB_SHORT_NOT_OK) {
1149 urb->status = -EREMOTEIO;
1150 isp1760_dbg(priv, "short bulk, %d instead %zu "
1151 "with URB_SHORT_NOT_OK flag.\n",
1152 length, qtd->length);
1153 }
1154
1155 if (urb->status == -EINPROGRESS)
1156 urb->status = 0;
1157
1158 qtd = clean_up_qtdlist(qtd);
1159
1160 isp1760_urb_done(priv, urb, urb->status);
1161
1162 } else if (qtd->status & URB_COMPLETE_NOTIFY) {
1163 /* that was the last qtd of that URB */
1164
1165 if (urb->status == -EINPROGRESS)
1166 urb->status = 0;
1167
1168 qtd = clean_this_qtd(qtd);
1169 isp1760_urb_done(priv, urb, urb->status);
1170
1171 } else {
1172 /* next QTD of this URB */
1173
1174 qtd = clean_this_qtd(qtd);
1175 BUG_ON(!qtd);
1176 }
1177
1178 if (qtd)
1179 enqueue_an_ATL_packet(usb_hcd, qh, qtd);
1180
1181 skip_map = isp1760_readl(usb_hcd->regs +
1182 HC_ATL_PTD_SKIPMAP_REG);
1183 }
1184 }
1185
1186 static void do_intl_int(struct usb_hcd *usb_hcd)
1187 {
1188 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
1189 u32 done_map, skip_map;
1190 struct ptd ptd;
1191 struct urb *urb = NULL;
1192 u32 int_regs;
1193 u32 int_regs_base;
1194 u32 payload;
1195 u32 length;
1196 u32 or_map;
1197 int error;
1198 u32 queue_entry;
1199 struct isp1760_qtd *qtd;
1200 struct isp1760_qh *qh;
1201
1202 done_map = isp1760_readl(usb_hcd->regs +
1203 HC_INT_PTD_DONEMAP_REG);
1204 skip_map = isp1760_readl(usb_hcd->regs +
1205 HC_INT_PTD_SKIPMAP_REG);
1206
1207 or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
1208 or_map &= ~done_map;
1209 isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
1210
1211 int_regs_base = INT_REGS_OFFSET;
1212
1213 while (done_map) {
1214 u32 dw1;
1215 u32 dw3;
1216
1217 queue_entry = __ffs(done_map);
1218 done_map &= ~(1 << queue_entry);
1219 skip_map |= 1 << queue_entry;
1220
1221 int_regs = int_regs_base + queue_entry * sizeof(struct ptd);
1222 urb = priv->int_ints[queue_entry].urb;
1223 qtd = priv->int_ints[queue_entry].qtd;
1224 qh = priv->int_ints[queue_entry].qh;
1225 payload = priv->int_ints[queue_entry].payload;
1226
1227 if (!qh) {
1228 printk(KERN_ERR "(INT) qh is 0\n");
1229 continue;
1230 }
1231
1232 isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs +
1233 HC_MEMORY_REG);
1234 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1235 HC_MEMORY_REG);
1236 /*
1237 * write bank1 address twice to ensure the 90ns delay (time
1238 * between BANK0 write and the priv_read_copy() call is at
1239 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
1240 */
1241 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1242 HC_MEMORY_REG);
1243
1244 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs +
1245 ISP_BANK(0), sizeof(ptd));
1246 dw1 = le32_to_cpu(ptd.dw1);
1247 dw3 = le32_to_cpu(ptd.dw3);
1248 check_int_err_status(le32_to_cpu(ptd.dw4));
1249
1250 error = check_error(&ptd);
1251 if (error) {
1252 #if 0
1253 printk(KERN_ERR "Error in %s().\n", __func__);
1254 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1255 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1256 "%08x dw7: %08x\n",
1257 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1258 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1259 #endif
1260 urb->status = -EPIPE;
1261 priv->int_ints[queue_entry].qh->toggle = 0;
1262 priv->int_ints[queue_entry].qh->ping = 0;
1263
1264 } else {
1265 priv->int_ints[queue_entry].qh->toggle =
1266 dw3 & (1 << 25);
1267 priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26);
1268 }
1269
1270 if (urb->dev->speed != USB_SPEED_HIGH)
1271 length = PTD_XFERRED_LENGTH_LO(dw3);
1272 else
1273 length = PTD_XFERRED_LENGTH(dw3);
1274
1275 if (length) {
1276 switch (DW1_GET_PID(dw1)) {
1277 case IN_PID:
1278 priv_read_copy(priv,
1279 priv->int_ints[queue_entry].data_buffer,
1280 usb_hcd->regs + payload + ISP_BANK(1),
1281 length);
1282 case OUT_PID:
1283
1284 urb->actual_length += length;
1285
1286 case SETUP_PID:
1287 break;
1288 }
1289 }
1290
1291 priv->int_ints[queue_entry].data_buffer = NULL;
1292 priv->int_ints[queue_entry].urb = NULL;
1293 priv->int_ints[queue_entry].qtd = NULL;
1294 priv->int_ints[queue_entry].qh = NULL;
1295
1296 isp1760_writel(skip_map, usb_hcd->regs +
1297 HC_INT_PTD_SKIPMAP_REG);
1298 free_mem(priv, payload);
1299
1300 if (urb->status == -EPIPE) {
1301 /* HALT received */
1302
1303 qtd = clean_up_qtdlist(qtd);
1304 isp1760_urb_done(priv, urb, urb->status);
1305
1306 } else if (qtd->status & URB_COMPLETE_NOTIFY) {
1307
1308 if (urb->status == -EINPROGRESS)
1309 urb->status = 0;
1310
1311 qtd = clean_this_qtd(qtd);
1312 isp1760_urb_done(priv, urb, urb->status);
1313
1314 } else {
1315 /* next QTD of this URB */
1316
1317 qtd = clean_this_qtd(qtd);
1318 BUG_ON(!qtd);
1319 }
1320
1321 if (qtd)
1322 enqueue_an_INT_packet(usb_hcd, qh, qtd);
1323
1324 skip_map = isp1760_readl(usb_hcd->regs +
1325 HC_INT_PTD_SKIPMAP_REG);
1326 }
1327 }
1328
1329 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1330 static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
1331 gfp_t flags)
1332 {
1333 struct isp1760_qh *qh;
1334 int is_input, type;
1335
1336 qh = isp1760_qh_alloc(priv, flags);
1337 if (!qh)
1338 return qh;
1339
1340 /*
1341 * init endpoint/device data for this QH
1342 */
1343 is_input = usb_pipein(urb->pipe);
1344 type = usb_pipetype(urb->pipe);
1345
1346 if (type == PIPE_INTERRUPT) {
1347
1348 if (urb->dev->speed == USB_SPEED_HIGH) {
1349
1350 qh->period = urb->interval >> 3;
1351 if (qh->period == 0 && urb->interval != 1) {
1352 /* NOTE interval 2 or 4 uframes could work.
1353 * But interval 1 scheduling is simpler, and
1354 * includes high bandwidth.
1355 */
1356 printk(KERN_ERR "intr period %d uframes, NYET!",
1357 urb->interval);
1358 qh_destroy(qh);
1359 return NULL;
1360 }
1361 } else {
1362 qh->period = urb->interval;
1363 }
1364 }
1365
1366 /* support for tt scheduling, and access to toggles */
1367 qh->dev = urb->dev;
1368
1369 if (!usb_pipecontrol(urb->pipe))
1370 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1371 1);
1372 return qh;
1373 }
1374
1375 /*
1376 * For control/bulk/interrupt, return QH with these TDs appended.
1377 * Allocates and initializes the QH if necessary.
1378 * Returns null if it can't allocate a QH it needs to.
1379 * If the QH has TDs (urbs) already, that's great.
1380 */
1381 static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv,
1382 struct urb *urb, struct list_head *qtd_list, int epnum,
1383 void **ptr)
1384 {
1385 struct isp1760_qh *qh;
1386 struct isp1760_qtd *qtd;
1387 struct isp1760_qtd *prev_qtd;
1388
1389 qh = (struct isp1760_qh *)*ptr;
1390 if (!qh) {
1391 /* can't sleep here, we have priv->lock... */
1392 qh = qh_make(priv, urb, GFP_ATOMIC);
1393 if (!qh)
1394 return qh;
1395 *ptr = qh;
1396 }
1397
1398 qtd = list_entry(qtd_list->next, struct isp1760_qtd,
1399 qtd_list);
1400 if (!list_empty(&qh->qtd_list))
1401 prev_qtd = list_entry(qh->qtd_list.prev,
1402 struct isp1760_qtd, qtd_list);
1403 else
1404 prev_qtd = NULL;
1405
1406 list_splice(qtd_list, qh->qtd_list.prev);
1407 if (prev_qtd) {
1408 BUG_ON(prev_qtd->hw_next);
1409 prev_qtd->hw_next = qtd;
1410 }
1411
1412 urb->hcpriv = qh;
1413 return qh;
1414 }
1415
1416 static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb,
1417 struct list_head *qtd_list)
1418 {
1419 struct list_head *entry, *temp;
1420
1421 list_for_each_safe(entry, temp, qtd_list) {
1422 struct isp1760_qtd *qtd;
1423
1424 qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
1425 list_del(&qtd->qtd_list);
1426 isp1760_qtd_free(qtd);
1427 }
1428 }
1429
1430 static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
1431 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1432 {
1433 struct isp1760_qtd *qtd;
1434 int epnum;
1435 unsigned long flags;
1436 struct isp1760_qh *qh = NULL;
1437 int rc;
1438 int qh_busy;
1439
1440 qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
1441 epnum = urb->ep->desc.bEndpointAddress;
1442
1443 spin_lock_irqsave(&priv->lock, flags);
1444 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &priv_to_hcd(priv)->flags)) {
1445 rc = -ESHUTDOWN;
1446 goto done;
1447 }
1448 rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb);
1449 if (rc)
1450 goto done;
1451
1452 qh = urb->ep->hcpriv;
1453 if (qh)
1454 qh_busy = !list_empty(&qh->qtd_list);
1455 else
1456 qh_busy = 0;
1457
1458 qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv);
1459 if (!qh) {
1460 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
1461 rc = -ENOMEM;
1462 goto done;
1463 }
1464
1465 if (!qh_busy)
1466 p(priv_to_hcd(priv), qh, qtd);
1467
1468 done:
1469 spin_unlock_irqrestore(&priv->lock, flags);
1470 if (!qh)
1471 qtd_list_free(priv, urb, qtd_list);
1472 return rc;
1473 }
1474
1475 static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv,
1476 gfp_t flags)
1477 {
1478 struct isp1760_qtd *qtd;
1479
1480 qtd = kmem_cache_zalloc(qtd_cachep, flags);
1481 if (qtd)
1482 INIT_LIST_HEAD(&qtd->qtd_list);
1483
1484 return qtd;
1485 }
1486
1487 /*
1488 * create a list of filled qtds for this URB; won't link into qh.
1489 */
1490 static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1491 struct urb *urb, struct list_head *head, gfp_t flags)
1492 {
1493 struct isp1760_qtd *qtd, *qtd_prev;
1494 void *buf;
1495 int len, maxpacket;
1496 int is_input;
1497 u32 token;
1498
1499 /*
1500 * URBs map to sequences of QTDs: one logical transaction
1501 */
1502 qtd = isp1760_qtd_alloc(priv, flags);
1503 if (!qtd)
1504 return NULL;
1505
1506 list_add_tail(&qtd->qtd_list, head);
1507 qtd->urb = urb;
1508 urb->status = -EINPROGRESS;
1509
1510 token = 0;
1511 /* for split transactions, SplitXState initialized to zero */
1512
1513 len = urb->transfer_buffer_length;
1514 is_input = usb_pipein(urb->pipe);
1515 if (usb_pipecontrol(urb->pipe)) {
1516 /* SETUP pid */
1517 qtd_fill(qtd, urb->setup_packet,
1518 sizeof(struct usb_ctrlrequest),
1519 token | SETUP_PID);
1520
1521 /* ... and always at least one more pid */
1522 token ^= DATA_TOGGLE;
1523 qtd_prev = qtd;
1524 qtd = isp1760_qtd_alloc(priv, flags);
1525 if (!qtd)
1526 goto cleanup;
1527 qtd->urb = urb;
1528 qtd_prev->hw_next = qtd;
1529 list_add_tail(&qtd->qtd_list, head);
1530
1531 /* for zero length DATA stages, STATUS is always IN */
1532 if (len == 0)
1533 token |= IN_PID;
1534 }
1535
1536 /*
1537 * data transfer stage: buffer setup
1538 */
1539 buf = urb->transfer_buffer;
1540
1541 if (is_input)
1542 token |= IN_PID;
1543 else
1544 token |= OUT_PID;
1545
1546 maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1547
1548 /*
1549 * buffer gets wrapped in one or more qtds;
1550 * last one may be "short" (including zero len)
1551 * and may serve as a control status ack
1552 */
1553 for (;;) {
1554 int this_qtd_len;
1555
1556 if (!buf && len) {
1557 /* XXX This looks like usb storage / SCSI bug */
1558 printk(KERN_ERR "buf is null, dma is %08lx len is %d\n",
1559 (long unsigned)urb->transfer_dma, len);
1560 WARN_ON(1);
1561 }
1562
1563 this_qtd_len = qtd_fill(qtd, buf, len, token);
1564 len -= this_qtd_len;
1565 buf += this_qtd_len;
1566
1567 /* qh makes control packets use qtd toggle; maybe switch it */
1568 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1569 token ^= DATA_TOGGLE;
1570
1571 if (len <= 0)
1572 break;
1573
1574 qtd_prev = qtd;
1575 qtd = isp1760_qtd_alloc(priv, flags);
1576 if (!qtd)
1577 goto cleanup;
1578 qtd->urb = urb;
1579 qtd_prev->hw_next = qtd;
1580 list_add_tail(&qtd->qtd_list, head);
1581 }
1582
1583 /*
1584 * control requests may need a terminating data "status" ack;
1585 * bulk ones may need a terminating short packet (zero length).
1586 */
1587 if (urb->transfer_buffer_length != 0) {
1588 int one_more = 0;
1589
1590 if (usb_pipecontrol(urb->pipe)) {
1591 one_more = 1;
1592 /* "in" <--> "out" */
1593 token ^= IN_PID;
1594 /* force DATA1 */
1595 token |= DATA_TOGGLE;
1596 } else if (usb_pipebulk(urb->pipe)
1597 && (urb->transfer_flags & URB_ZERO_PACKET)
1598 && !(urb->transfer_buffer_length % maxpacket)) {
1599 one_more = 1;
1600 }
1601 if (one_more) {
1602 qtd_prev = qtd;
1603 qtd = isp1760_qtd_alloc(priv, flags);
1604 if (!qtd)
1605 goto cleanup;
1606 qtd->urb = urb;
1607 qtd_prev->hw_next = qtd;
1608 list_add_tail(&qtd->qtd_list, head);
1609
1610 /* never any data in such packets */
1611 qtd_fill(qtd, NULL, 0, token);
1612 }
1613 }
1614
1615 qtd->status = URB_COMPLETE_NOTIFY;
1616 return head;
1617
1618 cleanup:
1619 qtd_list_free(priv, urb, head);
1620 return NULL;
1621 }
1622
1623 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1624 gfp_t mem_flags)
1625 {
1626 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1627 struct list_head qtd_list;
1628 packet_enqueue *pe;
1629
1630 INIT_LIST_HEAD(&qtd_list);
1631
1632 switch (usb_pipetype(urb->pipe)) {
1633 case PIPE_CONTROL:
1634 case PIPE_BULK:
1635
1636 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1637 return -ENOMEM;
1638 pe = enqueue_an_ATL_packet;
1639 break;
1640
1641 case PIPE_INTERRUPT:
1642 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1643 return -ENOMEM;
1644 pe = enqueue_an_INT_packet;
1645 break;
1646
1647 case PIPE_ISOCHRONOUS:
1648 printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n");
1649 default:
1650 return -EPIPE;
1651 }
1652
1653 return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe);
1654 }
1655
1656 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1657 int status)
1658 {
1659 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1660 struct inter_packet_info *ints;
1661 u32 i;
1662 u32 reg_base, or_reg, skip_reg;
1663 unsigned long flags;
1664 struct ptd ptd;
1665 packet_enqueue *pe;
1666
1667 switch (usb_pipetype(urb->pipe)) {
1668 case PIPE_ISOCHRONOUS:
1669 return -EPIPE;
1670 break;
1671
1672 case PIPE_INTERRUPT:
1673 ints = priv->int_ints;
1674 reg_base = INT_REGS_OFFSET;
1675 or_reg = HC_INT_IRQ_MASK_OR_REG;
1676 skip_reg = HC_INT_PTD_SKIPMAP_REG;
1677 pe = enqueue_an_INT_packet;
1678 break;
1679
1680 default:
1681 ints = priv->atl_ints;
1682 reg_base = ATL_REGS_OFFSET;
1683 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1684 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
1685 pe = enqueue_an_ATL_packet;
1686 break;
1687 }
1688
1689 memset(&ptd, 0, sizeof(ptd));
1690 spin_lock_irqsave(&priv->lock, flags);
1691
1692 for (i = 0; i < 32; i++) {
1693 if (ints->urb == urb) {
1694 u32 skip_map;
1695 u32 or_map;
1696 struct isp1760_qtd *qtd;
1697 struct isp1760_qh *qh = ints->qh;
1698
1699 skip_map = isp1760_readl(hcd->regs + skip_reg);
1700 skip_map |= 1 << i;
1701 isp1760_writel(skip_map, hcd->regs + skip_reg);
1702
1703 or_map = isp1760_readl(hcd->regs + or_reg);
1704 or_map &= ~(1 << i);
1705 isp1760_writel(or_map, hcd->regs + or_reg);
1706
1707 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base
1708 + i * sizeof(ptd), sizeof(ptd));
1709 qtd = ints->qtd;
1710 qtd = clean_up_qtdlist(qtd);
1711
1712 free_mem(priv, ints->payload);
1713
1714 ints->urb = NULL;
1715 ints->qh = NULL;
1716 ints->qtd = NULL;
1717 ints->data_buffer = NULL;
1718 ints->payload = 0;
1719
1720 isp1760_urb_done(priv, urb, status);
1721 if (qtd)
1722 pe(hcd, qh, qtd);
1723 break;
1724
1725 } else if (ints->qtd) {
1726 struct isp1760_qtd *qtd, *prev_qtd = ints->qtd;
1727
1728 for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) {
1729 if (qtd->urb == urb) {
1730 prev_qtd->hw_next = clean_up_qtdlist(qtd);
1731 isp1760_urb_done(priv, urb, status);
1732 break;
1733 }
1734 prev_qtd = qtd;
1735 }
1736 /* we found the urb before the end of the list */
1737 if (qtd)
1738 break;
1739 }
1740 ints++;
1741 }
1742
1743 spin_unlock_irqrestore(&priv->lock, flags);
1744 return 0;
1745 }
1746
1747 static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd)
1748 {
1749 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
1750 u32 imask;
1751 irqreturn_t irqret = IRQ_NONE;
1752
1753 spin_lock(&priv->lock);
1754
1755 if (!(usb_hcd->state & HC_STATE_RUNNING))
1756 goto leave;
1757
1758 imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG);
1759 if (unlikely(!imask))
1760 goto leave;
1761
1762 isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG);
1763 if (imask & HC_ATL_INT)
1764 do_atl_int(usb_hcd);
1765
1766 if (imask & HC_INTL_INT)
1767 do_intl_int(usb_hcd);
1768
1769 irqret = IRQ_HANDLED;
1770 leave:
1771 spin_unlock(&priv->lock);
1772 return irqret;
1773 }
1774
1775 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1776 {
1777 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1778 u32 temp, status = 0;
1779 u32 mask;
1780 int retval = 1;
1781 unsigned long flags;
1782
1783 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1784 if (!HC_IS_RUNNING(hcd->state))
1785 return 0;
1786
1787 /* init status to no-changes */
1788 buf[0] = 0;
1789 mask = PORT_CSC;
1790
1791 spin_lock_irqsave(&priv->lock, flags);
1792 temp = isp1760_readl(hcd->regs + HC_PORTSC1);
1793
1794 if (temp & PORT_OWNER) {
1795 if (temp & PORT_CSC) {
1796 temp &= ~PORT_CSC;
1797 isp1760_writel(temp, hcd->regs + HC_PORTSC1);
1798 goto done;
1799 }
1800 }
1801
1802 /*
1803 * Return status information even for ports with OWNER set.
1804 * Otherwise khubd wouldn't see the disconnect event when a
1805 * high-speed device is switched over to the companion
1806 * controller by the user.
1807 */
1808
1809 if ((temp & mask) != 0
1810 || ((temp & PORT_RESUME) != 0
1811 && time_after_eq(jiffies,
1812 priv->reset_done))) {
1813 buf [0] |= 1 << (0 + 1);
1814 status = STS_PCD;
1815 }
1816 /* FIXME autosuspend idle root hubs */
1817 done:
1818 spin_unlock_irqrestore(&priv->lock, flags);
1819 return status ? retval : 0;
1820 }
1821
1822 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1823 struct usb_hub_descriptor *desc)
1824 {
1825 int ports = HCS_N_PORTS(priv->hcs_params);
1826 u16 temp;
1827
1828 desc->bDescriptorType = 0x29;
1829 /* priv 1.0, 2.3.9 says 20ms max */
1830 desc->bPwrOn2PwrGood = 10;
1831 desc->bHubContrCurrent = 0;
1832
1833 desc->bNbrPorts = ports;
1834 temp = 1 + (ports / 8);
1835 desc->bDescLength = 7 + 2 * temp;
1836
1837 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1838 memset(&desc->bitmap[0], 0, temp);
1839 memset(&desc->bitmap[temp], 0xff, temp);
1840
1841 /* per-port overcurrent reporting */
1842 temp = 0x0008;
1843 if (HCS_PPC(priv->hcs_params))
1844 /* per-port power control */
1845 temp |= 0x0001;
1846 else
1847 /* no power switching */
1848 temp |= 0x0002;
1849 desc->wHubCharacteristics = cpu_to_le16(temp);
1850 }
1851
1852 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1853
1854 static int check_reset_complete(struct isp1760_hcd *priv, int index,
1855 u32 __iomem *status_reg, int port_status)
1856 {
1857 if (!(port_status & PORT_CONNECT))
1858 return port_status;
1859
1860 /* if reset finished and it's still not enabled -- handoff */
1861 if (!(port_status & PORT_PE)) {
1862
1863 printk(KERN_ERR "port %d full speed --> companion\n",
1864 index + 1);
1865
1866 port_status |= PORT_OWNER;
1867 port_status &= ~PORT_RWC_BITS;
1868 isp1760_writel(port_status, status_reg);
1869
1870 } else
1871 printk(KERN_ERR "port %d high speed\n", index + 1);
1872
1873 return port_status;
1874 }
1875
1876 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1877 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1878 {
1879 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1880 int ports = HCS_N_PORTS(priv->hcs_params);
1881 u32 __iomem *status_reg = hcd->regs + HC_PORTSC1;
1882 u32 temp, status;
1883 unsigned long flags;
1884 int retval = 0;
1885 unsigned selector;
1886
1887 /*
1888 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1889 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1890 * (track current state ourselves) ... blink for diagnostics,
1891 * power, "this is the one", etc. EHCI spec supports this.
1892 */
1893
1894 spin_lock_irqsave(&priv->lock, flags);
1895 switch (typeReq) {
1896 case ClearHubFeature:
1897 switch (wValue) {
1898 case C_HUB_LOCAL_POWER:
1899 case C_HUB_OVER_CURRENT:
1900 /* no hub-wide feature/status flags */
1901 break;
1902 default:
1903 goto error;
1904 }
1905 break;
1906 case ClearPortFeature:
1907 if (!wIndex || wIndex > ports)
1908 goto error;
1909 wIndex--;
1910 temp = isp1760_readl(status_reg);
1911
1912 /*
1913 * Even if OWNER is set, so the port is owned by the
1914 * companion controller, khubd needs to be able to clear
1915 * the port-change status bits (especially
1916 * USB_PORT_FEAT_C_CONNECTION).
1917 */
1918
1919 switch (wValue) {
1920 case USB_PORT_FEAT_ENABLE:
1921 isp1760_writel(temp & ~PORT_PE, status_reg);
1922 break;
1923 case USB_PORT_FEAT_C_ENABLE:
1924 /* XXX error? */
1925 break;
1926 case USB_PORT_FEAT_SUSPEND:
1927 if (temp & PORT_RESET)
1928 goto error;
1929
1930 if (temp & PORT_SUSPEND) {
1931 if ((temp & PORT_PE) == 0)
1932 goto error;
1933 /* resume signaling for 20 msec */
1934 temp &= ~(PORT_RWC_BITS);
1935 isp1760_writel(temp | PORT_RESUME,
1936 status_reg);
1937 priv->reset_done = jiffies +
1938 msecs_to_jiffies(20);
1939 }
1940 break;
1941 case USB_PORT_FEAT_C_SUSPEND:
1942 /* we auto-clear this feature */
1943 break;
1944 case USB_PORT_FEAT_POWER:
1945 if (HCS_PPC(priv->hcs_params))
1946 isp1760_writel(temp & ~PORT_POWER, status_reg);
1947 break;
1948 case USB_PORT_FEAT_C_CONNECTION:
1949 isp1760_writel(temp | PORT_CSC,
1950 status_reg);
1951 break;
1952 case USB_PORT_FEAT_C_OVER_CURRENT:
1953 /* XXX error ?*/
1954 break;
1955 case USB_PORT_FEAT_C_RESET:
1956 /* GetPortStatus clears reset */
1957 break;
1958 default:
1959 goto error;
1960 }
1961 isp1760_readl(hcd->regs + HC_USBCMD);
1962 break;
1963 case GetHubDescriptor:
1964 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1965 buf);
1966 break;
1967 case GetHubStatus:
1968 /* no hub-wide feature/status flags */
1969 memset(buf, 0, 4);
1970 break;
1971 case GetPortStatus:
1972 if (!wIndex || wIndex > ports)
1973 goto error;
1974 wIndex--;
1975 status = 0;
1976 temp = isp1760_readl(status_reg);
1977
1978 /* wPortChange bits */
1979 if (temp & PORT_CSC)
1980 status |= 1 << USB_PORT_FEAT_C_CONNECTION;
1981
1982
1983 /* whoever resumes must GetPortStatus to complete it!! */
1984 if (temp & PORT_RESUME) {
1985 printk(KERN_ERR "Port resume should be skipped.\n");
1986
1987 /* Remote Wakeup received? */
1988 if (!priv->reset_done) {
1989 /* resume signaling for 20 msec */
1990 priv->reset_done = jiffies
1991 + msecs_to_jiffies(20);
1992 /* check the port again */
1993 mod_timer(&priv_to_hcd(priv)->rh_timer,
1994 priv->reset_done);
1995 }
1996
1997 /* resume completed? */
1998 else if (time_after_eq(jiffies,
1999 priv->reset_done)) {
2000 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
2001 priv->reset_done = 0;
2002
2003 /* stop resume signaling */
2004 temp = isp1760_readl(status_reg);
2005 isp1760_writel(
2006 temp & ~(PORT_RWC_BITS | PORT_RESUME),
2007 status_reg);
2008 retval = handshake(priv, status_reg,
2009 PORT_RESUME, 0, 2000 /* 2msec */);
2010 if (retval != 0) {
2011 isp1760_err(priv,
2012 "port %d resume error %d\n",
2013 wIndex + 1, retval);
2014 goto error;
2015 }
2016 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
2017 }
2018 }
2019
2020 /* whoever resets must GetPortStatus to complete it!! */
2021 if ((temp & PORT_RESET)
2022 && time_after_eq(jiffies,
2023 priv->reset_done)) {
2024 status |= 1 << USB_PORT_FEAT_C_RESET;
2025 priv->reset_done = 0;
2026
2027 /* force reset to complete */
2028 isp1760_writel(temp & ~PORT_RESET,
2029 status_reg);
2030 /* REVISIT: some hardware needs 550+ usec to clear
2031 * this bit; seems too long to spin routinely...
2032 */
2033 retval = handshake(priv, status_reg,
2034 PORT_RESET, 0, 750);
2035 if (retval != 0) {
2036 isp1760_err(priv, "port %d reset error %d\n",
2037 wIndex + 1, retval);
2038 goto error;
2039 }
2040
2041 /* see what we found out */
2042 temp = check_reset_complete(priv, wIndex, status_reg,
2043 isp1760_readl(status_reg));
2044 }
2045 /*
2046 * Even if OWNER is set, there's no harm letting khubd
2047 * see the wPortStatus values (they should all be 0 except
2048 * for PORT_POWER anyway).
2049 */
2050
2051 if (temp & PORT_OWNER)
2052 printk(KERN_ERR "Warning: PORT_OWNER is set\n");
2053
2054 if (temp & PORT_CONNECT) {
2055 status |= 1 << USB_PORT_FEAT_CONNECTION;
2056 /* status may be from integrated TT */
2057 status |= ehci_port_speed(priv, temp);
2058 }
2059 if (temp & PORT_PE)
2060 status |= 1 << USB_PORT_FEAT_ENABLE;
2061 if (temp & (PORT_SUSPEND|PORT_RESUME))
2062 status |= 1 << USB_PORT_FEAT_SUSPEND;
2063 if (temp & PORT_RESET)
2064 status |= 1 << USB_PORT_FEAT_RESET;
2065 if (temp & PORT_POWER)
2066 status |= 1 << USB_PORT_FEAT_POWER;
2067
2068 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2069 break;
2070 case SetHubFeature:
2071 switch (wValue) {
2072 case C_HUB_LOCAL_POWER:
2073 case C_HUB_OVER_CURRENT:
2074 /* no hub-wide feature/status flags */
2075 break;
2076 default:
2077 goto error;
2078 }
2079 break;
2080 case SetPortFeature:
2081 selector = wIndex >> 8;
2082 wIndex &= 0xff;
2083 if (!wIndex || wIndex > ports)
2084 goto error;
2085 wIndex--;
2086 temp = isp1760_readl(status_reg);
2087 if (temp & PORT_OWNER)
2088 break;
2089
2090 /* temp &= ~PORT_RWC_BITS; */
2091 switch (wValue) {
2092 case USB_PORT_FEAT_ENABLE:
2093 isp1760_writel(temp | PORT_PE, status_reg);
2094 break;
2095
2096 case USB_PORT_FEAT_SUSPEND:
2097 if ((temp & PORT_PE) == 0
2098 || (temp & PORT_RESET) != 0)
2099 goto error;
2100
2101 isp1760_writel(temp | PORT_SUSPEND, status_reg);
2102 break;
2103 case USB_PORT_FEAT_POWER:
2104 if (HCS_PPC(priv->hcs_params))
2105 isp1760_writel(temp | PORT_POWER,
2106 status_reg);
2107 break;
2108 case USB_PORT_FEAT_RESET:
2109 if (temp & PORT_RESUME)
2110 goto error;
2111 /* line status bits may report this as low speed,
2112 * which can be fine if this root hub has a
2113 * transaction translator built in.
2114 */
2115 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2116 && PORT_USB11(temp)) {
2117 temp |= PORT_OWNER;
2118 } else {
2119 temp |= PORT_RESET;
2120 temp &= ~PORT_PE;
2121
2122 /*
2123 * caller must wait, then call GetPortStatus
2124 * usb 2.0 spec says 50 ms resets on root
2125 */
2126 priv->reset_done = jiffies +
2127 msecs_to_jiffies(50);
2128 }
2129 isp1760_writel(temp, status_reg);
2130 break;
2131 default:
2132 goto error;
2133 }
2134 isp1760_readl(hcd->regs + HC_USBCMD);
2135 break;
2136
2137 default:
2138 error:
2139 /* "stall" on error */
2140 retval = -EPIPE;
2141 }
2142 spin_unlock_irqrestore(&priv->lock, flags);
2143 return retval;
2144 }
2145
2146 static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd,
2147 struct usb_host_endpoint *ep)
2148 {
2149 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
2150 struct isp1760_qh *qh;
2151 struct isp1760_qtd *qtd;
2152 unsigned long flags;
2153
2154 spin_lock_irqsave(&priv->lock, flags);
2155 qh = ep->hcpriv;
2156 if (!qh)
2157 goto out;
2158
2159 ep->hcpriv = NULL;
2160 do {
2161 /* more than entry might get removed */
2162 if (list_empty(&qh->qtd_list))
2163 break;
2164
2165 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
2166 qtd_list);
2167
2168 if (qtd->status & URB_ENQUEUED) {
2169
2170 spin_unlock_irqrestore(&priv->lock, flags);
2171 isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET);
2172 spin_lock_irqsave(&priv->lock, flags);
2173 } else {
2174 struct urb *urb;
2175
2176 urb = qtd->urb;
2177 clean_up_qtdlist(qtd);
2178 isp1760_urb_done(priv, urb, -ECONNRESET);
2179 }
2180 } while (1);
2181
2182 qh_destroy(qh);
2183 /* remove requests and leak them.
2184 * ATL are pretty fast done, INT could take a while...
2185 * The latter shoule be removed
2186 */
2187 out:
2188 spin_unlock_irqrestore(&priv->lock, flags);
2189 }
2190
2191 static int isp1760_get_frame(struct usb_hcd *hcd)
2192 {
2193 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2194 u32 fr;
2195
2196 fr = isp1760_readl(hcd->regs + HC_FRINDEX);
2197 return (fr >> 3) % priv->periodic_size;
2198 }
2199
2200 static void isp1760_stop(struct usb_hcd *hcd)
2201 {
2202 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2203 u32 temp;
2204
2205 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2206 NULL, 0);
2207 mdelay(20);
2208
2209 spin_lock_irq(&priv->lock);
2210 ehci_reset(priv);
2211 /* Disable IRQ */
2212 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
2213 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
2214 spin_unlock_irq(&priv->lock);
2215
2216 isp1760_writel(0, hcd->regs + HC_CONFIGFLAG);
2217 }
2218
2219 static void isp1760_shutdown(struct usb_hcd *hcd)
2220 {
2221 u32 command, temp;
2222
2223 isp1760_stop(hcd);
2224 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
2225 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
2226
2227 command = isp1760_readl(hcd->regs + HC_USBCMD);
2228 command &= ~CMD_RUN;
2229 isp1760_writel(command, hcd->regs + HC_USBCMD);
2230 }
2231
2232 static const struct hc_driver isp1760_hc_driver = {
2233 .description = "isp1760-hcd",
2234 .product_desc = "NXP ISP1760 USB Host Controller",
2235 .hcd_priv_size = sizeof(struct isp1760_hcd),
2236 .irq = isp1760_irq,
2237 .flags = HCD_MEMORY | HCD_USB2,
2238 .reset = isp1760_hc_setup,
2239 .start = isp1760_run,
2240 .stop = isp1760_stop,
2241 .shutdown = isp1760_shutdown,
2242 .urb_enqueue = isp1760_urb_enqueue,
2243 .urb_dequeue = isp1760_urb_dequeue,
2244 .endpoint_disable = isp1760_endpoint_disable,
2245 .get_frame_number = isp1760_get_frame,
2246 .hub_status_data = isp1760_hub_status_data,
2247 .hub_control = isp1760_hub_control,
2248 };
2249
2250 int __init init_kmem_once(void)
2251 {
2252 qtd_cachep = kmem_cache_create("isp1760_qtd",
2253 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2254 SLAB_MEM_SPREAD, NULL);
2255
2256 if (!qtd_cachep)
2257 return -ENOMEM;
2258
2259 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2260 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2261
2262 if (!qh_cachep) {
2263 kmem_cache_destroy(qtd_cachep);
2264 return -ENOMEM;
2265 }
2266
2267 return 0;
2268 }
2269
2270 void deinit_kmem_cache(void)
2271 {
2272 kmem_cache_destroy(qtd_cachep);
2273 kmem_cache_destroy(qh_cachep);
2274 }
2275
2276 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2277 int irq, unsigned long irqflags,
2278 struct device *dev, const char *busname,
2279 unsigned int devflags)
2280 {
2281 struct usb_hcd *hcd;
2282 struct isp1760_hcd *priv;
2283 int ret;
2284
2285 if (usb_disabled())
2286 return ERR_PTR(-ENODEV);
2287
2288 /* prevent usb-core allocating DMA pages */
2289 dev->dma_mask = NULL;
2290
2291 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2292 if (!hcd)
2293 return ERR_PTR(-ENOMEM);
2294
2295 priv = hcd_to_priv(hcd);
2296 priv->devflags = devflags;
2297 init_memory(priv);
2298 hcd->regs = ioremap(res_start, res_len);
2299 if (!hcd->regs) {
2300 ret = -EIO;
2301 goto err_put;
2302 }
2303
2304 hcd->irq = irq;
2305 hcd->rsrc_start = res_start;
2306 hcd->rsrc_len = res_len;
2307
2308 ret = usb_add_hcd(hcd, irq, irqflags);
2309 if (ret)
2310 goto err_unmap;
2311
2312 return hcd;
2313
2314 err_unmap:
2315 iounmap(hcd->regs);
2316
2317 err_put:
2318 usb_put_hcd(hcd);
2319
2320 return ERR_PTR(ret);
2321 }
2322
2323 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2324 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2325 MODULE_LICENSE("GPL v2");
Linux for Ginger Game Console