arch/arm/mach-l7200/include/mach/sys-clock.h

   1 /****************************************************************************/
   2 /*
   3  *  arch/arm/mach-l7200/include/mach/sys-clock.h
   4  *
   5  *   Registers and  helper functions for the L7200 Link-Up Systems
   6  *   System clocks.
   7  *
   8  *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
   9  *
  10  *  This file is subject to the terms and conditions of the GNU General Public
  11  *  License. See the file COPYING in the main directory of this archive for
  12  *  more details.
  13  */
  14
  15 /****************************************************************************/
  16
  17 #define SYS_CLOCK_OFF   0x00050030  /* Offset from IO_START. */
  18
  19 /* IO_START and IO_BASE are defined in hardware.h */
  20
  21 #define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF)  /* Physical address */
  22 #define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
  23
  24 /* Define the interface to the SYS_CLOCK */
  25
  26 typedef struct
  27 {
  28      unsigned int ENABLE;
  29      unsigned int ESYNC;
  30      unsigned int SELECT;
  31 } sys_clock_interface;
  32
  33 #define SYS_CLOCK   ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
  34
  35 //#define CLOCK_EN    (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
  36 //#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
  37 //#define CLOCK_SEL   (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
  38
  39 /* SYS_CLOCK -> ENABLE */
  40
  41 #define SYN_EN          1<<0
  42 #define B18M_EN         1<<1
  43 #define CLK3M6_EN       1<<2
  44 #define BUART_EN        1<<3
  45 #define CLK18MU_EN      1<<4
  46 #define FIR_EN          1<<5
  47 #define MIRN_EN         1<<6
  48 #define UARTM_EN        1<<7
  49 #define SIBADC_EN       1<<8
  50 #define ALTD_EN         1<<9
  51 #define CLCLK_EN        1<<10
  52
  53 /* SYS_CLOCK -> SELECT */
  54
  55 #define CLK18M_DIV      1<<0
  56 #define MIR_SEL         1<<1
  57 #define SSP_SEL         1<<4
  58 #define MM_DIV          1<<5
  59 #define MM_SEL          1<<6
  60 #define ADC_SEL_2       0<<7
  61 #define ADC_SEL_4       1<<7
  62 #define ADC_SEL_8       3<<7
  63 #define ADC_SEL_16      7<<7
  64 #define ADC_SEL_32      0x0f<<7
  65 #define ADC_SEL_64      0x1f<<7
  66 #define ADC_SEL_128     0x3f<<7
  67 #define ALTD_SEL        1<<13