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First Support on Ginger and OMAP TI
[linux-ginger.git] / arch / arm / mach-omap2 / clock24xx.h
blobd19cf7a7d8db36ef7045edb601b65361709c4ddd
1 /*
2 * linux/arch/arm/mach-omap2/clock24xx.h
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
18
19 #include "clock.h"
20
21 #include "prm.h"
22 #include "cm.h"
23 #include "prm-regbits-24xx.h"
24 #include "cm-regbits-24xx.h"
25 #include "sdrc.h"
26
27 /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
28 #ifdef CONFIG_ARCH_OMAP2420
29 #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
30 #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
31 #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
32 #else
33 #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
34 #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
35 #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
36 #endif
37
38 static unsigned long omap2_table_mpu_recalc(struct clk *clk);
39 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
40 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
41 static unsigned long omap2_sys_clk_recalc(struct clk *clk);
42 static unsigned long omap2_osc_clk_recalc(struct clk *clk);
43 static unsigned long omap2_sys_clk_recalc(struct clk *clk);
44 static unsigned long omap2_dpllcore_recalc(struct clk *clk);
45 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
46
47 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
48 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
49 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
50 */
51 struct prcm_config {
52 unsigned long xtal_speed; /* crystal rate */
53 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
54 unsigned long mpu_speed; /* speed of MPU */
55 unsigned long cm_clksel_mpu; /* mpu divider */
56 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
57 unsigned long cm_clksel_gfx; /* gfx dividers */
58 unsigned long cm_clksel1_core; /* major subsystem dividers */
59 unsigned long cm_clksel1_pll; /* m,n */
60 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
61 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
62 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
63 unsigned char flags;
64 };
65
66 /*
67 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
68 * These configurations are characterized by voltage and speed for clocks.
69 * The device is only validated for certain combinations. One way to express
70 * these combinations is via the 'ratio's' which the clocks operate with
71 * respect to each other. These ratio sets are for a given voltage/DPLL
72 * setting. All configurations can be described by a DPLL setting and a ratio
73 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
74 *
75 * 2430 differs from 2420 in that there are no more phase synchronizers used.
76 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
77 * 2430 (iva2.1, NOdsp, mdm)
78 */
79
80 /* Core fields for cm_clksel, not ratio governed */
81 #define RX_CLKSEL_DSS1 (0x10 << 8)
82 #define RX_CLKSEL_DSS2 (0x0 << 13)
83 #define RX_CLKSEL_SSI (0x5 << 20)
84
85 /*-------------------------------------------------------------------------
86 * Voltage/DPLL ratios
87 *-------------------------------------------------------------------------*/
88
89 /* 2430 Ratio's, 2430-Ratio Config 1 */
90 #define R1_CLKSEL_L3 (4 << 0)
91 #define R1_CLKSEL_L4 (2 << 5)
92 #define R1_CLKSEL_USB (4 << 25)
93 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
94 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
95 R1_CLKSEL_L4 | R1_CLKSEL_L3
96 #define R1_CLKSEL_MPU (2 << 0)
97 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
98 #define R1_CLKSEL_DSP (2 << 0)
99 #define R1_CLKSEL_DSP_IF (2 << 5)
100 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
101 #define R1_CLKSEL_GFX (2 << 0)
102 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
103 #define R1_CLKSEL_MDM (4 << 0)
104 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
105
106 /* 2430-Ratio Config 2 */
107 #define R2_CLKSEL_L3 (6 << 0)
108 #define R2_CLKSEL_L4 (2 << 5)
109 #define R2_CLKSEL_USB (2 << 25)
110 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
111 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
112 R2_CLKSEL_L4 | R2_CLKSEL_L3
113 #define R2_CLKSEL_MPU (2 << 0)
114 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
115 #define R2_CLKSEL_DSP (2 << 0)
116 #define R2_CLKSEL_DSP_IF (3 << 5)
117 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
118 #define R2_CLKSEL_GFX (2 << 0)
119 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
120 #define R2_CLKSEL_MDM (6 << 0)
121 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
122
123 /* 2430-Ratio Bootm (BYPASS) */
124 #define RB_CLKSEL_L3 (1 << 0)
125 #define RB_CLKSEL_L4 (1 << 5)
126 #define RB_CLKSEL_USB (1 << 25)
127 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
128 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
129 RB_CLKSEL_L4 | RB_CLKSEL_L3
130 #define RB_CLKSEL_MPU (1 << 0)
131 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
132 #define RB_CLKSEL_DSP (1 << 0)
133 #define RB_CLKSEL_DSP_IF (1 << 5)
134 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
135 #define RB_CLKSEL_GFX (1 << 0)
136 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
137 #define RB_CLKSEL_MDM (1 << 0)
138 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
139
140 /* 2420 Ratio Equivalents */
141 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
142 #define RXX_CLKSEL_SSI (0x8 << 20)
143
144 /* 2420-PRCM III 532MHz core */
145 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
146 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
147 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
148 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
149 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
150 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
151 RIII_CLKSEL_L3
152 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
153 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
154 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
155 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
156 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
157 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
158 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
159 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
160 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
161 RIII_CLKSEL_DSP
162 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
163 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
164
165 /* 2420-PRCM II 600MHz core */
166 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
167 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
168 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
169 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
170 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
171 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
172 RII_CLKSEL_L4 | RII_CLKSEL_L3
173 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
174 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
175 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
176 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
177 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
178 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
179 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
180 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
181 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
182 RII_CLKSEL_DSP
183 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
184 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
185
186 /* 2420-PRCM I 660MHz core */
187 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
188 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
189 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
190 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
191 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
192 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
193 RI_CLKSEL_L4 | RI_CLKSEL_L3
194 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
195 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
196 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
197 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
198 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
199 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
200 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
201 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
202 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
203 RI_CLKSEL_DSP
204 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
205 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
206
207 /* 2420-PRCM VII (boot) */
208 #define RVII_CLKSEL_L3 (1 << 0)
209 #define RVII_CLKSEL_L4 (1 << 5)
210 #define RVII_CLKSEL_DSS1 (1 << 8)
211 #define RVII_CLKSEL_DSS2 (0 << 13)
212 #define RVII_CLKSEL_VLYNQ (1 << 15)
213 #define RVII_CLKSEL_SSI (1 << 20)
214 #define RVII_CLKSEL_USB (1 << 25)
215
216 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
217 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
218 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
219
220 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
221 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
222
223 #define RVII_CLKSEL_DSP (1 << 0)
224 #define RVII_CLKSEL_DSP_IF (1 << 5)
225 #define RVII_SYNC_DSP (0 << 7)
226 #define RVII_CLKSEL_IVA (1 << 8)
227 #define RVII_SYNC_IVA (0 << 13)
228 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
229 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
230
231 #define RVII_CLKSEL_GFX (1 << 0)
232 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
233
234 /*-------------------------------------------------------------------------
235 * 2430 Target modes: Along with each configuration the CPU has several
236 * modes which goes along with them. Modes mainly are the addition of
237 * describe DPLL combinations to go along with a ratio.
238 *-------------------------------------------------------------------------*/
239
240 /* Hardware governed */
241 #define MX_48M_SRC (0 << 3)
242 #define MX_54M_SRC (0 << 5)
243 #define MX_APLLS_CLIKIN_12 (3 << 23)
244 #define MX_APLLS_CLIKIN_13 (2 << 23)
245 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
246
247 /*
248 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
249 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
250 */
251 #define M5A_DPLL_MULT_12 (133 << 12)
252 #define M5A_DPLL_DIV_12 (5 << 8)
253 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
254 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
255 MX_APLLS_CLIKIN_12
256 #define M5A_DPLL_MULT_13 (61 << 12)
257 #define M5A_DPLL_DIV_13 (2 << 8)
258 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
259 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
260 MX_APLLS_CLIKIN_13
261 #define M5A_DPLL_MULT_19 (55 << 12)
262 #define M5A_DPLL_DIV_19 (3 << 8)
263 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
264 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
265 MX_APLLS_CLIKIN_19_2
266 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
267 #define M5B_DPLL_MULT_12 (50 << 12)
268 #define M5B_DPLL_DIV_12 (2 << 8)
269 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
270 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
271 MX_APLLS_CLIKIN_12
272 #define M5B_DPLL_MULT_13 (200 << 12)
273 #define M5B_DPLL_DIV_13 (12 << 8)
274
275 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
276 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
277 MX_APLLS_CLIKIN_13
278 #define M5B_DPLL_MULT_19 (125 << 12)
279 #define M5B_DPLL_DIV_19 (31 << 8)
280 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
281 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
282 MX_APLLS_CLIKIN_19_2
283 /*
284 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
285 */
286 #define M4_DPLL_MULT_12 (133 << 12)
287 #define M4_DPLL_DIV_12 (3 << 8)
288 #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
289 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
290 MX_APLLS_CLIKIN_12
291
292 #define M4_DPLL_MULT_13 (399 << 12)
293 #define M4_DPLL_DIV_13 (12 << 8)
294 #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
295 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
296 MX_APLLS_CLIKIN_13
297
298 #define M4_DPLL_MULT_19 (145 << 12)
299 #define M4_DPLL_DIV_19 (6 << 8)
300 #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
301 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
302 MX_APLLS_CLIKIN_19_2
303
304 /*
305 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
306 */
307 #define M3_DPLL_MULT_12 (55 << 12)
308 #define M3_DPLL_DIV_12 (1 << 8)
309 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
310 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
311 MX_APLLS_CLIKIN_12
312 #define M3_DPLL_MULT_13 (76 << 12)
313 #define M3_DPLL_DIV_13 (2 << 8)
314 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
315 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
316 MX_APLLS_CLIKIN_13
317 #define M3_DPLL_MULT_19 (17 << 12)
318 #define M3_DPLL_DIV_19 (0 << 8)
319 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
320 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
321 MX_APLLS_CLIKIN_19_2
322
323 /*
324 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
325 */
326 #define M2_DPLL_MULT_12 (55 << 12)
327 #define M2_DPLL_DIV_12 (1 << 8)
328 #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
329 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
330 MX_APLLS_CLIKIN_12
331
332 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
333 * relock time issue */
334 /* Core frequency changed from 330/165 to 329/164 MHz*/
335 #define M2_DPLL_MULT_13 (76 << 12)
336 #define M2_DPLL_DIV_13 (2 << 8)
337 #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
338 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
339 MX_APLLS_CLIKIN_13
340
341 #define M2_DPLL_MULT_19 (17 << 12)
342 #define M2_DPLL_DIV_19 (0 << 8)
343 #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
344 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
345 MX_APLLS_CLIKIN_19_2
346
347 /* boot (boot) */
348 #define MB_DPLL_MULT (1 << 12)
349 #define MB_DPLL_DIV (0 << 8)
350 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
351 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
352
353 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
354 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
355
356 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
357 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
358
359 /*
360 * 2430 - chassis (sedna)
361 * 165 (ratio1) same as above #2
362 * 150 (ratio1)
363 * 133 (ratio2) same as above #4
364 * 110 (ratio2) same as above #3
365 * 104 (ratio2)
366 * boot (boot)
367 */
368
369 /* PRCM I target DPLL = 2*330MHz = 660MHz */
370 #define MI_DPLL_MULT_12 (55 << 12)
371 #define MI_DPLL_DIV_12 (1 << 8)
372 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
373 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
374 MX_APLLS_CLIKIN_12
375
376 /*
377 * 2420 Equivalent - mode registers
378 * PRCM II , target DPLL = 2*300MHz = 600MHz
379 */
380 #define MII_DPLL_MULT_12 (50 << 12)
381 #define MII_DPLL_DIV_12 (1 << 8)
382 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
383 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
384 MX_APLLS_CLIKIN_12
385 #define MII_DPLL_MULT_13 (300 << 12)
386 #define MII_DPLL_DIV_13 (12 << 8)
387 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
388 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
389 MX_APLLS_CLIKIN_13
390
391 /* PRCM III target DPLL = 2*266 = 532MHz*/
392 #define MIII_DPLL_MULT_12 (133 << 12)
393 #define MIII_DPLL_DIV_12 (5 << 8)
394 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
395 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
396 MX_APLLS_CLIKIN_12
397 #define MIII_DPLL_MULT_13 (266 << 12)
398 #define MIII_DPLL_DIV_13 (12 << 8)
399 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
400 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
401 MX_APLLS_CLIKIN_13
402
403 /* PRCM VII (boot bypass) */
404 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
405 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
406
407 /* High and low operation value */
408 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
409 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
410
411 /* MPU speed defines */
412 #define S12M 12000000
413 #define S13M 13000000
414 #define S19M 19200000
415 #define S26M 26000000
416 #define S100M 100000000
417 #define S133M 133000000
418 #define S150M 150000000
419 #define S164M 164000000
420 #define S165M 165000000
421 #define S199M 199000000
422 #define S200M 200000000
423 #define S266M 266000000
424 #define S300M 300000000
425 #define S329M 329000000
426 #define S330M 330000000
427 #define S399M 399000000
428 #define S400M 400000000
429 #define S532M 532000000
430 #define S600M 600000000
431 #define S658M 658000000
432 #define S660M 660000000
433 #define S798M 798000000
434
435 /*-------------------------------------------------------------------------
436 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
437 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
438 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
439 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
440 *
441 * Filling in table based on H4 boards and 2430-SDPs variants available.
442 * There are quite a few more rates combinations which could be defined.
443 *
444 * When multiple values are defined the start up will try and choose the
445 * fastest one. If a 'fast' value is defined, then automatically, the /2
446 * one should be included as it can be used. Generally having more that
447 * one fast set does not make sense, as static timings need to be changed
448 * to change the set. The exception is the bypass setting which is
449 * availble for low power bypass.
450 *
451 * Note: This table needs to be sorted, fastest to slowest.
452 *-------------------------------------------------------------------------*/
453 static struct prcm_config rate_table[] = {
454 /* PRCM I - FAST */
455 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
456 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
457 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
458 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
459 RATE_IN_242X},
460
461 /* PRCM II - FAST */
462 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
463 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
464 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
465 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
466 RATE_IN_242X},
467
468 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
469 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
470 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
471 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
472 RATE_IN_242X},
473
474 /* PRCM III - FAST */
475 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
476 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
477 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
478 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
479 RATE_IN_242X},
480
481 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
482 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
483 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
484 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
485 RATE_IN_242X},
486
487 /* PRCM II - SLOW */
488 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
489 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
490 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
491 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
492 RATE_IN_242X},
493
494 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
495 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
496 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
497 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
498 RATE_IN_242X},
499
500 /* PRCM III - SLOW */
501 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
502 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
503 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
504 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
505 RATE_IN_242X},
506
507 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
508 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
509 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
510 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
511 RATE_IN_242X},
512
513 /* PRCM-VII (boot-bypass) */
514 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
515 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
516 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
517 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
518 RATE_IN_242X},
519
520 /* PRCM-VII (boot-bypass) */
521 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
522 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
523 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
524 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
525 RATE_IN_242X},
526
527 /* PRCM #4 - ratio2 (ES2.1) - FAST */
528 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
529 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
530 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
531 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
532 SDRC_RFR_CTRL_133MHz,
533 RATE_IN_243X},
534
535 /* PRCM #2 - ratio1 (ES2) - FAST */
536 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
537 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
538 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
539 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
540 SDRC_RFR_CTRL_165MHz,
541 RATE_IN_243X},
542
543 /* PRCM #5a - ratio1 - FAST */
544 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
545 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
546 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
547 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
548 SDRC_RFR_CTRL_133MHz,
549 RATE_IN_243X},
550
551 /* PRCM #5b - ratio1 - FAST */
552 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
553 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
554 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
555 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
556 SDRC_RFR_CTRL_100MHz,
557 RATE_IN_243X},
558
559 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
560 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
561 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
562 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
563 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
564 SDRC_RFR_CTRL_133MHz,
565 RATE_IN_243X},
566
567 /* PRCM #2 - ratio1 (ES2) - SLOW */
568 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
569 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
570 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
571 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
572 SDRC_RFR_CTRL_165MHz,
573 RATE_IN_243X},
574
575 /* PRCM #5a - ratio1 - SLOW */
576 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
577 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
578 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
579 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
580 SDRC_RFR_CTRL_133MHz,
581 RATE_IN_243X},
582
583 /* PRCM #5b - ratio1 - SLOW*/
584 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
585 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
586 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
587 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
588 SDRC_RFR_CTRL_100MHz,
589 RATE_IN_243X},
590
591 /* PRCM-boot/bypass */
592 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
593 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
594 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
595 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
596 SDRC_RFR_CTRL_BYPASS,
597 RATE_IN_243X},
598
599 /* PRCM-boot/bypass */
600 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
601 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
602 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
603 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
604 SDRC_RFR_CTRL_BYPASS,
605 RATE_IN_243X},
606
607 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
608 };
609
610 /*-------------------------------------------------------------------------
611 * 24xx clock tree.
612 *
613 * NOTE:In many cases here we are assigning a 'default' parent. In many
614 * cases the parent is selectable. The get/set parent calls will also
615 * switch sources.
616 *
617 * Many some clocks say always_enabled, but they can be auto idled for
618 * power savings. They will always be available upon clock request.
619 *
620 * Several sources are given initial rates which may be wrong, this will
621 * be fixed up in the init func.
622 *
623 * Things are broadly separated below by clock domains. It is
624 * noteworthy that most periferals have dependencies on multiple clock
625 * domains. Many get their interface clocks from the L4 domain, but get
626 * functional clocks from fixed sources or other core domain derived
627 * clocks.
628 *-------------------------------------------------------------------------*/
629
630 /* Base external input clocks */
631 static struct clk func_32k_ck = {
632 .name = "func_32k_ck",
633 .ops = &clkops_null,
634 .rate = 32000,
635 .flags = RATE_FIXED,
636 .clkdm_name = "wkup_clkdm",
637 };
638
639 static struct clk secure_32k_ck = {
640 .name = "secure_32k_ck",
641 .ops = &clkops_null,
642 .rate = 32768,
643 .flags = RATE_FIXED,
644 .clkdm_name = "wkup_clkdm",
645 };
646
647 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
648 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
649 .name = "osc_ck",
650 .ops = &clkops_oscck,
651 .clkdm_name = "wkup_clkdm",
652 .recalc = &omap2_osc_clk_recalc,
653 };
654
655 /* Without modem likely 12MHz, with modem likely 13MHz */
656 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
657 .name = "sys_ck", /* ~ ref_clk also */
658 .ops = &clkops_null,
659 .parent = &osc_ck,
660 .clkdm_name = "wkup_clkdm",
661 .recalc = &omap2_sys_clk_recalc,
662 };
663
664 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
665 .name = "alt_ck",
666 .ops = &clkops_null,
667 .rate = 54000000,
668 .flags = RATE_FIXED,
669 .clkdm_name = "wkup_clkdm",
670 };
671
672 /*
673 * Analog domain root source clocks
674 */
675
676 /* dpll_ck, is broken out in to special cases through clksel */
677 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
678 * deal with this
679 */
680
681 static struct dpll_data dpll_dd = {
682 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
683 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
684 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
685 .clk_bypass = &sys_ck,
686 .clk_ref = &sys_ck,
687 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
688 .enable_mask = OMAP24XX_EN_DPLL_MASK,
689 .max_multiplier = 1024,
690 .min_divider = 1,
691 .max_divider = 16,
692 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
693 };
694
695 /*
696 * XXX Cannot add round_rate here yet, as this is still a composite clock,
697 * not just a DPLL
698 */
699 static struct clk dpll_ck = {
700 .name = "dpll_ck",
701 .ops = &clkops_null,
702 .parent = &sys_ck, /* Can be func_32k also */
703 .dpll_data = &dpll_dd,
704 .clkdm_name = "wkup_clkdm",
705 .recalc = &omap2_dpllcore_recalc,
706 .set_rate = &omap2_reprogram_dpllcore,
707 };
708
709 static struct clk apll96_ck = {
710 .name = "apll96_ck",
711 .ops = &clkops_fixed,
712 .parent = &sys_ck,
713 .rate = 96000000,
714 .flags = RATE_FIXED | ENABLE_ON_INIT,
715 .clkdm_name = "wkup_clkdm",
716 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
717 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
718 };
719
720 static struct clk apll54_ck = {
721 .name = "apll54_ck",
722 .ops = &clkops_fixed,
723 .parent = &sys_ck,
724 .rate = 54000000,
725 .flags = RATE_FIXED | ENABLE_ON_INIT,
726 .clkdm_name = "wkup_clkdm",
727 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
728 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
729 };
730
731 /*
732 * PRCM digital base sources
733 */
734
735 /* func_54m_ck */
736
737 static const struct clksel_rate func_54m_apll54_rates[] = {
738 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
739 { .div = 0 },
740 };
741
742 static const struct clksel_rate func_54m_alt_rates[] = {
743 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
744 { .div = 0 },
745 };
746
747 static const struct clksel func_54m_clksel[] = {
748 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
749 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
750 { .parent = NULL },
751 };
752
753 static struct clk func_54m_ck = {
754 .name = "func_54m_ck",
755 .ops = &clkops_null,
756 .parent = &apll54_ck, /* can also be alt_clk */
757 .clkdm_name = "wkup_clkdm",
758 .init = &omap2_init_clksel_parent,
759 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
760 .clksel_mask = OMAP24XX_54M_SOURCE,
761 .clksel = func_54m_clksel,
762 .recalc = &omap2_clksel_recalc,
763 };
764
765 static struct clk core_ck = {
766 .name = "core_ck",
767 .ops = &clkops_null,
768 .parent = &dpll_ck, /* can also be 32k */
769 .clkdm_name = "wkup_clkdm",
770 .recalc = &followparent_recalc,
771 };
772
773 /* func_96m_ck */
774 static const struct clksel_rate func_96m_apll96_rates[] = {
775 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
776 { .div = 0 },
777 };
778
779 static const struct clksel_rate func_96m_alt_rates[] = {
780 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
781 { .div = 0 },
782 };
783
784 static const struct clksel func_96m_clksel[] = {
785 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
786 { .parent = &alt_ck, .rates = func_96m_alt_rates },
787 { .parent = NULL }
788 };
789
790 /* The parent of this clock is not selectable on 2420. */
791 static struct clk func_96m_ck = {
792 .name = "func_96m_ck",
793 .ops = &clkops_null,
794 .parent = &apll96_ck,
795 .clkdm_name = "wkup_clkdm",
796 .init = &omap2_init_clksel_parent,
797 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
798 .clksel_mask = OMAP2430_96M_SOURCE,
799 .clksel = func_96m_clksel,
800 .recalc = &omap2_clksel_recalc,
801 .round_rate = &omap2_clksel_round_rate,
802 .set_rate = &omap2_clksel_set_rate
803 };
804
805 /* func_48m_ck */
806
807 static const struct clksel_rate func_48m_apll96_rates[] = {
808 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
809 { .div = 0 },
810 };
811
812 static const struct clksel_rate func_48m_alt_rates[] = {
813 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
814 { .div = 0 },
815 };
816
817 static const struct clksel func_48m_clksel[] = {
818 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
819 { .parent = &alt_ck, .rates = func_48m_alt_rates },
820 { .parent = NULL }
821 };
822
823 static struct clk func_48m_ck = {
824 .name = "func_48m_ck",
825 .ops = &clkops_null,
826 .parent = &apll96_ck, /* 96M or Alt */
827 .clkdm_name = "wkup_clkdm",
828 .init = &omap2_init_clksel_parent,
829 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
830 .clksel_mask = OMAP24XX_48M_SOURCE,
831 .clksel = func_48m_clksel,
832 .recalc = &omap2_clksel_recalc,
833 .round_rate = &omap2_clksel_round_rate,
834 .set_rate = &omap2_clksel_set_rate
835 };
836
837 static struct clk func_12m_ck = {
838 .name = "func_12m_ck",
839 .ops = &clkops_null,
840 .parent = &func_48m_ck,
841 .fixed_div = 4,
842 .clkdm_name = "wkup_clkdm",
843 .recalc = &omap2_fixed_divisor_recalc,
844 };
845
846 /* Secure timer, only available in secure mode */
847 static struct clk wdt1_osc_ck = {
848 .name = "ck_wdt1_osc",
849 .ops = &clkops_null, /* RMK: missing? */
850 .parent = &osc_ck,
851 .recalc = &followparent_recalc,
852 };
853
854 /*
855 * The common_clkout* clksel_rate structs are common to
856 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
857 * sys_clkout2_* are 2420-only, so the
858 * clksel_rate flags fields are inaccurate for those clocks. This is
859 * harmless since access to those clocks are gated by the struct clk
860 * flags fields, which mark them as 2420-only.
861 */
862 static const struct clksel_rate common_clkout_src_core_rates[] = {
863 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
864 { .div = 0 }
865 };
866
867 static const struct clksel_rate common_clkout_src_sys_rates[] = {
868 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
869 { .div = 0 }
870 };
871
872 static const struct clksel_rate common_clkout_src_96m_rates[] = {
873 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
874 { .div = 0 }
875 };
876
877 static const struct clksel_rate common_clkout_src_54m_rates[] = {
878 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
879 { .div = 0 }
880 };
881
882 static const struct clksel common_clkout_src_clksel[] = {
883 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
884 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
885 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
886 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
887 { .parent = NULL }
888 };
889
890 static struct clk sys_clkout_src = {
891 .name = "sys_clkout_src",
892 .ops = &clkops_omap2_dflt,
893 .parent = &func_54m_ck,
894 .clkdm_name = "wkup_clkdm",
895 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
896 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
897 .init = &omap2_init_clksel_parent,
898 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
899 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
900 .clksel = common_clkout_src_clksel,
901 .recalc = &omap2_clksel_recalc,
902 .round_rate = &omap2_clksel_round_rate,
903 .set_rate = &omap2_clksel_set_rate
904 };
905
906 static const struct clksel_rate common_clkout_rates[] = {
907 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
908 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
909 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
910 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
911 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
912 { .div = 0 },
913 };
914
915 static const struct clksel sys_clkout_clksel[] = {
916 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
917 { .parent = NULL }
918 };
919
920 static struct clk sys_clkout = {
921 .name = "sys_clkout",
922 .ops = &clkops_null,
923 .parent = &sys_clkout_src,
924 .clkdm_name = "wkup_clkdm",
925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
927 .clksel = sys_clkout_clksel,
928 .recalc = &omap2_clksel_recalc,
929 .round_rate = &omap2_clksel_round_rate,
930 .set_rate = &omap2_clksel_set_rate
931 };
932
933 /* In 2430, new in 2420 ES2 */
934 static struct clk sys_clkout2_src = {
935 .name = "sys_clkout2_src",
936 .ops = &clkops_omap2_dflt,
937 .parent = &func_54m_ck,
938 .clkdm_name = "wkup_clkdm",
939 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
940 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
941 .init = &omap2_init_clksel_parent,
942 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
943 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
944 .clksel = common_clkout_src_clksel,
945 .recalc = &omap2_clksel_recalc,
946 .round_rate = &omap2_clksel_round_rate,
947 .set_rate = &omap2_clksel_set_rate
948 };
949
950 static const struct clksel sys_clkout2_clksel[] = {
951 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
952 { .parent = NULL }
953 };
954
955 /* In 2430, new in 2420 ES2 */
956 static struct clk sys_clkout2 = {
957 .name = "sys_clkout2",
958 .ops = &clkops_null,
959 .parent = &sys_clkout2_src,
960 .clkdm_name = "wkup_clkdm",
961 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
962 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
963 .clksel = sys_clkout2_clksel,
964 .recalc = &omap2_clksel_recalc,
965 .round_rate = &omap2_clksel_round_rate,
966 .set_rate = &omap2_clksel_set_rate
967 };
968
969 static struct clk emul_ck = {
970 .name = "emul_ck",
971 .ops = &clkops_omap2_dflt,
972 .parent = &func_54m_ck,
973 .clkdm_name = "wkup_clkdm",
974 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
975 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
976 .recalc = &followparent_recalc,
977
978 };
979
980 /*
981 * MPU clock domain
982 * Clocks:
983 * MPU_FCLK, MPU_ICLK
984 * INT_M_FCLK, INT_M_I_CLK
985 *
986 * - Individual clocks are hardware managed.
987 * - Base divider comes from: CM_CLKSEL_MPU
988 *
989 */
990 static const struct clksel_rate mpu_core_rates[] = {
991 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
992 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
993 { .div = 4, .val = 4, .flags = RATE_IN_242X },
994 { .div = 6, .val = 6, .flags = RATE_IN_242X },
995 { .div = 8, .val = 8, .flags = RATE_IN_242X },
996 { .div = 0 },
997 };
998
999 static const struct clksel mpu_clksel[] = {
1000 { .parent = &core_ck, .rates = mpu_core_rates },
1001 { .parent = NULL }
1002 };
1003
1004 static struct clk mpu_ck = { /* Control cpu */
1005 .name = "mpu_ck",
1006 .ops = &clkops_null,
1007 .parent = &core_ck,
1008 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1009 .clkdm_name = "mpu_clkdm",
1010 .init = &omap2_init_clksel_parent,
1011 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1012 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
1013 .clksel = mpu_clksel,
1014 .recalc = &omap2_clksel_recalc,
1015 .round_rate = &omap2_clksel_round_rate,
1016 .set_rate = &omap2_clksel_set_rate
1017 };
1018
1019 /*
1020 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1021 * Clocks:
1022 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1023 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1024 *
1025 * Won't be too specific here. The core clock comes into this block
1026 * it is divided then tee'ed. One branch goes directly to xyz enable
1027 * controls. The other branch gets further divided by 2 then possibly
1028 * routed into a synchronizer and out of clocks abc.
1029 */
1030 static const struct clksel_rate dsp_fck_core_rates[] = {
1031 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1032 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1033 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1034 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1035 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1036 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1037 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1038 { .div = 0 },
1039 };
1040
1041 static const struct clksel dsp_fck_clksel[] = {
1042 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1043 { .parent = NULL }
1044 };
1045
1046 static struct clk dsp_fck = {
1047 .name = "dsp_fck",
1048 .ops = &clkops_omap2_dflt_wait,
1049 .parent = &core_ck,
1050 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1051 .clkdm_name = "dsp_clkdm",
1052 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1053 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1054 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1055 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1056 .clksel = dsp_fck_clksel,
1057 .recalc = &omap2_clksel_recalc,
1058 .round_rate = &omap2_clksel_round_rate,
1059 .set_rate = &omap2_clksel_set_rate
1060 };
1061
1062 /* DSP interface clock */
1063 static const struct clksel_rate dsp_irate_ick_rates[] = {
1064 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1065 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1066 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1067 { .div = 0 },
1068 };
1069
1070 static const struct clksel dsp_irate_ick_clksel[] = {
1071 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1072 { .parent = NULL }
1073 };
1074
1075 /* This clock does not exist as such in the TRM. */
1076 static struct clk dsp_irate_ick = {
1077 .name = "dsp_irate_ick",
1078 .ops = &clkops_null,
1079 .parent = &dsp_fck,
1080 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1081 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1082 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1083 .clksel = dsp_irate_ick_clksel,
1084 .recalc = &omap2_clksel_recalc,
1085 .round_rate = &omap2_clksel_round_rate,
1086 .set_rate = &omap2_clksel_set_rate
1087 };
1088
1089 /* 2420 only */
1090 static struct clk dsp_ick = {
1091 .name = "dsp_ick", /* apparently ipi and isp */
1092 .ops = &clkops_omap2_dflt_wait,
1093 .parent = &dsp_irate_ick,
1094 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1095 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1096 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1097 };
1098
1099 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1100 static struct clk iva2_1_ick = {
1101 .name = "iva2_1_ick",
1102 .ops = &clkops_omap2_dflt_wait,
1103 .parent = &dsp_irate_ick,
1104 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1105 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1106 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1107 };
1108
1109 /*
1110 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1111 * the C54x, but which is contained in the DSP powerdomain. Does not
1112 * exist on later OMAPs.
1113 */
1114 static struct clk iva1_ifck = {
1115 .name = "iva1_ifck",
1116 .ops = &clkops_omap2_dflt_wait,
1117 .parent = &core_ck,
1118 .flags = CONFIG_PARTICIPANT | DELAYED_APP,
1119 .clkdm_name = "iva1_clkdm",
1120 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1121 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1122 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1123 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1124 .clksel = dsp_fck_clksel,
1125 .recalc = &omap2_clksel_recalc,
1126 .round_rate = &omap2_clksel_round_rate,
1127 .set_rate = &omap2_clksel_set_rate
1128 };
1129
1130 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1131 static struct clk iva1_mpu_int_ifck = {
1132 .name = "iva1_mpu_int_ifck",
1133 .ops = &clkops_omap2_dflt_wait,
1134 .parent = &iva1_ifck,
1135 .clkdm_name = "iva1_clkdm",
1136 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1137 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1138 .fixed_div = 2,
1139 .recalc = &omap2_fixed_divisor_recalc,
1140 };
1141
1142 /*
1143 * L3 clock domain
1144 * L3 clocks are used for both interface and functional clocks to
1145 * multiple entities. Some of these clocks are completely managed
1146 * by hardware, and some others allow software control. Hardware
1147 * managed ones general are based on directly CLK_REQ signals and
1148 * various auto idle settings. The functional spec sets many of these
1149 * as 'tie-high' for their enables.
1150 *
1151 * I-CLOCKS:
1152 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1153 * CAM, HS-USB.
1154 * F-CLOCK
1155 * SSI.
1156 *
1157 * GPMC memories and SDRC have timing and clock sensitive registers which
1158 * may very well need notification when the clock changes. Currently for low
1159 * operating points, these are taken care of in sleep.S.
1160 */
1161 static const struct clksel_rate core_l3_core_rates[] = {
1162 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1163 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1164 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1165 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1166 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1167 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1168 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1169 { .div = 0 }
1170 };
1171
1172 static const struct clksel core_l3_clksel[] = {
1173 { .parent = &core_ck, .rates = core_l3_core_rates },
1174 { .parent = NULL }
1175 };
1176
1177 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1178 .name = "core_l3_ck",
1179 .ops = &clkops_null,
1180 .parent = &core_ck,
1181 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1182 .clkdm_name = "core_l3_clkdm",
1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1184 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1185 .clksel = core_l3_clksel,
1186 .recalc = &omap2_clksel_recalc,
1187 .round_rate = &omap2_clksel_round_rate,
1188 .set_rate = &omap2_clksel_set_rate
1189 };
1190
1191 /* usb_l4_ick */
1192 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1193 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1194 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1195 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1196 { .div = 0 }
1197 };
1198
1199 static const struct clksel usb_l4_ick_clksel[] = {
1200 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1201 { .parent = NULL },
1202 };
1203
1204 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1205 static struct clk usb_l4_ick = { /* FS-USB interface clock */
1206 .name = "usb_l4_ick",
1207 .ops = &clkops_omap2_dflt_wait,
1208 .parent = &core_l3_ck,
1209 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1210 .clkdm_name = "core_l4_clkdm",
1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1212 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1213 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1214 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1215 .clksel = usb_l4_ick_clksel,
1216 .recalc = &omap2_clksel_recalc,
1217 .round_rate = &omap2_clksel_round_rate,
1218 .set_rate = &omap2_clksel_set_rate
1219 };
1220
1221 /*
1222 * L4 clock management domain
1223 *
1224 * This domain contains lots of interface clocks from the L4 interface, some
1225 * functional clocks. Fixed APLL functional source clocks are managed in
1226 * this domain.
1227 */
1228 static const struct clksel_rate l4_core_l3_rates[] = {
1229 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1230 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1231 { .div = 0 }
1232 };
1233
1234 static const struct clksel l4_clksel[] = {
1235 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1236 { .parent = NULL }
1237 };
1238
1239 static struct clk l4_ck = { /* used both as an ick and fck */
1240 .name = "l4_ck",
1241 .ops = &clkops_null,
1242 .parent = &core_l3_ck,
1243 .flags = DELAYED_APP,
1244 .clkdm_name = "core_l4_clkdm",
1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1247 .clksel = l4_clksel,
1248 .recalc = &omap2_clksel_recalc,
1249 .round_rate = &omap2_clksel_round_rate,
1250 .set_rate = &omap2_clksel_set_rate
1251 };
1252
1253 /*
1254 * SSI is in L3 management domain, its direct parent is core not l3,
1255 * many core power domain entities are grouped into the L3 clock
1256 * domain.
1257 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1258 *
1259 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1260 */
1261 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1262 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1263 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1264 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1265 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1266 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1267 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1268 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1269 { .div = 0 }
1270 };
1271
1272 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1273 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1274 { .parent = NULL }
1275 };
1276
1277 static struct clk ssi_ssr_sst_fck = {
1278 .name = "ssi_fck",
1279 .ops = &clkops_omap2_dflt_wait,
1280 .parent = &core_ck,
1281 .flags = DELAYED_APP,
1282 .clkdm_name = "core_l3_clkdm",
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1285 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1286 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1287 .clksel = ssi_ssr_sst_fck_clksel,
1288 .recalc = &omap2_clksel_recalc,
1289 .round_rate = &omap2_clksel_round_rate,
1290 .set_rate = &omap2_clksel_set_rate
1291 };
1292
1293 /*
1294 * Presumably this is the same as SSI_ICLK.
1295 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1296 */
1297 static struct clk ssi_l4_ick = {
1298 .name = "ssi_l4_ick",
1299 .ops = &clkops_omap2_dflt_wait,
1300 .parent = &l4_ck,
1301 .clkdm_name = "core_l4_clkdm",
1302 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1303 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1304 .recalc = &followparent_recalc,
1305 };
1306
1307
1308 /*
1309 * GFX clock domain
1310 * Clocks:
1311 * GFX_FCLK, GFX_ICLK
1312 * GFX_CG1(2d), GFX_CG2(3d)
1313 *
1314 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1315 * The 2d and 3d clocks run at a hardware determined
1316 * divided value of fclk.
1317 *
1318 */
1319 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1320
1321 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1322 static const struct clksel gfx_fck_clksel[] = {
1323 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1324 { .parent = NULL },
1325 };
1326
1327 static struct clk gfx_3d_fck = {
1328 .name = "gfx_3d_fck",
1329 .ops = &clkops_omap2_dflt_wait,
1330 .parent = &core_l3_ck,
1331 .clkdm_name = "gfx_clkdm",
1332 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1333 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1334 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1335 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1336 .clksel = gfx_fck_clksel,
1337 .recalc = &omap2_clksel_recalc,
1338 .round_rate = &omap2_clksel_round_rate,
1339 .set_rate = &omap2_clksel_set_rate
1340 };
1341
1342 static struct clk gfx_2d_fck = {
1343 .name = "gfx_2d_fck",
1344 .ops = &clkops_omap2_dflt_wait,
1345 .parent = &core_l3_ck,
1346 .clkdm_name = "gfx_clkdm",
1347 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1348 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1349 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1350 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1351 .clksel = gfx_fck_clksel,
1352 .recalc = &omap2_clksel_recalc,
1353 .round_rate = &omap2_clksel_round_rate,
1354 .set_rate = &omap2_clksel_set_rate
1355 };
1356
1357 static struct clk gfx_ick = {
1358 .name = "gfx_ick", /* From l3 */
1359 .ops = &clkops_omap2_dflt_wait,
1360 .parent = &core_l3_ck,
1361 .clkdm_name = "gfx_clkdm",
1362 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1363 .enable_bit = OMAP_EN_GFX_SHIFT,
1364 .recalc = &followparent_recalc,
1365 };
1366
1367 /*
1368 * Modem clock domain (2430)
1369 * CLOCKS:
1370 * MDM_OSC_CLK
1371 * MDM_ICLK
1372 * These clocks are usable in chassis mode only.
1373 */
1374 static const struct clksel_rate mdm_ick_core_rates[] = {
1375 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1376 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1377 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1378 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1379 { .div = 0 }
1380 };
1381
1382 static const struct clksel mdm_ick_clksel[] = {
1383 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1384 { .parent = NULL }
1385 };
1386
1387 static struct clk mdm_ick = { /* used both as a ick and fck */
1388 .name = "mdm_ick",
1389 .ops = &clkops_omap2_dflt_wait,
1390 .parent = &core_ck,
1391 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1392 .clkdm_name = "mdm_clkdm",
1393 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1394 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1395 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1396 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1397 .clksel = mdm_ick_clksel,
1398 .recalc = &omap2_clksel_recalc,
1399 .round_rate = &omap2_clksel_round_rate,
1400 .set_rate = &omap2_clksel_set_rate
1401 };
1402
1403 static struct clk mdm_osc_ck = {
1404 .name = "mdm_osc_ck",
1405 .ops = &clkops_omap2_dflt_wait,
1406 .parent = &osc_ck,
1407 .clkdm_name = "mdm_clkdm",
1408 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1409 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1410 .recalc = &followparent_recalc,
1411 };
1412
1413 /*
1414 * DSS clock domain
1415 * CLOCKs:
1416 * DSS_L4_ICLK, DSS_L3_ICLK,
1417 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1418 *
1419 * DSS is both initiator and target.
1420 */
1421 /* XXX Add RATE_NOT_VALIDATED */
1422
1423 static const struct clksel_rate dss1_fck_sys_rates[] = {
1424 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1425 { .div = 0 }
1426 };
1427
1428 static const struct clksel_rate dss1_fck_core_rates[] = {
1429 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1430 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1431 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1432 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1433 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1434 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1435 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1436 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1437 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1438 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1439 { .div = 0 }
1440 };
1441
1442 static const struct clksel dss1_fck_clksel[] = {
1443 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1444 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1445 { .parent = NULL },
1446 };
1447
1448 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1449 .name = "dss_ick",
1450 .ops = &clkops_omap2_dflt,
1451 .parent = &l4_ck, /* really both l3 and l4 */
1452 .clkdm_name = "dss_clkdm",
1453 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1454 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1455 .recalc = &followparent_recalc,
1456 };
1457
1458 static struct clk dss1_fck = {
1459 .name = "dss1_fck",
1460 .ops = &clkops_omap2_dflt,
1461 .parent = &core_ck, /* Core or sys */
1462 .flags = DELAYED_APP,
1463 .clkdm_name = "dss_clkdm",
1464 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1465 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1466 .init = &omap2_init_clksel_parent,
1467 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1468 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1469 .clksel = dss1_fck_clksel,
1470 .recalc = &omap2_clksel_recalc,
1471 .round_rate = &omap2_clksel_round_rate,
1472 .set_rate = &omap2_clksel_set_rate
1473 };
1474
1475 static const struct clksel_rate dss2_fck_sys_rates[] = {
1476 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1477 { .div = 0 }
1478 };
1479
1480 static const struct clksel_rate dss2_fck_48m_rates[] = {
1481 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1482 { .div = 0 }
1483 };
1484
1485 static const struct clksel dss2_fck_clksel[] = {
1486 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1487 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1488 { .parent = NULL }
1489 };
1490
1491 static struct clk dss2_fck = { /* Alt clk used in power management */
1492 .name = "dss2_fck",
1493 .ops = &clkops_omap2_dflt,
1494 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1495 .flags = DELAYED_APP,
1496 .clkdm_name = "dss_clkdm",
1497 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1498 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1499 .init = &omap2_init_clksel_parent,
1500 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1501 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1502 .clksel = dss2_fck_clksel,
1503 .recalc = &followparent_recalc,
1504 };
1505
1506 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1507 .name = "dss_54m_fck", /* 54m tv clk */
1508 .ops = &clkops_omap2_dflt_wait,
1509 .parent = &func_54m_ck,
1510 .clkdm_name = "dss_clkdm",
1511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1512 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1513 .recalc = &followparent_recalc,
1514 };
1515
1516 /*
1517 * CORE power domain ICLK & FCLK defines.
1518 * Many of the these can have more than one possible parent. Entries
1519 * here will likely have an L4 interface parent, and may have multiple
1520 * functional clock parents.
1521 */
1522 static const struct clksel_rate gpt_alt_rates[] = {
1523 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1524 { .div = 0 }
1525 };
1526
1527 static const struct clksel omap24xx_gpt_clksel[] = {
1528 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1529 { .parent = &sys_ck, .rates = gpt_sys_rates },
1530 { .parent = &alt_ck, .rates = gpt_alt_rates },
1531 { .parent = NULL },
1532 };
1533
1534 static struct clk gpt1_ick = {
1535 .name = "gpt1_ick",
1536 .ops = &clkops_omap2_dflt_wait,
1537 .parent = &l4_ck,
1538 .clkdm_name = "core_l4_clkdm",
1539 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1540 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1541 .recalc = &followparent_recalc,
1542 };
1543
1544 static struct clk gpt1_fck = {
1545 .name = "gpt1_fck",
1546 .ops = &clkops_omap2_dflt_wait,
1547 .parent = &func_32k_ck,
1548 .clkdm_name = "core_l4_clkdm",
1549 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1550 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1551 .init = &omap2_init_clksel_parent,
1552 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1553 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1554 .clksel = omap24xx_gpt_clksel,
1555 .recalc = &omap2_clksel_recalc,
1556 .round_rate = &omap2_clksel_round_rate,
1557 .set_rate = &omap2_clksel_set_rate
1558 };
1559
1560 static struct clk gpt2_ick = {
1561 .name = "gpt2_ick",
1562 .ops = &clkops_omap2_dflt_wait,
1563 .parent = &l4_ck,
1564 .clkdm_name = "core_l4_clkdm",
1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1566 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1567 .recalc = &followparent_recalc,
1568 };
1569
1570 static struct clk gpt2_fck = {
1571 .name = "gpt2_fck",
1572 .ops = &clkops_omap2_dflt_wait,
1573 .parent = &func_32k_ck,
1574 .clkdm_name = "core_l4_clkdm",
1575 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1576 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1577 .init = &omap2_init_clksel_parent,
1578 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1579 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1580 .clksel = omap24xx_gpt_clksel,
1581 .recalc = &omap2_clksel_recalc,
1582 };
1583
1584 static struct clk gpt3_ick = {
1585 .name = "gpt3_ick",
1586 .ops = &clkops_omap2_dflt_wait,
1587 .parent = &l4_ck,
1588 .clkdm_name = "core_l4_clkdm",
1589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1590 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1591 .recalc = &followparent_recalc,
1592 };
1593
1594 static struct clk gpt3_fck = {
1595 .name = "gpt3_fck",
1596 .ops = &clkops_omap2_dflt_wait,
1597 .parent = &func_32k_ck,
1598 .clkdm_name = "core_l4_clkdm",
1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1601 .init = &omap2_init_clksel_parent,
1602 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1603 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1604 .clksel = omap24xx_gpt_clksel,
1605 .recalc = &omap2_clksel_recalc,
1606 };
1607
1608 static struct clk gpt4_ick = {
1609 .name = "gpt4_ick",
1610 .ops = &clkops_omap2_dflt_wait,
1611 .parent = &l4_ck,
1612 .clkdm_name = "core_l4_clkdm",
1613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1614 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1615 .recalc = &followparent_recalc,
1616 };
1617
1618 static struct clk gpt4_fck = {
1619 .name = "gpt4_fck",
1620 .ops = &clkops_omap2_dflt_wait,
1621 .parent = &func_32k_ck,
1622 .clkdm_name = "core_l4_clkdm",
1623 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1624 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1625 .init = &omap2_init_clksel_parent,
1626 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1627 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1628 .clksel = omap24xx_gpt_clksel,
1629 .recalc = &omap2_clksel_recalc,
1630 };
1631
1632 static struct clk gpt5_ick = {
1633 .name = "gpt5_ick",
1634 .ops = &clkops_omap2_dflt_wait,
1635 .parent = &l4_ck,
1636 .clkdm_name = "core_l4_clkdm",
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1638 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1639 .recalc = &followparent_recalc,
1640 };
1641
1642 static struct clk gpt5_fck = {
1643 .name = "gpt5_fck",
1644 .ops = &clkops_omap2_dflt_wait,
1645 .parent = &func_32k_ck,
1646 .clkdm_name = "core_l4_clkdm",
1647 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1648 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1649 .init = &omap2_init_clksel_parent,
1650 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1651 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1652 .clksel = omap24xx_gpt_clksel,
1653 .recalc = &omap2_clksel_recalc,
1654 };
1655
1656 static struct clk gpt6_ick = {
1657 .name = "gpt6_ick",
1658 .ops = &clkops_omap2_dflt_wait,
1659 .parent = &l4_ck,
1660 .clkdm_name = "core_l4_clkdm",
1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1662 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1663 .recalc = &followparent_recalc,
1664 };
1665
1666 static struct clk gpt6_fck = {
1667 .name = "gpt6_fck",
1668 .ops = &clkops_omap2_dflt_wait,
1669 .parent = &func_32k_ck,
1670 .clkdm_name = "core_l4_clkdm",
1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1672 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1673 .init = &omap2_init_clksel_parent,
1674 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1675 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1676 .clksel = omap24xx_gpt_clksel,
1677 .recalc = &omap2_clksel_recalc,
1678 };
1679
1680 static struct clk gpt7_ick = {
1681 .name = "gpt7_ick",
1682 .ops = &clkops_omap2_dflt_wait,
1683 .parent = &l4_ck,
1684 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1685 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1686 .recalc = &followparent_recalc,
1687 };
1688
1689 static struct clk gpt7_fck = {
1690 .name = "gpt7_fck",
1691 .ops = &clkops_omap2_dflt_wait,
1692 .parent = &func_32k_ck,
1693 .clkdm_name = "core_l4_clkdm",
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1695 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1696 .init = &omap2_init_clksel_parent,
1697 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1698 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1699 .clksel = omap24xx_gpt_clksel,
1700 .recalc = &omap2_clksel_recalc,
1701 };
1702
1703 static struct clk gpt8_ick = {
1704 .name = "gpt8_ick",
1705 .ops = &clkops_omap2_dflt_wait,
1706 .parent = &l4_ck,
1707 .clkdm_name = "core_l4_clkdm",
1708 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1709 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1710 .recalc = &followparent_recalc,
1711 };
1712
1713 static struct clk gpt8_fck = {
1714 .name = "gpt8_fck",
1715 .ops = &clkops_omap2_dflt_wait,
1716 .parent = &func_32k_ck,
1717 .clkdm_name = "core_l4_clkdm",
1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1719 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1720 .init = &omap2_init_clksel_parent,
1721 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1722 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1723 .clksel = omap24xx_gpt_clksel,
1724 .recalc = &omap2_clksel_recalc,
1725 };
1726
1727 static struct clk gpt9_ick = {
1728 .name = "gpt9_ick",
1729 .ops = &clkops_omap2_dflt_wait,
1730 .parent = &l4_ck,
1731 .clkdm_name = "core_l4_clkdm",
1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1734 .recalc = &followparent_recalc,
1735 };
1736
1737 static struct clk gpt9_fck = {
1738 .name = "gpt9_fck",
1739 .ops = &clkops_omap2_dflt_wait,
1740 .parent = &func_32k_ck,
1741 .clkdm_name = "core_l4_clkdm",
1742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1743 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1744 .init = &omap2_init_clksel_parent,
1745 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1746 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1747 .clksel = omap24xx_gpt_clksel,
1748 .recalc = &omap2_clksel_recalc,
1749 };
1750
1751 static struct clk gpt10_ick = {
1752 .name = "gpt10_ick",
1753 .ops = &clkops_omap2_dflt_wait,
1754 .parent = &l4_ck,
1755 .clkdm_name = "core_l4_clkdm",
1756 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1757 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1758 .recalc = &followparent_recalc,
1759 };
1760
1761 static struct clk gpt10_fck = {
1762 .name = "gpt10_fck",
1763 .ops = &clkops_omap2_dflt_wait,
1764 .parent = &func_32k_ck,
1765 .clkdm_name = "core_l4_clkdm",
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1767 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1768 .init = &omap2_init_clksel_parent,
1769 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1770 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1771 .clksel = omap24xx_gpt_clksel,
1772 .recalc = &omap2_clksel_recalc,
1773 };
1774
1775 static struct clk gpt11_ick = {
1776 .name = "gpt11_ick",
1777 .ops = &clkops_omap2_dflt_wait,
1778 .parent = &l4_ck,
1779 .clkdm_name = "core_l4_clkdm",
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1781 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1782 .recalc = &followparent_recalc,
1783 };
1784
1785 static struct clk gpt11_fck = {
1786 .name = "gpt11_fck",
1787 .ops = &clkops_omap2_dflt_wait,
1788 .parent = &func_32k_ck,
1789 .clkdm_name = "core_l4_clkdm",
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1791 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1792 .init = &omap2_init_clksel_parent,
1793 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1794 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1795 .clksel = omap24xx_gpt_clksel,
1796 .recalc = &omap2_clksel_recalc,
1797 };
1798
1799 static struct clk gpt12_ick = {
1800 .name = "gpt12_ick",
1801 .ops = &clkops_omap2_dflt_wait,
1802 .parent = &l4_ck,
1803 .clkdm_name = "core_l4_clkdm",
1804 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1805 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1806 .recalc = &followparent_recalc,
1807 };
1808
1809 static struct clk gpt12_fck = {
1810 .name = "gpt12_fck",
1811 .ops = &clkops_omap2_dflt_wait,
1812 .parent = &secure_32k_ck,
1813 .clkdm_name = "core_l4_clkdm",
1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1815 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1816 .init = &omap2_init_clksel_parent,
1817 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1818 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1819 .clksel = omap24xx_gpt_clksel,
1820 .recalc = &omap2_clksel_recalc,
1821 };
1822
1823 static struct clk mcbsp1_ick = {
1824 .name = "mcbsp_ick",
1825 .ops = &clkops_omap2_dflt_wait,
1826 .id = 1,
1827 .parent = &l4_ck,
1828 .clkdm_name = "core_l4_clkdm",
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1831 .recalc = &followparent_recalc,
1832 };
1833
1834 static struct clk mcbsp1_fck = {
1835 .name = "mcbsp_fck",
1836 .ops = &clkops_omap2_dflt_wait,
1837 .id = 1,
1838 .parent = &func_96m_ck,
1839 .clkdm_name = "core_l4_clkdm",
1840 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1841 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1842 .recalc = &followparent_recalc,
1843 };
1844
1845 static struct clk mcbsp2_ick = {
1846 .name = "mcbsp_ick",
1847 .ops = &clkops_omap2_dflt_wait,
1848 .id = 2,
1849 .parent = &l4_ck,
1850 .clkdm_name = "core_l4_clkdm",
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1852 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1853 .recalc = &followparent_recalc,
1854 };
1855
1856 static struct clk mcbsp2_fck = {
1857 .name = "mcbsp_fck",
1858 .ops = &clkops_omap2_dflt_wait,
1859 .id = 2,
1860 .parent = &func_96m_ck,
1861 .clkdm_name = "core_l4_clkdm",
1862 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1863 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1864 .recalc = &followparent_recalc,
1865 };
1866
1867 static struct clk mcbsp3_ick = {
1868 .name = "mcbsp_ick",
1869 .ops = &clkops_omap2_dflt_wait,
1870 .id = 3,
1871 .parent = &l4_ck,
1872 .clkdm_name = "core_l4_clkdm",
1873 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1874 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1875 .recalc = &followparent_recalc,
1876 };
1877
1878 static struct clk mcbsp3_fck = {
1879 .name = "mcbsp_fck",
1880 .ops = &clkops_omap2_dflt_wait,
1881 .id = 3,
1882 .parent = &func_96m_ck,
1883 .clkdm_name = "core_l4_clkdm",
1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1885 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1886 .recalc = &followparent_recalc,
1887 };
1888
1889 static struct clk mcbsp4_ick = {
1890 .name = "mcbsp_ick",
1891 .ops = &clkops_omap2_dflt_wait,
1892 .id = 4,
1893 .parent = &l4_ck,
1894 .clkdm_name = "core_l4_clkdm",
1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1896 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1897 .recalc = &followparent_recalc,
1898 };
1899
1900 static struct clk mcbsp4_fck = {
1901 .name = "mcbsp_fck",
1902 .ops = &clkops_omap2_dflt_wait,
1903 .id = 4,
1904 .parent = &func_96m_ck,
1905 .clkdm_name = "core_l4_clkdm",
1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1907 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1908 .recalc = &followparent_recalc,
1909 };
1910
1911 static struct clk mcbsp5_ick = {
1912 .name = "mcbsp_ick",
1913 .ops = &clkops_omap2_dflt_wait,
1914 .id = 5,
1915 .parent = &l4_ck,
1916 .clkdm_name = "core_l4_clkdm",
1917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1918 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1919 .recalc = &followparent_recalc,
1920 };
1921
1922 static struct clk mcbsp5_fck = {
1923 .name = "mcbsp_fck",
1924 .ops = &clkops_omap2_dflt_wait,
1925 .id = 5,
1926 .parent = &func_96m_ck,
1927 .clkdm_name = "core_l4_clkdm",
1928 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1929 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1930 .recalc = &followparent_recalc,
1931 };
1932
1933 static struct clk mcspi1_ick = {
1934 .name = "mcspi_ick",
1935 .ops = &clkops_omap2_dflt_wait,
1936 .id = 1,
1937 .parent = &l4_ck,
1938 .clkdm_name = "core_l4_clkdm",
1939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1940 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1941 .recalc = &followparent_recalc,
1942 };
1943
1944 static struct clk mcspi1_fck = {
1945 .name = "mcspi_fck",
1946 .ops = &clkops_omap2_dflt_wait,
1947 .id = 1,
1948 .parent = &func_48m_ck,
1949 .clkdm_name = "core_l4_clkdm",
1950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1951 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1952 .recalc = &followparent_recalc,
1953 };
1954
1955 static struct clk mcspi2_ick = {
1956 .name = "mcspi_ick",
1957 .ops = &clkops_omap2_dflt_wait,
1958 .id = 2,
1959 .parent = &l4_ck,
1960 .clkdm_name = "core_l4_clkdm",
1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1962 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1963 .recalc = &followparent_recalc,
1964 };
1965
1966 static struct clk mcspi2_fck = {
1967 .name = "mcspi_fck",
1968 .ops = &clkops_omap2_dflt_wait,
1969 .id = 2,
1970 .parent = &func_48m_ck,
1971 .clkdm_name = "core_l4_clkdm",
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1973 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1974 .recalc = &followparent_recalc,
1975 };
1976
1977 static struct clk mcspi3_ick = {
1978 .name = "mcspi_ick",
1979 .ops = &clkops_omap2_dflt_wait,
1980 .id = 3,
1981 .parent = &l4_ck,
1982 .clkdm_name = "core_l4_clkdm",
1983 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1984 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1985 .recalc = &followparent_recalc,
1986 };
1987
1988 static struct clk mcspi3_fck = {
1989 .name = "mcspi_fck",
1990 .ops = &clkops_omap2_dflt_wait,
1991 .id = 3,
1992 .parent = &func_48m_ck,
1993 .clkdm_name = "core_l4_clkdm",
1994 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1995 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1996 .recalc = &followparent_recalc,
1997 };
1998
1999 static struct clk uart1_ick = {
2000 .name = "uart1_ick",
2001 .ops = &clkops_omap2_dflt_wait,
2002 .parent = &l4_ck,
2003 .clkdm_name = "core_l4_clkdm",
2004 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2005 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2006 .recalc = &followparent_recalc,
2007 };
2008
2009 static struct clk uart1_fck = {
2010 .name = "uart1_fck",
2011 .ops = &clkops_omap2_dflt_wait,
2012 .parent = &func_48m_ck,
2013 .clkdm_name = "core_l4_clkdm",
2014 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2015 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2016 .recalc = &followparent_recalc,
2017 };
2018
2019 static struct clk uart2_ick = {
2020 .name = "uart2_ick",
2021 .ops = &clkops_omap2_dflt_wait,
2022 .parent = &l4_ck,
2023 .clkdm_name = "core_l4_clkdm",
2024 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2025 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2026 .recalc = &followparent_recalc,
2027 };
2028
2029 static struct clk uart2_fck = {
2030 .name = "uart2_fck",
2031 .ops = &clkops_omap2_dflt_wait,
2032 .parent = &func_48m_ck,
2033 .clkdm_name = "core_l4_clkdm",
2034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2035 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2036 .recalc = &followparent_recalc,
2037 };
2038
2039 static struct clk uart3_ick = {
2040 .name = "uart3_ick",
2041 .ops = &clkops_omap2_dflt_wait,
2042 .parent = &l4_ck,
2043 .clkdm_name = "core_l4_clkdm",
2044 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2045 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2046 .recalc = &followparent_recalc,
2047 };
2048
2049 static struct clk uart3_fck = {
2050 .name = "uart3_fck",
2051 .ops = &clkops_omap2_dflt_wait,
2052 .parent = &func_48m_ck,
2053 .clkdm_name = "core_l4_clkdm",
2054 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2055 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2056 .recalc = &followparent_recalc,
2057 };
2058
2059 static struct clk gpios_ick = {
2060 .name = "gpios_ick",
2061 .ops = &clkops_omap2_dflt_wait,
2062 .parent = &l4_ck,
2063 .clkdm_name = "core_l4_clkdm",
2064 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2065 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2066 .recalc = &followparent_recalc,
2067 };
2068
2069 static struct clk gpios_fck = {
2070 .name = "gpios_fck",
2071 .ops = &clkops_omap2_dflt_wait,
2072 .parent = &func_32k_ck,
2073 .clkdm_name = "wkup_clkdm",
2074 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2075 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2076 .recalc = &followparent_recalc,
2077 };
2078
2079 static struct clk mpu_wdt_ick = {
2080 .name = "mpu_wdt_ick",
2081 .ops = &clkops_omap2_dflt_wait,
2082 .parent = &l4_ck,
2083 .clkdm_name = "core_l4_clkdm",
2084 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2085 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2086 .recalc = &followparent_recalc,
2087 };
2088
2089 static struct clk mpu_wdt_fck = {
2090 .name = "mpu_wdt_fck",
2091 .ops = &clkops_omap2_dflt_wait,
2092 .parent = &func_32k_ck,
2093 .clkdm_name = "wkup_clkdm",
2094 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2095 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2096 .recalc = &followparent_recalc,
2097 };
2098
2099 static struct clk sync_32k_ick = {
2100 .name = "sync_32k_ick",
2101 .ops = &clkops_omap2_dflt_wait,
2102 .parent = &l4_ck,
2103 .flags = ENABLE_ON_INIT,
2104 .clkdm_name = "core_l4_clkdm",
2105 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2106 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2107 .recalc = &followparent_recalc,
2108 };
2109
2110 static struct clk wdt1_ick = {
2111 .name = "wdt1_ick",
2112 .ops = &clkops_omap2_dflt_wait,
2113 .parent = &l4_ck,
2114 .clkdm_name = "core_l4_clkdm",
2115 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2116 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2117 .recalc = &followparent_recalc,
2118 };
2119
2120 static struct clk omapctrl_ick = {
2121 .name = "omapctrl_ick",
2122 .ops = &clkops_omap2_dflt_wait,
2123 .parent = &l4_ck,
2124 .flags = ENABLE_ON_INIT,
2125 .clkdm_name = "core_l4_clkdm",
2126 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2127 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2128 .recalc = &followparent_recalc,
2129 };
2130
2131 static struct clk icr_ick = {
2132 .name = "icr_ick",
2133 .ops = &clkops_omap2_dflt_wait,
2134 .parent = &l4_ck,
2135 .clkdm_name = "core_l4_clkdm",
2136 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2137 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2138 .recalc = &followparent_recalc,
2139 };
2140
2141 static struct clk cam_ick = {
2142 .name = "cam_ick",
2143 .ops = &clkops_omap2_dflt,
2144 .parent = &l4_ck,
2145 .clkdm_name = "core_l4_clkdm",
2146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2147 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2148 .recalc = &followparent_recalc,
2149 };
2150
2151 /*
2152 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2153 * split into two separate clocks, since the parent clocks are different
2154 * and the clockdomains are also different.
2155 */
2156 static struct clk cam_fck = {
2157 .name = "cam_fck",
2158 .ops = &clkops_omap2_dflt,
2159 .parent = &func_96m_ck,
2160 .clkdm_name = "core_l3_clkdm",
2161 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2162 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2163 .recalc = &followparent_recalc,
2164 };
2165
2166 static struct clk mailboxes_ick = {
2167 .name = "mailboxes_ick",
2168 .ops = &clkops_omap2_dflt_wait,
2169 .parent = &l4_ck,
2170 .clkdm_name = "core_l4_clkdm",
2171 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2172 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2173 .recalc = &followparent_recalc,
2174 };
2175
2176 static struct clk wdt4_ick = {
2177 .name = "wdt4_ick",
2178 .ops = &clkops_omap2_dflt_wait,
2179 .parent = &l4_ck,
2180 .clkdm_name = "core_l4_clkdm",
2181 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2182 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2183 .recalc = &followparent_recalc,
2184 };
2185
2186 static struct clk wdt4_fck = {
2187 .name = "wdt4_fck",
2188 .ops = &clkops_omap2_dflt_wait,
2189 .parent = &func_32k_ck,
2190 .clkdm_name = "core_l4_clkdm",
2191 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2192 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2193 .recalc = &followparent_recalc,
2194 };
2195
2196 static struct clk wdt3_ick = {
2197 .name = "wdt3_ick",
2198 .ops = &clkops_omap2_dflt_wait,
2199 .parent = &l4_ck,
2200 .clkdm_name = "core_l4_clkdm",
2201 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2202 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2203 .recalc = &followparent_recalc,
2204 };
2205
2206 static struct clk wdt3_fck = {
2207 .name = "wdt3_fck",
2208 .ops = &clkops_omap2_dflt_wait,
2209 .parent = &func_32k_ck,
2210 .clkdm_name = "core_l4_clkdm",
2211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2212 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2213 .recalc = &followparent_recalc,
2214 };
2215
2216 static struct clk mspro_ick = {
2217 .name = "mspro_ick",
2218 .ops = &clkops_omap2_dflt_wait,
2219 .parent = &l4_ck,
2220 .clkdm_name = "core_l4_clkdm",
2221 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2222 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2223 .recalc = &followparent_recalc,
2224 };
2225
2226 static struct clk mspro_fck = {
2227 .name = "mspro_fck",
2228 .ops = &clkops_omap2_dflt_wait,
2229 .parent = &func_96m_ck,
2230 .clkdm_name = "core_l4_clkdm",
2231 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2232 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2233 .recalc = &followparent_recalc,
2234 };
2235
2236 static struct clk mmc_ick = {
2237 .name = "mmc_ick",
2238 .ops = &clkops_omap2_dflt_wait,
2239 .parent = &l4_ck,
2240 .clkdm_name = "core_l4_clkdm",
2241 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2242 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2243 .recalc = &followparent_recalc,
2244 };
2245
2246 static struct clk mmc_fck = {
2247 .name = "mmc_fck",
2248 .ops = &clkops_omap2_dflt_wait,
2249 .parent = &func_96m_ck,
2250 .clkdm_name = "core_l4_clkdm",
2251 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2252 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2253 .recalc = &followparent_recalc,
2254 };
2255
2256 static struct clk fac_ick = {
2257 .name = "fac_ick",
2258 .ops = &clkops_omap2_dflt_wait,
2259 .parent = &l4_ck,
2260 .clkdm_name = "core_l4_clkdm",
2261 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2262 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2263 .recalc = &followparent_recalc,
2264 };
2265
2266 static struct clk fac_fck = {
2267 .name = "fac_fck",
2268 .ops = &clkops_omap2_dflt_wait,
2269 .parent = &func_12m_ck,
2270 .clkdm_name = "core_l4_clkdm",
2271 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2272 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2273 .recalc = &followparent_recalc,
2274 };
2275
2276 static struct clk eac_ick = {
2277 .name = "eac_ick",
2278 .ops = &clkops_omap2_dflt_wait,
2279 .parent = &l4_ck,
2280 .clkdm_name = "core_l4_clkdm",
2281 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2282 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2283 .recalc = &followparent_recalc,
2284 };
2285
2286 static struct clk eac_fck = {
2287 .name = "eac_fck",
2288 .ops = &clkops_omap2_dflt_wait,
2289 .parent = &func_96m_ck,
2290 .clkdm_name = "core_l4_clkdm",
2291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2292 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2293 .recalc = &followparent_recalc,
2294 };
2295
2296 static struct clk hdq_ick = {
2297 .name = "hdq_ick",
2298 .ops = &clkops_omap2_dflt_wait,
2299 .parent = &l4_ck,
2300 .clkdm_name = "core_l4_clkdm",
2301 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2302 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2303 .recalc = &followparent_recalc,
2304 };
2305
2306 static struct clk hdq_fck = {
2307 .name = "hdq_fck",
2308 .ops = &clkops_omap2_dflt_wait,
2309 .parent = &func_12m_ck,
2310 .clkdm_name = "core_l4_clkdm",
2311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2312 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2313 .recalc = &followparent_recalc,
2314 };
2315
2316 static struct clk i2c2_ick = {
2317 .name = "i2c_ick",
2318 .ops = &clkops_omap2_dflt_wait,
2319 .id = 2,
2320 .parent = &l4_ck,
2321 .clkdm_name = "core_l4_clkdm",
2322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2323 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2324 .recalc = &followparent_recalc,
2325 };
2326
2327 static struct clk i2c2_fck = {
2328 .name = "i2c_fck",
2329 .ops = &clkops_omap2_dflt_wait,
2330 .id = 2,
2331 .parent = &func_12m_ck,
2332 .clkdm_name = "core_l4_clkdm",
2333 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2334 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2335 .recalc = &followparent_recalc,
2336 };
2337
2338 static struct clk i2chs2_fck = {
2339 .name = "i2c_fck",
2340 .ops = &clkops_omap2430_i2chs_wait,
2341 .id = 2,
2342 .parent = &func_96m_ck,
2343 .clkdm_name = "core_l4_clkdm",
2344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2345 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2346 .recalc = &followparent_recalc,
2347 };
2348
2349 static struct clk i2c1_ick = {
2350 .name = "i2c_ick",
2351 .ops = &clkops_omap2_dflt_wait,
2352 .id = 1,
2353 .parent = &l4_ck,
2354 .clkdm_name = "core_l4_clkdm",
2355 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2356 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2357 .recalc = &followparent_recalc,
2358 };
2359
2360 static struct clk i2c1_fck = {
2361 .name = "i2c_fck",
2362 .ops = &clkops_omap2_dflt_wait,
2363 .id = 1,
2364 .parent = &func_12m_ck,
2365 .clkdm_name = "core_l4_clkdm",
2366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2367 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2368 .recalc = &followparent_recalc,
2369 };
2370
2371 static struct clk i2chs1_fck = {
2372 .name = "i2c_fck",
2373 .ops = &clkops_omap2430_i2chs_wait,
2374 .id = 1,
2375 .parent = &func_96m_ck,
2376 .clkdm_name = "core_l4_clkdm",
2377 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2378 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2379 .recalc = &followparent_recalc,
2380 };
2381
2382 static struct clk gpmc_fck = {
2383 .name = "gpmc_fck",
2384 .ops = &clkops_null, /* RMK: missing? */
2385 .parent = &core_l3_ck,
2386 .flags = ENABLE_ON_INIT,
2387 .clkdm_name = "core_l3_clkdm",
2388 .recalc = &followparent_recalc,
2389 };
2390
2391 static struct clk sdma_fck = {
2392 .name = "sdma_fck",
2393 .ops = &clkops_null, /* RMK: missing? */
2394 .parent = &core_l3_ck,
2395 .clkdm_name = "core_l3_clkdm",
2396 .recalc = &followparent_recalc,
2397 };
2398
2399 static struct clk sdma_ick = {
2400 .name = "sdma_ick",
2401 .ops = &clkops_null, /* RMK: missing? */
2402 .parent = &l4_ck,
2403 .clkdm_name = "core_l3_clkdm",
2404 .recalc = &followparent_recalc,
2405 };
2406
2407 static struct clk vlynq_ick = {
2408 .name = "vlynq_ick",
2409 .ops = &clkops_omap2_dflt_wait,
2410 .parent = &core_l3_ck,
2411 .clkdm_name = "core_l3_clkdm",
2412 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2413 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2414 .recalc = &followparent_recalc,
2415 };
2416
2417 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2418 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2419 { .div = 0 }
2420 };
2421
2422 static const struct clksel_rate vlynq_fck_core_rates[] = {
2423 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2424 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2425 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2426 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2427 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2428 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2429 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2430 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2431 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2432 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2433 { .div = 0 }
2434 };
2435
2436 static const struct clksel vlynq_fck_clksel[] = {
2437 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2438 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2439 { .parent = NULL }
2440 };
2441
2442 static struct clk vlynq_fck = {
2443 .name = "vlynq_fck",
2444 .ops = &clkops_omap2_dflt_wait,
2445 .parent = &func_96m_ck,
2446 .flags = DELAYED_APP,
2447 .clkdm_name = "core_l3_clkdm",
2448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2449 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2450 .init = &omap2_init_clksel_parent,
2451 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2452 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2453 .clksel = vlynq_fck_clksel,
2454 .recalc = &omap2_clksel_recalc,
2455 .round_rate = &omap2_clksel_round_rate,
2456 .set_rate = &omap2_clksel_set_rate
2457 };
2458
2459 static struct clk sdrc_ick = {
2460 .name = "sdrc_ick",
2461 .ops = &clkops_omap2_dflt_wait,
2462 .parent = &l4_ck,
2463 .flags = ENABLE_ON_INIT,
2464 .clkdm_name = "core_l4_clkdm",
2465 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2466 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2467 .recalc = &followparent_recalc,
2468 };
2469
2470 static struct clk des_ick = {
2471 .name = "des_ick",
2472 .ops = &clkops_omap2_dflt_wait,
2473 .parent = &l4_ck,
2474 .clkdm_name = "core_l4_clkdm",
2475 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2476 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2477 .recalc = &followparent_recalc,
2478 };
2479
2480 static struct clk sha_ick = {
2481 .name = "sha_ick",
2482 .ops = &clkops_omap2_dflt_wait,
2483 .parent = &l4_ck,
2484 .clkdm_name = "core_l4_clkdm",
2485 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2486 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2487 .recalc = &followparent_recalc,
2488 };
2489
2490 static struct clk rng_ick = {
2491 .name = "rng_ick",
2492 .ops = &clkops_omap2_dflt_wait,
2493 .parent = &l4_ck,
2494 .clkdm_name = "core_l4_clkdm",
2495 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2496 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2497 .recalc = &followparent_recalc,
2498 };
2499
2500 static struct clk aes_ick = {
2501 .name = "aes_ick",
2502 .ops = &clkops_omap2_dflt_wait,
2503 .parent = &l4_ck,
2504 .clkdm_name = "core_l4_clkdm",
2505 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2506 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2507 .recalc = &followparent_recalc,
2508 };
2509
2510 static struct clk pka_ick = {
2511 .name = "pka_ick",
2512 .ops = &clkops_omap2_dflt_wait,
2513 .parent = &l4_ck,
2514 .clkdm_name = "core_l4_clkdm",
2515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2516 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2517 .recalc = &followparent_recalc,
2518 };
2519
2520 static struct clk usb_fck = {
2521 .name = "usb_fck",
2522 .ops = &clkops_omap2_dflt_wait,
2523 .parent = &func_48m_ck,
2524 .clkdm_name = "core_l3_clkdm",
2525 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2526 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2527 .recalc = &followparent_recalc,
2528 };
2529
2530 static struct clk usbhs_ick = {
2531 .name = "usbhs_ick",
2532 .ops = &clkops_omap2_dflt_wait,
2533 .parent = &core_l3_ck,
2534 .clkdm_name = "core_l3_clkdm",
2535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2536 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2537 .recalc = &followparent_recalc,
2538 };
2539
2540 static struct clk mmchs1_ick = {
2541 .name = "mmchs_ick",
2542 .ops = &clkops_omap2_dflt_wait,
2543 .parent = &l4_ck,
2544 .clkdm_name = "core_l4_clkdm",
2545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2546 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2547 .recalc = &followparent_recalc,
2548 };
2549
2550 static struct clk mmchs1_fck = {
2551 .name = "mmchs_fck",
2552 .ops = &clkops_omap2_dflt_wait,
2553 .parent = &func_96m_ck,
2554 .clkdm_name = "core_l3_clkdm",
2555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2556 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2557 .recalc = &followparent_recalc,
2558 };
2559
2560 static struct clk mmchs2_ick = {
2561 .name = "mmchs_ick",
2562 .ops = &clkops_omap2_dflt_wait,
2563 .id = 1,
2564 .parent = &l4_ck,
2565 .clkdm_name = "core_l4_clkdm",
2566 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2567 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2568 .recalc = &followparent_recalc,
2569 };
2570
2571 static struct clk mmchs2_fck = {
2572 .name = "mmchs_fck",
2573 .ops = &clkops_omap2_dflt_wait,
2574 .id = 1,
2575 .parent = &func_96m_ck,
2576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2577 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2578 .recalc = &followparent_recalc,
2579 };
2580
2581 static struct clk gpio5_ick = {
2582 .name = "gpio5_ick",
2583 .ops = &clkops_omap2_dflt_wait,
2584 .parent = &l4_ck,
2585 .clkdm_name = "core_l4_clkdm",
2586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2587 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2588 .recalc = &followparent_recalc,
2589 };
2590
2591 static struct clk gpio5_fck = {
2592 .name = "gpio5_fck",
2593 .ops = &clkops_omap2_dflt_wait,
2594 .parent = &func_32k_ck,
2595 .clkdm_name = "core_l4_clkdm",
2596 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2597 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2598 .recalc = &followparent_recalc,
2599 };
2600
2601 static struct clk mdm_intc_ick = {
2602 .name = "mdm_intc_ick",
2603 .ops = &clkops_omap2_dflt_wait,
2604 .parent = &l4_ck,
2605 .clkdm_name = "core_l4_clkdm",
2606 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2607 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2608 .recalc = &followparent_recalc,
2609 };
2610
2611 static struct clk mmchsdb1_fck = {
2612 .name = "mmchsdb_fck",
2613 .ops = &clkops_omap2_dflt_wait,
2614 .parent = &func_32k_ck,
2615 .clkdm_name = "core_l4_clkdm",
2616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2617 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2618 .recalc = &followparent_recalc,
2619 };
2620
2621 static struct clk mmchsdb2_fck = {
2622 .name = "mmchsdb_fck",
2623 .ops = &clkops_omap2_dflt_wait,
2624 .id = 1,
2625 .parent = &func_32k_ck,
2626 .clkdm_name = "core_l4_clkdm",
2627 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2628 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2629 .recalc = &followparent_recalc,
2630 };
2631
2632 /*
2633 * This clock is a composite clock which does entire set changes then
2634 * forces a rebalance. It keys on the MPU speed, but it really could
2635 * be any key speed part of a set in the rate table.
2636 *
2637 * to really change a set, you need memory table sets which get changed
2638 * in sram, pre-notifiers & post notifiers, changing the top set, without
2639 * having low level display recalc's won't work... this is why dpm notifiers
2640 * work, isr's off, walk a list of clocks already _off_ and not messing with
2641 * the bus.
2642 *
2643 * This clock should have no parent. It embodies the entire upper level
2644 * active set. A parent will mess up some of the init also.
2645 */
2646 static struct clk virt_prcm_set = {
2647 .name = "virt_prcm_set",
2648 .ops = &clkops_null,
2649 .flags = DELAYED_APP,
2650 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2651 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2652 .set_rate = &omap2_select_table_rate,
2653 .round_rate = &omap2_round_to_table_rate,
2654 };
2655
2656 #endif
2657
Linux for Ginger Game Console