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First Support on Ginger and OMAP TI
[linux-ginger.git] / arch / arm / mach-omap2 / clock34xx.c
blobb965ea219a7c80761534af2c62b9ad071c3502b4
1 /*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17 #undef DEBUG
18
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
29 #include <linux/err.h>
30 #include <linux/cpufreq.h>
31
32 #include <plat/cpu.h>
33 #include <plat/clock.h>
34 #include <plat/sram.h>
35 #include <plat/omap-pm.h>
36
37 #include <asm/div64.h>
38 #include <asm/clkdev.h>
39
40 #include <plat/sdrc.h>
41 #include "clock.h"
42 #include "prm.h"
43 #include "prm-regbits-34xx.h"
44 #include "cm.h"
45 #include "cm-regbits-34xx.h"
46 #include "omap3-opp.h"
47
48 static const struct clkops clkops_noncore_dpll_ops;
49
50 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
51 void __iomem **idlest_reg,
52 u8 *idlest_bit);
53 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
54 void __iomem **idlest_reg,
55 u8 *idlest_bit);
56 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
57 void __iomem **idlest_reg,
58 u8 *idlest_bit);
59
60 static const struct clkops clkops_omap3430es2_ssi_wait = {
61 .enable = omap2_dflt_clk_enable,
62 .disable = omap2_dflt_clk_disable,
63 .find_idlest = omap3430es2_clk_ssi_find_idlest,
64 .find_companion = omap2_clk_dflt_find_companion,
65 };
66
67 static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
68 .enable = omap2_dflt_clk_enable,
69 .disable = omap2_dflt_clk_disable,
70 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
71 .find_companion = omap2_clk_dflt_find_companion,
72 };
73
74 static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
75 .enable = omap2_dflt_clk_enable,
76 .disable = omap2_dflt_clk_disable,
77 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
78 .find_companion = omap2_clk_dflt_find_companion,
79 };
80
81 #include "clock34xx.h"
82
83 struct omap_clk {
84 u32 cpu;
85 struct clk_lookup lk;
86 };
87
88 #define CLK(dev, con, ck, cp) \
89 { \
90 .cpu = cp, \
91 .lk = { \
92 .dev_id = dev, \
93 .con_id = con, \
94 .clk = ck, \
95 }, \
96 }
97
98 #define CK_343X (1 << 0)
99 #define CK_3430ES1 (1 << 1)
100 #define CK_3430ES2 (1 << 2)
101 #define CK_3517 (1 << 3)
102 #define CK_3505 (1 << 4)
103 #define CK_35XX (CK_3517 | CK_3505)
104
105 static struct omap_clk omap34xx_clks[] = {
106 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X | CK_35XX),
107 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X | CK_35XX),
108 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X | CK_35XX),
109 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_35XX),
110 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X | CK_35XX),
111 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X | CK_35XX),
112 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X | CK_35XX),
113 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X | CK_35XX),
114 CLK(NULL, "sys_ck", &sys_ck, CK_343X | CK_35XX),
115 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X | CK_35XX),
116 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X | CK_35XX),
117 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X | CK_35XX),
118 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X | CK_35XX),
119 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X | CK_35XX),
120 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X | CK_35XX),
121 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
122 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
123 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X | CK_35XX),
124 CLK(NULL, "core_ck", &core_ck, CK_343X | CK_35XX),
125 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X | CK_35XX),
126 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X | CK_35XX),
127 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X | CK_35XX),
128 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X | CK_35XX),
129 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X | CK_35XX),
130 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X | CK_35XX),
131 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X | CK_35XX),
132 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X | CK_35XX),
133 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X | CK_35XX),
134 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X | CK_35XX),
135 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X | CK_35XX),
136 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X | CK_35XX),
137 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X | CK_35XX),
138 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X | CK_35XX),
139 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X | CK_35XX),
140 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X | CK_35XX),
141 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X | CK_35XX),
142 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X | CK_35XX),
143 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X | CK_35XX),
144 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X | CK_35XX),
145 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X | CK_35XX),
146 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X | CK_35XX),
147 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X | CK_35XX),
148 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X | CK_35XX),
149 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X | CK_35XX),
150 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_35XX),
151 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_35XX),
152 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X | CK_35XX),
153 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X | CK_35XX),
154 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X | CK_35XX),
155 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X | CK_35XX),
156 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X | CK_35XX),
157 CLK(NULL, "arm_fck", &arm_fck, CK_343X | CK_35XX),
158 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X | CK_35XX),
159 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
160 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
161 CLK(NULL, "l3_ick", &l3_ick, CK_343X | CK_35XX),
162 CLK(NULL, "l4_ick", &l4_ick, CK_343X | CK_35XX),
163 CLK(NULL, "rm_ick", &rm_ick, CK_343X | CK_35XX),
164 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
165 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
166 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
167 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
168 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
169 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
170 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
171 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
172 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
173 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
174 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
175 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X | CK_35XX),
176 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X | CK_35XX),
177 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_35XX),
178 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_35XX),
179 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_35XX),
180 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X | CK_35XX),
181 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_35XX),
182 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X | CK_35XX),
183 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
184 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X | CK_35XX),
185 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X | CK_35XX),
186 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X | CK_35XX),
187 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X | CK_35XX),
188 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X | CK_35XX),
189 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X | CK_35XX),
190 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X | CK_35XX),
191 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X | CK_35XX),
192 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X | CK_35XX),
193 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X | CK_35XX),
194 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X | CK_35XX),
195 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X | CK_35XX),
196 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X | CK_35XX),
197 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
198 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X | CK_35XX),
199 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X | CK_35XX),
200 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
201 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
202 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
203 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
204 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X | CK_35XX),
205 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
206 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
207 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X | CK_35XX),
208 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X | CK_35XX),
209 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
210 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
211 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X | CK_35XX),
212 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_35XX),
213 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_35XX),
214 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
215 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
216 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
217 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
218 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X | CK_35XX),
219 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X | CK_35XX),
220 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
221 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X | CK_35XX),
222 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X | CK_35XX),
223 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X | CK_35XX),
224 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X | CK_35XX),
225 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X | CK_35XX),
226 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X | CK_35XX),
227 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X | CK_35XX),
228 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X | CK_35XX),
229 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X | CK_35XX),
230 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X | CK_35XX),
231 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X | CK_35XX),
232 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X | CK_35XX),
233 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X | CK_35XX),
234 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X | CK_35XX),
235 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
236 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
237 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X | CK_35XX),
238 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
239 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
240 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
241 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
242 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
243 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
244 CLK("omap_rng", "ick", &rng_ick, CK_343X),
245 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
246 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
247 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
248 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_35XX),
249 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X | CK_35XX),
250 CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X | CK_35XX),
251 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X | CK_35XX),
252 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
253 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_35XX),
254 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
255 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
256 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
257 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_35XX),
258 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_35XX),
259 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_35XX),
260 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
261 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X | CK_35XX),
262 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X | CK_35XX),
263 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X | CK_35XX),
264 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X | CK_35XX),
265 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X | CK_35XX),
266 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
267 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X | CK_35XX),
268 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X | CK_35XX),
269 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X | CK_35XX),
270 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X | CK_35XX),
271 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X | CK_35XX),
272 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X | CK_35XX),
273 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X | CK_35XX),
274 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X | CK_35XX),
275 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X | CK_35XX),
276 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X | CK_35XX),
277 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X | CK_35XX),
278 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X | CK_35XX),
279 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X | CK_35XX),
280 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X | CK_35XX),
281 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X | CK_35XX),
282 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X | CK_35XX),
283 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X | CK_35XX),
284 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X | CK_35XX),
285 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X | CK_35XX),
286 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X | CK_35XX),
287 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X | CK_35XX),
288 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X | CK_35XX),
289 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X | CK_35XX),
290 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X | CK_35XX),
291 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X | CK_35XX),
292 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X | CK_35XX),
293 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X | CK_35XX),
294 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X | CK_35XX),
295 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X | CK_35XX),
296 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X | CK_35XX),
297 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X | CK_35XX),
298 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X | CK_35XX),
299 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X | CK_35XX),
300 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X | CK_35XX),
301 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X | CK_35XX),
302 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X | CK_35XX),
303 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X | CK_35XX),
304 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X | CK_35XX),
305 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X | CK_35XX),
306 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X | CK_35XX),
307 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X | CK_35XX),
308 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X | CK_35XX),
309 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X | CK_35XX),
310 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X | CK_35XX),
311 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X | CK_35XX),
312 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X | CK_35XX),
313 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X | CK_35XX),
314 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X | CK_35XX),
315 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X | CK_35XX),
316 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X | CK_35XX),
317 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X | CK_35XX),
318 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X | CK_35XX),
319 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
320 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
321 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
322 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X | CK_35XX),
323 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X | CK_35XX),
324 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X | CK_35XX),
325 CLK(NULL, "emac_ck", &emac_ck, CK_35XX),
326 CLK(NULL, "emac_phy_ck", &emac_phy_ck, CK_35XX),
327 CLK(NULL, "usbotg_ck", &usbotg_ck, CK_35XX),
328 CLK(NULL, "usbotg_phy_ck", &usbotg_phy_ck, CK_35XX),
329 CLK(NULL, "hecc_ck", &hecc_ck, CK_35XX),
330 CLK(NULL, "vpfe_ck", &vpfe_ck, CK_35XX),
331 CLK(NULL, "vpfe_pck", &vpfe_pck, CK_35XX),
332 CLK(NULL, "uart4_ick", &uart4_ick, CK_35XX),
333 };
334
335 struct omap_opp omap3_mpu_rate_table[] = {
336 {0, 0, 0},
337 /*OPP1*/
338 {S125M, VDD1_OPP1, 0x1E},
339 /*OPP2*/
340 {S250M, VDD1_OPP2, 0x26},
341 /*OPP3*/
342 {S500M, VDD1_OPP3, 0x30},
343 /*OPP4*/
344 {S550M, VDD1_OPP4, 0x36},
345 /*OPP5*/
346 {S600M, VDD1_OPP5, 0x3C},
347 /*OPP6*/
348 {S720M, VDD1_OPP6, 0x3C},
349 };
350
351 struct omap_opp omap3_l3_rate_table[] = {
352 {0, 0, 0},
353 /*OPP1*/
354 {0, VDD2_OPP1, 0x1E},
355 /*OPP2*/
356 {S83M, VDD2_OPP2, 0x24},
357 /*OPP3*/
358 {S166M, VDD2_OPP3, 0x2C},
359 };
360
361 struct omap_opp omap3_dsp_rate_table[] = {
362 {0, 0, 0},
363 /*OPP1*/
364 {S90M, VDD1_OPP1, 0x1E},
365 /*OPP2*/
366 {S180M, VDD1_OPP2, 0x26},
367 /*OPP3*/
368 {S360M, VDD1_OPP3, 0x30},
369 /*OPP4*/
370 {S400M, VDD1_OPP4, 0x36},
371 /*OPP5*/
372 {S430M, VDD1_OPP5, 0x3C},
373 /*OPP5*/
374 {S520M, VDD1_OPP6, 0x3C},
375 };
376
377 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
378 #define DPLL_AUTOIDLE_DISABLE 0x0
379 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
380
381 #define MAX_DPLL_WAIT_TRIES 1000000
382
383 #define MIN_SDRC_DLL_LOCK_FREQ 83000000
384
385 #define CYCLES_PER_MHZ 1000000
386
387 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
388 #define SDRC_MPURATE_SCALE 8
389
390 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
391 #define SDRC_MPURATE_BASE_SHIFT 9
392
393 /*
394 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
395 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
396 */
397 #define SDRC_MPURATE_LOOPS 96
398
399 /*
400 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
401 * that are sourced by DPLL5, and both of these require this clock
402 * to be at 120 MHz for proper operation.
403 */
404 #define DPLL5_FREQ_FOR_USBHOST 120000000
405
406 /**
407 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
408 * @clk: struct clk * being enabled
409 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
410 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
411 *
412 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
413 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
414 * @idlest_reg and @idlest_bit. No return value.
415 */
416 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
417 void __iomem **idlest_reg,
418 u8 *idlest_bit)
419 {
420 u32 r;
421
422 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
423 *idlest_reg = (__force void __iomem *)r;
424 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
425 }
426
427 /**
428 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
429 * @clk: struct clk * being enabled
430 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
431 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
432 *
433 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
434 * target IDLEST bits. For our purposes, we are concerned with the
435 * target IDLEST bits, which exist at a different bit position than
436 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
437 * default find_idlest code assumes that they are at the same
438 * position.) No return value.
439 */
440 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
441 void __iomem **idlest_reg,
442 u8 *idlest_bit)
443 {
444 u32 r;
445
446 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
447 *idlest_reg = (__force void __iomem *)r;
448 /* USBHOST_IDLE has same shift */
449 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
450 }
451
452 /**
453 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
454 * @clk: struct clk * being enabled
455 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
456 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
457 *
458 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
459 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
460 * @idlest_reg and @idlest_bit. No return value.
461 */
462 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
463 void __iomem **idlest_reg,
464 u8 *idlest_bit)
465 {
466 u32 r;
467
468 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
469 *idlest_reg = (__force void __iomem *)r;
470 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
471 }
472
473 /**
474 * omap3_dpll_recalc - recalculate DPLL rate
475 * @clk: DPLL struct clk
476 *
477 * Recalculate and propagate the DPLL rate.
478 */
479 static unsigned long omap3_dpll_recalc(struct clk *clk)
480 {
481 return omap2_get_dpll_rate(clk);
482 }
483
484 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
485 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
486 {
487 const struct dpll_data *dd;
488 u32 v;
489
490 dd = clk->dpll_data;
491
492 v = __raw_readl(dd->control_reg);
493 v &= ~dd->enable_mask;
494 v |= clken_bits << __ffs(dd->enable_mask);
495 __raw_writel(v, dd->control_reg);
496 }
497
498 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
499 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
500 {
501 const struct dpll_data *dd;
502 int i = 0;
503 int ret = -EINVAL;
504
505 dd = clk->dpll_data;
506
507 state <<= __ffs(dd->idlest_mask);
508
509 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
510 i < MAX_DPLL_WAIT_TRIES) {
511 i++;
512 udelay(1);
513 }
514
515 if (i == MAX_DPLL_WAIT_TRIES) {
516 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
517 clk->name, (state) ? "locked" : "bypassed");
518 } else {
519 pr_debug("clock: %s transition to '%s' in %d loops\n",
520 clk->name, (state) ? "locked" : "bypassed", i);
521
522 ret = 0;
523 }
524
525 return ret;
526 }
527
528 /* From 3430 TRM ES2 4.7.6.2 */
529 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
530 {
531 unsigned long fint;
532 u16 f = 0;
533
534 fint = clk->dpll_data->clk_ref->rate / (n + 1);
535
536 pr_debug("clock: fint is %lu\n", fint);
537
538 if (fint >= 750000 && fint <= 1000000)
539 f = 0x3;
540 else if (fint > 1000000 && fint <= 1250000)
541 f = 0x4;
542 else if (fint > 1250000 && fint <= 1500000)
543 f = 0x5;
544 else if (fint > 1500000 && fint <= 1750000)
545 f = 0x6;
546 else if (fint > 1750000 && fint <= 2100000)
547 f = 0x7;
548 else if (fint > 7500000 && fint <= 10000000)
549 f = 0xB;
550 else if (fint > 10000000 && fint <= 12500000)
551 f = 0xC;
552 else if (fint > 12500000 && fint <= 15000000)
553 f = 0xD;
554 else if (fint > 15000000 && fint <= 17500000)
555 f = 0xE;
556 else if (fint > 17500000 && fint <= 21000000)
557 f = 0xF;
558 else
559 pr_debug("clock: unknown freqsel setting for %d\n", n);
560
561 return f;
562 }
563
564 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
565
566 /*
567 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
568 * @clk: pointer to a DPLL struct clk
569 *
570 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
571 * readiness before returning. Will save and restore the DPLL's
572 * autoidle state across the enable, per the CDP code. If the DPLL
573 * locked successfully, return 0; if the DPLL did not lock in the time
574 * allotted, or DPLL3 was passed in, return -EINVAL.
575 */
576 static int _omap3_noncore_dpll_lock(struct clk *clk)
577 {
578 u8 ai;
579 int r;
580
581 if (clk == &dpll3_ck)
582 return -EINVAL;
583
584 pr_debug("clock: locking DPLL %s\n", clk->name);
585
586 ai = omap3_dpll_autoidle_read(clk);
587
588 omap3_dpll_deny_idle(clk);
589
590 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
591
592 r = _omap3_wait_dpll_status(clk, 1);
593
594 if (ai)
595 omap3_dpll_allow_idle(clk);
596
597 return r;
598 }
599
600 /*
601 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
602 * @clk: pointer to a DPLL struct clk
603 *
604 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
605 * bypass mode, the DPLL's rate is set equal to its parent clock's
606 * rate. Waits for the DPLL to report readiness before returning.
607 * Will save and restore the DPLL's autoidle state across the enable,
608 * per the CDP code. If the DPLL entered bypass mode successfully,
609 * return 0; if the DPLL did not enter bypass in the time allotted, or
610 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
611 * return -EINVAL.
612 */
613 static int _omap3_noncore_dpll_bypass(struct clk *clk)
614 {
615 int r;
616 u8 ai;
617
618 if (clk == &dpll3_ck)
619 return -EINVAL;
620
621 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
622 return -EINVAL;
623
624 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
625 clk->name);
626
627 ai = omap3_dpll_autoidle_read(clk);
628
629 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
630
631 r = _omap3_wait_dpll_status(clk, 0);
632
633 if (ai)
634 omap3_dpll_allow_idle(clk);
635 else
636 omap3_dpll_deny_idle(clk);
637
638 return r;
639 }
640
641 /*
642 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
643 * @clk: pointer to a DPLL struct clk
644 *
645 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
646 * restore the DPLL's autoidle state across the stop, per the CDP
647 * code. If DPLL3 was passed in, or the DPLL does not support
648 * low-power stop, return -EINVAL; otherwise, return 0.
649 */
650 static int _omap3_noncore_dpll_stop(struct clk *clk)
651 {
652 u8 ai;
653
654 if (clk == &dpll3_ck)
655 return -EINVAL;
656
657 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
658 return -EINVAL;
659
660 pr_debug("clock: stopping DPLL %s\n", clk->name);
661
662 ai = omap3_dpll_autoidle_read(clk);
663
664 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
665
666 if (ai)
667 omap3_dpll_allow_idle(clk);
668 else
669 omap3_dpll_deny_idle(clk);
670
671 return 0;
672 }
673
674 /**
675 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
676 * @clk: pointer to a DPLL struct clk
677 *
678 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
679 * The choice of modes depends on the DPLL's programmed rate: if it is
680 * the same as the DPLL's parent clock, it will enter bypass;
681 * otherwise, it will enter lock. This code will wait for the DPLL to
682 * indicate readiness before returning, unless the DPLL takes too long
683 * to enter the target state. Intended to be used as the struct clk's
684 * enable function. If DPLL3 was passed in, or the DPLL does not
685 * support low-power stop, or if the DPLL took too long to enter
686 * bypass or lock, return -EINVAL; otherwise, return 0.
687 */
688 static int omap3_noncore_dpll_enable(struct clk *clk)
689 {
690 int r;
691 struct dpll_data *dd;
692
693 if (clk == &dpll3_ck)
694 return -EINVAL;
695
696 dd = clk->dpll_data;
697 if (!dd)
698 return -EINVAL;
699
700 if (clk->rate == dd->clk_bypass->rate) {
701 WARN_ON(clk->parent != dd->clk_bypass);
702 r = _omap3_noncore_dpll_bypass(clk);
703 } else {
704 WARN_ON(clk->parent != dd->clk_ref);
705 r = _omap3_noncore_dpll_lock(clk);
706 }
707 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
708 if (!r)
709 clk->rate = omap2_get_dpll_rate(clk);
710
711 return r;
712 }
713
714 /**
715 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
716 * @clk: pointer to a DPLL struct clk
717 *
718 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
719 * The choice of modes depends on the DPLL's programmed rate: if it is
720 * the same as the DPLL's parent clock, it will enter bypass;
721 * otherwise, it will enter lock. This code will wait for the DPLL to
722 * indicate readiness before returning, unless the DPLL takes too long
723 * to enter the target state. Intended to be used as the struct clk's
724 * enable function. If DPLL3 was passed in, or the DPLL does not
725 * support low-power stop, or if the DPLL took too long to enter
726 * bypass or lock, return -EINVAL; otherwise, return 0.
727 */
728 static void omap3_noncore_dpll_disable(struct clk *clk)
729 {
730 if (clk == &dpll3_ck)
731 return;
732
733 _omap3_noncore_dpll_stop(clk);
734 }
735
736
737 /* Non-CORE DPLL rate set code */
738
739 /*
740 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
741 * @clk: struct clk * of DPLL to set
742 * @m: DPLL multiplier to set
743 * @n: DPLL divider to set
744 * @freqsel: FREQSEL value to set
745 *
746 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
747 * lock.. Returns -EINVAL upon error, or 0 upon success.
748 */
749 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
750 {
751 struct dpll_data *dd = clk->dpll_data;
752 u32 v;
753
754 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
755 _omap3_noncore_dpll_bypass(clk);
756
757 /* Set jitter correction */
758 v = __raw_readl(dd->control_reg);
759 v &= ~dd->freqsel_mask;
760 v |= freqsel << __ffs(dd->freqsel_mask);
761 __raw_writel(v, dd->control_reg);
762
763 /* Set DPLL multiplier, divider */
764 v = __raw_readl(dd->mult_div1_reg);
765 v &= ~(dd->mult_mask | dd->div1_mask);
766 v |= m << __ffs(dd->mult_mask);
767 v |= (n - 1) << __ffs(dd->div1_mask);
768 __raw_writel(v, dd->mult_div1_reg);
769
770 /* We let the clock framework set the other output dividers later */
771
772 /* REVISIT: Set ramp-up delay? */
773
774 _omap3_noncore_dpll_lock(clk);
775
776 return 0;
777 }
778
779 /**
780 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
781 * @clk: struct clk * of DPLL to set
782 * @rate: rounded target rate
783 *
784 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
785 * low-power bypass, and the target rate is the bypass source clock
786 * rate, then configure the DPLL for bypass. Otherwise, round the
787 * target rate if it hasn't been done already, then program and lock
788 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
789 */
790 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
791 {
792 struct clk *new_parent = NULL;
793 u16 freqsel;
794 struct dpll_data *dd;
795 int ret;
796
797 if (!clk || !rate)
798 return -EINVAL;
799
800 dd = clk->dpll_data;
801 if (!dd)
802 return -EINVAL;
803
804 if (rate == omap2_get_dpll_rate(clk))
805 return 0;
806
807 /*
808 * Ensure both the bypass and ref clocks are enabled prior to
809 * doing anything; we need the bypass clock running to reprogram
810 * the DPLL.
811 */
812 omap2_clk_enable(dd->clk_bypass);
813 omap2_clk_enable(dd->clk_ref);
814
815 if (dd->clk_bypass->rate == rate &&
816 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
817 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
818
819 ret = _omap3_noncore_dpll_bypass(clk);
820 if (!ret)
821 new_parent = dd->clk_bypass;
822 } else {
823 if (dd->last_rounded_rate != rate)
824 omap2_dpll_round_rate(clk, rate);
825
826 if (dd->last_rounded_rate == 0)
827 return -EINVAL;
828
829 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
830 if (!freqsel)
831 WARN_ON(1);
832
833 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
834 clk->name, rate);
835
836 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
837 dd->last_rounded_n, freqsel);
838 if (!ret)
839 new_parent = dd->clk_ref;
840 }
841 if (!ret) {
842 /*
843 * Switch the parent clock in the heirarchy, and make sure
844 * that the new parent's usecount is correct. Note: we
845 * enable the new parent before disabling the old to avoid
846 * any unnecessary hardware disable->enable transitions.
847 */
848 if (clk->usecount) {
849 omap2_clk_enable(new_parent);
850 omap2_clk_disable(clk->parent);
851 }
852 clk_reparent(clk, new_parent);
853 clk->rate = rate;
854 }
855 omap2_clk_disable(dd->clk_ref);
856 omap2_clk_disable(dd->clk_bypass);
857
858 return 0;
859 }
860
861 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
862 {
863 /*
864 * According to the 12-5 CDP code from TI, "Limitation 2.5"
865 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
866 * on DPLL4.
867 */
868 if (omap_rev_is_1_0()) {
869 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
870 "silicon 'Limitation 2.5' on 3430ES1.\n");
871 return -EINVAL;
872 }
873 return omap3_noncore_dpll_set_rate(clk, rate);
874 }
875
876
877 /*
878 * CORE DPLL (DPLL3) rate programming functions
879 *
880 * These call into SRAM code to do the actual CM writes, since the SDRAM
881 * is clocked from DPLL3.
882 */
883
884 /**
885 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
886 * @clk: struct clk * of DPLL to set
887 * @rate: rounded target rate
888 *
889 * Program the DPLL M2 divider with the rounded target rate. Returns
890 * -EINVAL upon error, or 0 upon success.
891 */
892 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
893 {
894 u32 new_div = 0;
895 u32 unlock_dll = 0;
896 u32 c;
897 unsigned long validrate, sdrcrate, mpurate;
898 struct omap_sdrc_params *sdrc_cs0;
899 struct omap_sdrc_params *sdrc_cs1;
900 int ret;
901
902 if (!clk || !rate)
903 return -EINVAL;
904
905 if (clk != &dpll3_m2_ck)
906 return -EINVAL;
907
908 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
909 if (validrate != rate)
910 return -EINVAL;
911
912 sdrcrate = sdrc_ick.rate;
913 if (rate > clk->rate)
914 sdrcrate <<= ((rate / clk->rate) >> 1);
915 else
916 sdrcrate >>= ((clk->rate / rate) >> 1);
917
918 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
919 if (ret)
920 return -EINVAL;
921
922 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
923 pr_debug("clock: will unlock SDRC DLL\n");
924 unlock_dll = 1;
925 }
926
927 /*
928 * XXX This only needs to be done when the CPU frequency changes
929 */
930 mpurate = arm_fck.rate / CYCLES_PER_MHZ;
931 c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
932 c += 1; /* for safety */
933 c *= SDRC_MPURATE_LOOPS;
934 c >>= SDRC_MPURATE_SCALE;
935 if (c == 0)
936 c = 1;
937
938 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
939 validrate);
940 pr_debug("clock: SDRC CS0 timing params used:"
941 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
942 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
943 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
944 if (sdrc_cs1)
945 pr_debug("clock: SDRC CS1 timing params used: "
946 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
947 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
948 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
949
950 if (sdrc_cs1)
951 omap3_configure_core_dpll(
952 new_div, unlock_dll, c, rate > clk->rate,
953 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
954 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
955 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
956 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
957 else
958 omap3_configure_core_dpll(
959 new_div, unlock_dll, c, rate > clk->rate,
960 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
961 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
962 0, 0, 0, 0);
963
964 return 0;
965 }
966
967
968 static const struct clkops clkops_noncore_dpll_ops = {
969 .enable = &omap3_noncore_dpll_enable,
970 .disable = &omap3_noncore_dpll_disable,
971 };
972
973 /* DPLL autoidle read/set code */
974
975
976 /**
977 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
978 * @clk: struct clk * of the DPLL to read
979 *
980 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
981 * -EINVAL if passed a null pointer or if the struct clk does not
982 * appear to refer to a DPLL.
983 */
984 static u32 omap3_dpll_autoidle_read(struct clk *clk)
985 {
986 const struct dpll_data *dd;
987 u32 v;
988
989 if (!clk || !clk->dpll_data)
990 return -EINVAL;
991
992 dd = clk->dpll_data;
993
994 v = __raw_readl(dd->autoidle_reg);
995 v &= dd->autoidle_mask;
996 v >>= __ffs(dd->autoidle_mask);
997
998 return v;
999 }
1000
1001 /**
1002 * omap3_dpll_allow_idle - enable DPLL autoidle bits
1003 * @clk: struct clk * of the DPLL to operate on
1004 *
1005 * Enable DPLL automatic idle control. This automatic idle mode
1006 * switching takes effect only when the DPLL is locked, at least on
1007 * OMAP3430. The DPLL will enter low-power stop when its downstream
1008 * clocks are gated. No return value.
1009 */
1010 static void omap3_dpll_allow_idle(struct clk *clk)
1011 {
1012 const struct dpll_data *dd;
1013 u32 v;
1014
1015 if (!clk || !clk->dpll_data)
1016 return;
1017
1018 dd = clk->dpll_data;
1019
1020 /*
1021 * REVISIT: CORE DPLL can optionally enter low-power bypass
1022 * by writing 0x5 instead of 0x1. Add some mechanism to
1023 * optionally enter this mode.
1024 */
1025 v = __raw_readl(dd->autoidle_reg);
1026 v &= ~dd->autoidle_mask;
1027 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
1028 __raw_writel(v, dd->autoidle_reg);
1029 }
1030
1031 /**
1032 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
1033 * @clk: struct clk * of the DPLL to operate on
1034 *
1035 * Disable DPLL automatic idle control. No return value.
1036 */
1037 static void omap3_dpll_deny_idle(struct clk *clk)
1038 {
1039 const struct dpll_data *dd;
1040 u32 v;
1041
1042 if (!clk || !clk->dpll_data)
1043 return;
1044
1045 dd = clk->dpll_data;
1046
1047 v = __raw_readl(dd->autoidle_reg);
1048 v &= ~dd->autoidle_mask;
1049 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
1050 __raw_writel(v, dd->autoidle_reg);
1051 }
1052
1053 /* Clock control for DPLL outputs */
1054
1055 /**
1056 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
1057 * @clk: DPLL output struct clk
1058 *
1059 * Using parent clock DPLL data, look up DPLL state. If locked, set our
1060 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
1061 */
1062 static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
1063 {
1064 const struct dpll_data *dd;
1065 unsigned long rate;
1066 u32 v;
1067 struct clk *pclk;
1068
1069 /* Walk up the parents of clk, looking for a DPLL */
1070 pclk = clk->parent;
1071 while (pclk && !pclk->dpll_data)
1072 pclk = pclk->parent;
1073
1074 /* clk does not have a DPLL as a parent? */
1075 WARN_ON(!pclk);
1076
1077 dd = pclk->dpll_data;
1078
1079 WARN_ON(!dd->enable_mask);
1080
1081 v = __raw_readl(dd->control_reg) & dd->enable_mask;
1082 v >>= __ffs(dd->enable_mask);
1083 if (v != OMAP3XXX_EN_DPLL_LOCKED)
1084 rate = clk->parent->rate;
1085 else
1086 rate = clk->parent->rate * 2;
1087 return rate;
1088 }
1089
1090 /* Common clock code */
1091
1092 /*
1093 * As it is structured now, this will prevent an OMAP2/3 multiboot
1094 * kernel from compiling. This will need further attention.
1095 */
1096 #if defined(CONFIG_ARCH_OMAP3)
1097
1098 #ifdef CONFIG_CPU_FREQ
1099 static struct cpufreq_frequency_table freq_table[MAX_VDD1_OPP+1];
1100
1101 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
1102 {
1103 struct omap_opp *prcm;
1104 int i = 0;
1105
1106 if (!mpu_opps)
1107 return;
1108
1109 prcm = mpu_opps + MAX_VDD1_OPP;
1110 for (; prcm->rate; prcm--) {
1111 freq_table[i].index = i;
1112 freq_table[i].frequency = prcm->rate / 1000;
1113 i++;
1114 }
1115
1116 if (i == 0) {
1117 printk(KERN_WARNING "%s: failed to initialize frequency \
1118 table\n",
1119 __func__);
1120 return;
1121 }
1122
1123 freq_table[i].index = i;
1124 freq_table[i].frequency = CPUFREQ_TABLE_END;
1125
1126 *table = &freq_table[0];
1127 }
1128 #endif
1129
1130 static struct clk_functions omap2_clk_functions = {
1131 .clk_enable = omap2_clk_enable,
1132 .clk_disable = omap2_clk_disable,
1133 .clk_round_rate = omap2_clk_round_rate,
1134 .clk_set_rate = omap2_clk_set_rate,
1135 .clk_set_parent = omap2_clk_set_parent,
1136 .clk_disable_unused = omap2_clk_disable_unused,
1137 #ifdef CONFIG_CPU_FREQ
1138 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
1139 #endif
1140 };
1141
1142 /*
1143 * Set clocks for bypass mode for reboot to work.
1144 */
1145 void omap2_clk_prepare_for_reboot(void)
1146 {
1147 /* REVISIT: Not ready for 343x */
1148 #if 0
1149 u32 rate;
1150
1151 if (vclk == NULL || sclk == NULL)
1152 return;
1153
1154 rate = clk_get_rate(sclk);
1155 clk_set_rate(vclk, rate);
1156 #endif
1157 }
1158
1159 static void omap3_clk_lock_dpll5(void)
1160 {
1161 struct clk *dpll5_clk;
1162 struct clk *dpll5_m2_clk;
1163
1164 dpll5_clk = clk_get(NULL, "dpll5_ck");
1165 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
1166 clk_enable(dpll5_clk);
1167
1168 /* Enable autoidle to allow it to enter low power bypass */
1169 omap3_dpll_allow_idle(dpll5_clk);
1170
1171 /* Program dpll5_m2_clk divider for no division */
1172 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
1173 clk_enable(dpll5_m2_clk);
1174 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
1175
1176 clk_disable(dpll5_m2_clk);
1177 clk_disable(dpll5_clk);
1178 return;
1179 }
1180
1181 /* REVISIT: Move this init stuff out into clock.c */
1182
1183 /*
1184 * Switch the MPU rate if specified on cmdline.
1185 * We cannot do this early until cmdline is parsed.
1186 */
1187 static int __init omap2_clk_arch_init(void)
1188 {
1189 short opp=0, valid=0;
1190 short i;
1191 unsigned long dsprate, l3rate;
1192 struct omap_opp *opp_table;
1193 int l3div;
1194
1195 if (!mpurate)
1196 return -EINVAL;
1197
1198 if ((mpurate == S720M) && !omap3_has_720m()) {
1199 /*
1200 * Silicon doesn't support this rate.
1201 * Use the next highest.
1202 */
1203 mpurate = S600M;
1204 printk(KERN_ERR "*** This silicon doesn't support 720MHz\n");
1205 }
1206
1207 /* Check if mpurate is valid */
1208 if (mpu_opps) {
1209 opp_table = mpu_opps;
1210
1211 for (i = 1; opp_table[i].opp_id <= MAX_VDD1_OPP; i++) {
1212 if (opp_table[i].rate == mpurate) {
1213 valid = 1;
1214 break;
1215 }
1216 }
1217
1218 if (valid) {
1219 opp = opp_table[i].opp_id;
1220 printk(KERN_INFO "Switching to OPP:%d\n", opp);
1221 } else {
1222 printk(KERN_ERR "*** Invalid MPU rate specified\n");
1223 return 1;
1224 }
1225 }
1226
1227 if (clk_set_rate(&dpll1_ck, mpurate))
1228 printk(KERN_ERR "*** Unable to set MPU rate\n");
1229 omap3_dpll_recalc(&dpll1_ck);
1230
1231 /* Select VDD2_OPP2, if VDD1_OPP1 is chosen */
1232 if (opp == VDD1_OPP1) {
1233 l3div = cm_read_mod_reg(CORE_MOD, CM_CLKSEL) &
1234 OMAP3430_CLKSEL_L3_MASK;
1235
1236 l3rate = l3_opps[VDD2_OPP2].rate * l3div;
1237 if (clk_set_rate(&dpll3_m2_ck, l3rate))
1238 printk(KERN_ERR "*** Unable to set L3 rate(%ld)\n", l3rate);
1239 else
1240 printk(KERN_INFO "Switching to L3 rate:%ld\n", l3rate);
1241
1242 omap3_dpll_recalc(&dpll3_m2_ck);
1243 }
1244
1245 /* Get dsprate corresponding to the opp */
1246 if ((cpu_is_omap3430() || cpu_is_omap3530() || cpu_is_omap3525())
1247 && (dsp_opps)
1248 && (opp >= MIN_VDD1_OPP) && (opp <= MAX_VDD1_OPP)) {
1249 opp_table = dsp_opps;
1250
1251 for (i=0; opp_table[i].opp_id <= MAX_VDD1_OPP; i++)
1252 if (opp_table[i].opp_id == opp)
1253 break;
1254
1255 dsprate = opp_table[i].rate;
1256
1257 if (clk_set_rate(&dpll2_ck, dsprate))
1258 printk(KERN_ERR "*** Unable to set IVA2 rate\n");
1259 omap3_dpll_recalc(&dpll2_ck);
1260 }
1261
1262 recalculate_root_clocks();
1263
1264 printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
1265 "%ld.%01ld/%ld/%ld MHz\n",
1266 (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
1267 (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
1268 printk(KERN_INFO "IVA2 clocking rate: %ld MHz\n",
1269 (iva2_ck.rate / 1000000)) ;
1270
1271 calibrate_delay();
1272
1273 return 0;
1274 }
1275 arch_initcall(omap2_clk_arch_init);
1276
1277 int __init omap2_clk_init(void)
1278 {
1279 /* struct prcm_config *prcm; */
1280 struct omap_clk *c;
1281 /* u32 clkrate; */
1282 u32 cpu_clkflg;
1283
1284 if (cpu_is_omap3517()) {
1285 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
1286 cpu_clkflg = CK_3517;
1287 } else if (cpu_is_omap3505()) {
1288 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
1289 cpu_clkflg = CK_3505;
1290 } else if (cpu_is_omap34xx()) {
1291 cpu_mask = RATE_IN_343X;
1292 cpu_clkflg = CK_343X;
1293
1294 /*
1295 * Update this if there are further clock changes between ES2
1296 * and production parts
1297 */
1298 if (omap_rev_is_1_0()) {
1299 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
1300 cpu_clkflg |= CK_3430ES1;
1301 } else {
1302 cpu_mask |= RATE_IN_3430ES2;
1303 cpu_clkflg |= CK_3430ES2;
1304 }
1305 }
1306
1307 clk_init(&omap2_clk_functions);
1308
1309 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
1310 clk_preinit(c->lk.clk);
1311
1312 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
1313 if (c->cpu & cpu_clkflg) {
1314 clkdev_add(&c->lk);
1315 clk_register(c->lk.clk);
1316 omap2_init_clk_clkdm(c->lk.clk);
1317 }
1318
1319 /* REVISIT: Not yet ready for OMAP3 */
1320 #if 0
1321 /* Check the MPU rate set by bootloader */
1322 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
1323 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1324 if (!(prcm->flags & cpu_mask))
1325 continue;
1326 if (prcm->xtal_speed != sys_ck.rate)
1327 continue;
1328 if (prcm->dpll_speed <= clkrate)
1329 break;
1330 }
1331 curr_prcm_set = prcm;
1332 #endif
1333
1334 recalculate_root_clocks();
1335
1336 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
1337 "%ld.%01ld/%ld/%ld MHz\n",
1338 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
1339 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
1340 printk(KERN_INFO "IVA2 clocking rate: %ld MHz\n",
1341 (iva2_ck.rate / 1000000)) ;
1342
1343 /*
1344 * Only enable those clocks we will need, let the drivers
1345 * enable other clocks as necessary
1346 */
1347 clk_enable_init_clocks();
1348
1349 /*
1350 * Lock DPLL5 and put it in autoidle.
1351 */
1352 if (omap_rev() >= OMAP3430_REV_ES2_0)
1353 omap3_clk_lock_dpll5();
1354
1355 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
1356 /* REVISIT: not yet ready for 343x */
1357 #if 0
1358 vclk = clk_get(NULL, "virt_prcm_set");
1359 sclk = clk_get(NULL, "sys_ck");
1360 #endif
1361 return 0;
1362 }
1363
1364 #endif /* CONFIG_ARCH_OMAP3 */
Linux for Ginger Game Console