arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27
  28 #include <plat/prcm.h>
  29 #include <plat/irqs.h>
  30 #include <plat/powerdomain.h>
  31 #include <plat/clockdomain.h>
  32 #include <plat/control.h>
  33 #include <plat/serial.h>
  34
  35 #include "pm.h"
  36
  37 #ifdef CONFIG_CPU_IDLE
  38
  39 #define OMAP3_MAX_STATES 7
  40 #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
  41 #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
  42 #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
  43 #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
  44 #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
  45 #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
  46 #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
  47
  48 #define OMAP3_STATE_MAX OMAP3_STATE_C7
  49
  50 struct omap3_processor_cx {
  51         u8 valid;
  52         u8 type;
  53         u32 sleep_latency;
  54         u32 wakeup_latency;
  55         u32 mpu_state;
  56         u32 core_state;
  57         u32 threshold;
  58         u32 flags;
  59 };
  60
  61 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
  62 struct omap3_processor_cx current_cx_state;
  63 struct powerdomain *mpu_pd, *core_pd;
  64
  65 /*
  66  * The latencies/thresholds for various C states have
  67  * to be configured from the respective board files.
  68  * These are some default values (which might not provide
  69  * the best power savings) used on boards which do not
  70  * pass these details from the board file.
  71  */
  72 static struct cpuidle_params cpuidle_params_table[] = {
  73         /* C1 */
  74         {2, 2, 5},
  75         /* C2 */
  76         {10, 10, 30},
  77         /* C3 */
  78         {50, 50, 300},
  79         /* C4 */
  80         {1500, 1800, 4000},
  81         /* C5 */
  82         {2500, 7500, 12000},
  83         /* C6 */
  84         {3000, 8500, 15000},
  85         /* C7 */
  86         {10000, 30000, 300000},
  87 };
  88
  89 static int omap3_idle_bm_check(void)
  90 {
  91         if (!omap3_can_sleep())
  92                 return 1;
  93         return 0;
  94 }
  95
  96 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  97                                 struct clockdomain *clkdm)
  98 {
  99         omap2_clkdm_allow_idle(clkdm);
 100         return 0;
 101 }
 102
 103 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
 104                                 struct clockdomain *clkdm)
 105 {
 106         omap2_clkdm_deny_idle(clkdm);
 107         return 0;
 108 }
 109
 110 /**
 111  * omap3_enter_idle - Programs OMAP3 to enter the specified state
 112  * @dev: cpuidle device
 113  * @state: The target state to be programmed
 114  *
 115  * Called from the CPUidle framework to program the device to the
 116  * specified target state selected by the governor.
 117  */
 118 static int omap3_enter_idle(struct cpuidle_device *dev,
 119                         struct cpuidle_state *state)
 120 {
 121         struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
 122         struct timespec ts_preidle, ts_postidle, ts_idle;
 123         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 124
 125         current_cx_state = *cx;
 126
 127         /* Used to keep track of the total time in idle */
 128         getnstimeofday(&ts_preidle);
 129
 130         local_irq_disable();
 131         local_fiq_disable();
 132
 133         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 134         pwrdm_set_next_pwrst(core_pd, core_state);
 135
 136         if (omap_irq_pending() || need_resched())
 137                 goto return_sleep_time;
 138
 139         if (cx->type == OMAP3_STATE_C1) {
 140                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 141                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 142         }
 143
 144         /* Execute ARM wfi */
 145         omap_sram_idle();
 146
 147         if (cx->type == OMAP3_STATE_C1) {
 148                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 149                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 150         }
 151
 152 return_sleep_time:
 153         getnstimeofday(&ts_postidle);
 154         ts_idle = timespec_sub(ts_postidle, ts_preidle);
 155
 156         local_irq_enable();
 157         local_fiq_enable();
 158
 159         return (u32)timespec_to_ns(&ts_idle)/1000;
 160 }
 161
 162
 163 /* next_valid_state - Find next valid c-state
 164  * @dev: cpuidle device
 165  * @state: Currently selected c-state
 166  *
 167  * If the current state is valid, it is returned back to the caller.
 168  * Else, this function searches for a lower c-state which is still
 169  * valid (as defined in omap3_power_states[]).
 170  */
 171 static struct cpuidle_state* next_valid_state(struct cpuidle_device *dev,
 172                                                 struct cpuidle_state *curr)
 173 {
 174         struct cpuidle_state *next = NULL;
 175         struct omap3_processor_cx *cx;
 176
 177         cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
 178
 179         /* Check if current state is valid */
 180         if (cx->valid) {
 181                 next = curr;
 182         }
 183         else {
 184                 u8 idx = OMAP3_STATE_MAX;
 185
 186                 /* Reach the current state starting at highest C-state */
 187                 for (; idx >= OMAP3_STATE_C1; idx--) {
 188                         if (&dev->states[idx] == curr) {
 189                                 next = &dev->states[idx];
 190                                 break;
 191                         }
 192                 }
 193
 194                 /*
 195                  * Should never hit this condition.
 196                  */
 197                 BUG_ON(next == NULL);
 198
 199                 /* Drop to next valid state.
 200                  * Start search from the next (lower) state.
 201                  */
 202                 idx--;
 203                 for (; idx >= OMAP3_STATE_C1; idx--) {
 204                         if (((struct omap3_processor_cx *)
 205                                 cpuidle_get_statedata(
 206                                         &dev->states[idx]))->valid) {
 207                                 next = &dev->states[idx];
 208                                 break;
 209                         }
 210                 }
 211                 /*
 212                  * C1 and C2 are always valid.
 213                  * So, no need to check for 'next==NULL' outside this loop.
 214                  */
 215         }
 216
 217         return next;
 218 }
 219
 220
 221 /**
 222  * omap3_enter_idle_bm - Checks for any bus activity
 223  * @dev: cpuidle device
 224  * @state: The target state to be programmed
 225  *
 226  * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
 227  * function checks for any pending activity and then programs the
 228  * device to the specified or a safer state.
 229  */
 230 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 231                                struct cpuidle_state *state)
 232 {
 233         struct cpuidle_state *new_state= next_valid_state(dev, state);
 234
 235         if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
 236                 BUG_ON(!dev->safe_state);
 237                 new_state = dev->safe_state;
 238         }
 239
 240         dev->last_state = new_state;
 241         return omap3_enter_idle(dev, new_state);
 242 }
 243
 244 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 245
 246 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
 247 {
 248         int i;
 249
 250         if (!cpuidle_board_params)
 251                 return;
 252
 253         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
 254                 cpuidle_params_table[i].sleep_latency =
 255                         cpuidle_board_params[i].sleep_latency;
 256                 cpuidle_params_table[i].wake_latency =
 257                         cpuidle_board_params[i].wake_latency;
 258                 cpuidle_params_table[i].threshold =
 259                         cpuidle_board_params[i].threshold;
 260         }
 261         return;
 262 }
 263
 264 /**
 265  * omap3_cpuidle_update_states - Update the cpuidle states.
 266  *
 267  * Currently, this function toggles the validity of idle states based upon
 268  * the flag 'enable_off_mode'. When the flag is set all states are valid.
 269  * Else, states leading to OFF state set to be invalid.
 270  */
 271 void omap3_cpuidle_update_states(void)
 272 {
 273         int i;
 274
 275         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
 276                 if (enable_off_mode) {
 277                         omap3_power_states[i].valid = 1;
 278                 }
 279                 else {
 280                         if ((omap3_power_states[i].mpu_state
 281                                         == PWRDM_POWER_OFF)
 282                                 || (omap3_power_states[i].core_state
 283                                         == PWRDM_POWER_OFF))
 284                         omap3_power_states[i].valid = 0;
 285                 }
 286         }
 287 }
 288
 289
 290 /* omap3_init_power_states - Initialises the OMAP3 specific C states.
 291  *
 292  * Below is the desciption of each C state.
 293  *      C1 . MPU WFI + Core active
 294  *      C2 . MPU WFI + Core inactive
 295  *      C3 . MPU CSWR + Core inactive
 296  *      C4 . MPU OFF + Core inactive
 297  *      C5 . MPU CSWR + Core CSWR
 298  *      C6 . MPU OFF + Core CSWR
 299  *      C7 . MPU OFF + Core OFF
 300  */
 301 void omap_init_power_states(void)
 302 {
 303         /* C1 . MPU WFI + Core active */
 304         omap3_power_states[OMAP3_STATE_C1].valid = 1;
 305         omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
 306         omap3_power_states[OMAP3_STATE_C1].sleep_latency =
 307                         cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
 308         omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
 309                         cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
 310         omap3_power_states[OMAP3_STATE_C1].threshold =
 311                         cpuidle_params_table[OMAP3_STATE_C1].threshold;
 312         omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
 313         omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
 314         omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
 315
 316         /* C2 . MPU WFI + Core inactive */
 317         omap3_power_states[OMAP3_STATE_C2].valid = 1;
 318         omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
 319         omap3_power_states[OMAP3_STATE_C2].sleep_latency =
 320                         cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
 321         omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
 322                         cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
 323         omap3_power_states[OMAP3_STATE_C2].threshold =
 324                         cpuidle_params_table[OMAP3_STATE_C2].threshold;
 325         omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
 326         omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
 327         omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
 328
 329         /* C3 . MPU CSWR + Core inactive */
 330         omap3_power_states[OMAP3_STATE_C3].valid = 1;
 331         omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
 332         omap3_power_states[OMAP3_STATE_C3].sleep_latency =
 333                         cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
 334         omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
 335                         cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
 336         omap3_power_states[OMAP3_STATE_C3].threshold =
 337                         cpuidle_params_table[OMAP3_STATE_C3].threshold;
 338         omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
 339         omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
 340         omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
 341                                 CPUIDLE_FLAG_CHECK_BM;
 342
 343         /* C4 . MPU OFF + Core inactive */
 344         omap3_power_states[OMAP3_STATE_C4].valid = 1;
 345         omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
 346         omap3_power_states[OMAP3_STATE_C4].sleep_latency =
 347                         cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
 348         omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
 349                         cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
 350         omap3_power_states[OMAP3_STATE_C4].threshold =
 351                         cpuidle_params_table[OMAP3_STATE_C4].threshold;
 352         omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
 353         omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
 354         omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
 355                                 CPUIDLE_FLAG_CHECK_BM;
 356
 357         /* C5 . MPU CSWR + Core CSWR*/
 358         omap3_power_states[OMAP3_STATE_C5].valid = 1;
 359         omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
 360         omap3_power_states[OMAP3_STATE_C5].sleep_latency =
 361                         cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
 362         omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
 363                         cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
 364         omap3_power_states[OMAP3_STATE_C5].threshold =
 365                         cpuidle_params_table[OMAP3_STATE_C5].threshold;
 366         omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
 367         omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
 368         omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
 369                                 CPUIDLE_FLAG_CHECK_BM;
 370
 371         /* C6 . MPU OFF + Core CSWR */
 372         omap3_power_states[OMAP3_STATE_C6].valid = 1;
 373         omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
 374         omap3_power_states[OMAP3_STATE_C6].sleep_latency =
 375                         cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
 376         omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
 377                         cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
 378         omap3_power_states[OMAP3_STATE_C6].threshold =
 379                         cpuidle_params_table[OMAP3_STATE_C6].threshold;
 380         omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
 381         omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
 382         omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
 383                                 CPUIDLE_FLAG_CHECK_BM;
 384
 385         /* C7 . MPU OFF + Core OFF */
 386         omap3_power_states[OMAP3_STATE_C7].valid = 1;
 387         omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
 388         omap3_power_states[OMAP3_STATE_C7].sleep_latency =
 389                         cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
 390         omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
 391                         cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
 392         omap3_power_states[OMAP3_STATE_C7].threshold =
 393                         cpuidle_params_table[OMAP3_STATE_C7].threshold;
 394         omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
 395         omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
 396         omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
 397                                 CPUIDLE_FLAG_CHECK_BM;
 398 }
 399
 400 struct cpuidle_driver omap3_idle_driver = {
 401         .name =         "omap3_idle",
 402         .owner =        THIS_MODULE,
 403 };
 404
 405 /**
 406  * omap3_idle_init - Init routine for OMAP3 idle
 407  *
 408  * Registers the OMAP3 specific cpuidle driver with the cpuidle
 409  * framework with the valid set of states.
 410  */
 411 int __init omap3_idle_init(void)
 412 {
 413         int i, count = 0;
 414         struct omap3_processor_cx *cx;
 415         struct cpuidle_state *state;
 416         struct cpuidle_device *dev;
 417
 418         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 419         core_pd = pwrdm_lookup("core_pwrdm");
 420
 421         omap_init_power_states();
 422         cpuidle_register_driver(&omap3_idle_driver);
 423
 424         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 425
 426         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
 427                 cx = &omap3_power_states[i];
 428                 state = &dev->states[count];
 429
 430                 if (!cx->valid)
 431                         continue;
 432                 cpuidle_set_statedata(state, cx);
 433                 state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
 434                 state->target_residency = cx->threshold;
 435                 state->flags = cx->flags;
 436                 state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
 437                         omap3_enter_idle_bm : omap3_enter_idle;
 438                 if (cx->type == OMAP3_STATE_C1)
 439                         dev->safe_state = state;
 440                 sprintf(state->name, "C%d", count+1);
 441                 count++;
 442         }
 443
 444         if (!count)
 445                 return -EINVAL;
 446         dev->state_count = count;
 447
 448         omap3_cpuidle_update_states();
 449
 450         if (cpuidle_register_device(dev)) {
 451                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 452                        __func__);
 453                 return -EIO;
 454         }
 455
 456         return 0;
 457 }
 458 #else
 459 int __init omap3_idle_init(void)
 460 {
 461         return 0;
 462 }
 463 #endif /* CONFIG_CPU_IDLE */