arch/arm/mach-omap2/include/mach/entry-macro.S

   1 /*
   2  * arch/arm/plat-omap/include/mach/entry-macro.S
   3  *
   4  * Low-level IRQ helper macros for OMAP-based platforms
   5  *
   6  * Copyright (C) 2009 Texas Instruments
   7  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This file is licensed under  the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13 #include <mach/hardware.h>
  14 #include <mach/io.h>
  15 #include <mach/irqs.h>
  16 #include <asm/hardware/gic.h>
  17
  18 #include <plat/omap24xx.h>
  19 #include <plat/omap34xx.h>
  20
  21 /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
  22 #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
  23 #define OMAP2_VA_IC_BASE                OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
  24 #elif defined(CONFIG_ARCH_OMAP34XX)
  25 #define OMAP2_VA_IC_BASE                OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
  26 #endif
  27 #if defined(CONFIG_ARCH_OMAP4)
  28 #include <plat/omap44xx.h>
  29 #endif
  30 #define INTCPS_SIR_IRQ_OFFSET   0x0040          /* Active interrupt offset */
  31 #define ACTIVEIRQ_MASK          0x7f            /* Active interrupt bits */
  32
  33                 .macro  disable_fiq
  34                 .endm
  35
  36                 .macro  get_irqnr_preamble, base, tmp
  37                 .endm
  38
  39                 .macro  arch_ret_to_user, tmp1, tmp2
  40                 .endm
  41
  42 #ifndef CONFIG_ARCH_OMAP4
  43                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  44                 ldr     \base, =OMAP2_VA_IC_BASE
  45                 ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
  46                 cmp     \irqnr, #0x0
  47                 bne     2222f
  48                 ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
  49                 cmp     \irqnr, #0x0
  50                 bne     2222f
  51                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
  52                 cmp     \irqnr, #0x0
  53 2222:
  54                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
  55                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
  56
  57                 .endm
  58 #else
  59 #define OMAP44XX_VA_GIC_CPU_BASE        OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
  60
  61                 /*
  62                  * The interrupt numbering scheme is defined in the
  63                  * interrupt controller spec.  To wit:
  64                  *
  65                  * Interrupts 0-15 are IPI
  66                  * 16-28 are reserved
  67                  * 29-31 are local.  We allow 30 to be used for the watchdog.
  68                  * 32-1020 are global
  69                  * 1021-1022 are reserved
  70                  * 1023 is "spurious" (no interrupt)
  71                  *
  72                  * For now, we ignore all local interrupts so only return an
  73                  * interrupt if it's between 30 and 1020.  The test_for_ipi
  74                  * routine below will pick up on IPIs.
  75                  * A simple read from the controller will tell us the number
  76                  * of the highest priority enabled interrupt.
  77                  * We then just need to check whether it is in the
  78                  * valid range for an IRQ (30-1020 inclusive).
  79                  */
  80                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  81                 ldr     \base, =OMAP44XX_VA_GIC_CPU_BASE
  82                 ldr     \irqstat, [\base, #GIC_CPU_INTACK]
  83
  84                 ldr     \tmp, =1021
  85
  86                 bic     \irqnr, \irqstat, #0x1c00
  87
  88                 cmp     \irqnr, #29
  89                 cmpcc   \irqnr, \irqnr
  90                 cmpne   \irqnr, \tmp
  91                 cmpcs   \irqnr, \irqnr
  92                 .endm
  93
  94                 /* We assume that irqstat (the raw value of the IRQ acknowledge
  95                  * register) is preserved from the macro above.
  96                  * If there is an IPI, we immediately signal end of interrupt
  97                  * on the controller, since this requires the original irqstat
  98                  * value which we won't easily be able to recreate later.
  99                  */
 100
 101                 .macro test_for_ipi, irqnr, irqstat, base, tmp
 102                 bic     \irqnr, \irqstat, #0x1c00
 103                 cmp     \irqnr, #16
 104                 it      cc
 105                 strcc   \irqstat, [\base, #GIC_CPU_EOI]
 106                 it      cs
 107                 cmpcs   \irqnr, \irqnr
 108                 .endm
 109
 110                 /* As above, this assumes that irqstat and base are preserved */
 111
 112                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
 113                 bic     \irqnr, \irqstat, #0x1c00
 114                 mov     \tmp, #0
 115                 cmp     \irqnr, #29
 116                 itt     eq
 117                 moveq   \tmp, #1
 118                 streq   \irqstat, [\base, #GIC_CPU_EOI]
 119                 cmp     \tmp, #0
 120                 .endm
 121 #endif
 122
 123                 .macro  irq_prio_table
 124                 .endm