arch/arm/plat-omap/include/plat/dma.h

   1 /*
   2  *  arch/arm/plat-omap/include/mach/dma.h
   3  *
   4  *  Copyright (C) 2003 Nokia Corporation
   5  *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20  */
  21 #ifndef __ASM_ARCH_DMA_H
  22 #define __ASM_ARCH_DMA_H
  23
  24 /* Hardware registers for omap1 */
  25 #define OMAP1_DMA_BASE                  (0xfffed800)
  26
  27 #define OMAP1_DMA_GCR                   0x400
  28 #define OMAP1_DMA_GSCR                  0x404
  29 #define OMAP1_DMA_GRST                  0x408
  30 #define OMAP1_DMA_HW_ID                 0x442
  31 #define OMAP1_DMA_PCH2_ID               0x444
  32 #define OMAP1_DMA_PCH0_ID               0x446
  33 #define OMAP1_DMA_PCH1_ID               0x448
  34 #define OMAP1_DMA_PCHG_ID               0x44a
  35 #define OMAP1_DMA_PCHD_ID               0x44c
  36 #define OMAP1_DMA_CAPS_0_U              0x44e
  37 #define OMAP1_DMA_CAPS_0_L              0x450
  38 #define OMAP1_DMA_CAPS_1_U              0x452
  39 #define OMAP1_DMA_CAPS_1_L              0x454
  40 #define OMAP1_DMA_CAPS_2                0x456
  41 #define OMAP1_DMA_CAPS_3                0x458
  42 #define OMAP1_DMA_CAPS_4                0x45a
  43 #define OMAP1_DMA_PCH2_SR               0x460
  44 #define OMAP1_DMA_PCH0_SR               0x480
  45 #define OMAP1_DMA_PCH1_SR               0x482
  46 #define OMAP1_DMA_PCHD_SR               0x4c0
  47
  48 /* Hardware registers for omap2 and omap3 */
  49 #define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
  50 #define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
  51 #define OMAP44XX_DMA4_BASE              (L4_44XX_BASE + 0x56000)
  52
  53 #define OMAP_DMA4_REVISION              0x00
  54 #define OMAP_DMA4_GCR                   0x78
  55 #define OMAP_DMA4_IRQSTATUS_L0          0x08
  56 #define OMAP_DMA4_IRQSTATUS_L1          0x0c
  57 #define OMAP_DMA4_IRQSTATUS_L2          0x10
  58 #define OMAP_DMA4_IRQSTATUS_L3          0x14
  59 #define OMAP_DMA4_IRQENABLE_L0          0x18
  60 #define OMAP_DMA4_IRQENABLE_L1          0x1c
  61 #define OMAP_DMA4_IRQENABLE_L2          0x20
  62 #define OMAP_DMA4_IRQENABLE_L3          0x24
  63 #define OMAP_DMA4_SYSSTATUS             0x28
  64 #define OMAP_DMA4_OCP_SYSCONFIG         0x2c
  65 #define OMAP_DMA4_CAPS_0                0x64
  66 #define OMAP_DMA4_CAPS_2                0x6c
  67 #define OMAP_DMA4_CAPS_3                0x70
  68 #define OMAP_DMA4_CAPS_4                0x74
  69
  70 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
  71 #define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
  72
  73 /* Common channel specific registers for omap1 */
  74 #define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
  75 #define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
  76 #define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
  77 #define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
  78 #define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
  79 #define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
  80 #define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
  81 #define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
  82 #define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
  83 #define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
  84 #define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
  85 #define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
  86 #define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
  87 #define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
  88 #define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
  89
  90 /* Common channel specific registers for omap2 */
  91 #define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
  92 #define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
  93 #define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
  94 #define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
  95 #define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
  96 #define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
  97 #define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
  98 #define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
  99 #define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
 100 #define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
 101 #define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
 102 #define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
 103 #define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
 104 #define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
 105
 106 /* Channel specific registers only on omap1 */
 107 #define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
 108 #define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
 109 #define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
 110 #define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
 111 #define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
 112 #define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
 113 #define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
 114 #define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
 115 #define OMAP1_DMA_CCEN(n)               0
 116 #define OMAP1_DMA_CCFN(n)               0
 117
 118 /* Channel specific registers only on omap2 */
 119 #define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
 120 #define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
 121 #define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
 122 #define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
 123 #define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
 124
 125 /* Additional registers available on OMAP4 */
 126 #define OMAP_DMA4_CDP(n)                (0x60 * (n) + 0xd0)
 127 #define OMAP_DMA4_CNDP(n)               (0x60 * (n) + 0xd4)
 128 #define OMAP_DMA4_CCDN(n)               (0x60 * (n) + 0xd8)
 129
 130 /* Dummy defines to keep multi-omap compiles happy */
 131 #define OMAP1_DMA_REVISION              0
 132 #define OMAP1_DMA_IRQSTATUS_L0          0
 133 #define OMAP1_DMA_IRQENABLE_L0          0
 134 #define OMAP1_DMA_OCP_SYSCONFIG         0
 135 #define OMAP_DMA4_HW_ID                 0
 136 #define OMAP_DMA4_CAPS_0_L              0
 137 #define OMAP_DMA4_CAPS_0_U              0
 138 #define OMAP_DMA4_CAPS_1_L              0
 139 #define OMAP_DMA4_CAPS_1_U              0
 140 #define OMAP_DMA4_GSCR                  0
 141 #define OMAP_DMA4_CPC(n)                0
 142
 143 #define OMAP_DMA4_LCH_CTRL(n)           0
 144 #define OMAP_DMA4_COLOR_L(n)            0
 145 #define OMAP_DMA4_COLOR_U(n)            0
 146 #define OMAP_DMA4_CCR2(n)               0
 147 #define OMAP1_DMA_CSSA(n)               0
 148 #define OMAP1_DMA_CDSA(n)               0
 149 #define OMAP_DMA4_CSSA_L(n)             0
 150 #define OMAP_DMA4_CSSA_U(n)             0
 151 #define OMAP_DMA4_CDSA_L(n)             0
 152 #define OMAP_DMA4_CDSA_U(n)             0
 153 #define OMAP1_DMA_COLOR(n)              0
 154
 155 /*----------------------------------------------------------------------------*/
 156
 157 /* DMA channels for omap1 */
 158 #define OMAP_DMA_NO_DEVICE              0
 159 #define OMAP_DMA_MCSI1_TX               1
 160 #define OMAP_DMA_MCSI1_RX               2
 161 #define OMAP_DMA_I2C_RX                 3
 162 #define OMAP_DMA_I2C_TX                 4
 163 #define OMAP_DMA_EXT_NDMA_REQ           5
 164 #define OMAP_DMA_EXT_NDMA_REQ2          6
 165 #define OMAP_DMA_UWIRE_TX               7
 166 #define OMAP_DMA_MCBSP1_TX              8
 167 #define OMAP_DMA_MCBSP1_RX              9
 168 #define OMAP_DMA_MCBSP3_TX              10
 169 #define OMAP_DMA_MCBSP3_RX              11
 170 #define OMAP_DMA_UART1_TX               12
 171 #define OMAP_DMA_UART1_RX               13
 172 #define OMAP_DMA_UART2_TX               14
 173 #define OMAP_DMA_UART2_RX               15
 174 #define OMAP_DMA_MCBSP2_TX              16
 175 #define OMAP_DMA_MCBSP2_RX              17
 176 #define OMAP_DMA_UART3_TX               18
 177 #define OMAP_DMA_UART3_RX               19
 178 #define OMAP_DMA_CAMERA_IF_RX           20
 179 #define OMAP_DMA_MMC_TX                 21
 180 #define OMAP_DMA_MMC_RX                 22
 181 #define OMAP_DMA_NAND                   23
 182 #define OMAP_DMA_IRQ_LCD_LINE           24
 183 #define OMAP_DMA_MEMORY_STICK           25
 184 #define OMAP_DMA_USB_W2FC_RX0           26
 185 #define OMAP_DMA_USB_W2FC_RX1           27
 186 #define OMAP_DMA_USB_W2FC_RX2           28
 187 #define OMAP_DMA_USB_W2FC_TX0           29
 188 #define OMAP_DMA_USB_W2FC_TX1           30
 189 #define OMAP_DMA_USB_W2FC_TX2           31
 190
 191 /* These are only for 1610 */
 192 #define OMAP_DMA_CRYPTO_DES_IN          32
 193 #define OMAP_DMA_SPI_TX                 33
 194 #define OMAP_DMA_SPI_RX                 34
 195 #define OMAP_DMA_CRYPTO_HASH            35
 196 #define OMAP_DMA_CCP_ATTN               36
 197 #define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
 198 #define OMAP_DMA_CMT_APE_TX_CHAN_0      38
 199 #define OMAP_DMA_CMT_APE_RV_CHAN_0      39
 200 #define OMAP_DMA_CMT_APE_TX_CHAN_1      40
 201 #define OMAP_DMA_CMT_APE_RV_CHAN_1      41
 202 #define OMAP_DMA_CMT_APE_TX_CHAN_2      42
 203 #define OMAP_DMA_CMT_APE_RV_CHAN_2      43
 204 #define OMAP_DMA_CMT_APE_TX_CHAN_3      44
 205 #define OMAP_DMA_CMT_APE_RV_CHAN_3      45
 206 #define OMAP_DMA_CMT_APE_TX_CHAN_4      46
 207 #define OMAP_DMA_CMT_APE_RV_CHAN_4      47
 208 #define OMAP_DMA_CMT_APE_TX_CHAN_5      48
 209 #define OMAP_DMA_CMT_APE_RV_CHAN_5      49
 210 #define OMAP_DMA_CMT_APE_TX_CHAN_6      50
 211 #define OMAP_DMA_CMT_APE_RV_CHAN_6      51
 212 #define OMAP_DMA_CMT_APE_TX_CHAN_7      52
 213 #define OMAP_DMA_CMT_APE_RV_CHAN_7      53
 214 #define OMAP_DMA_MMC2_TX                54
 215 #define OMAP_DMA_MMC2_RX                55
 216 #define OMAP_DMA_CRYPTO_DES_OUT         56
 217
 218 /* DMA channels for 24xx */
 219 #define OMAP24XX_DMA_NO_DEVICE          0
 220 #define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
 221 #define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
 222 #define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
 223 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
 224 #define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
 225 #define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
 226 #define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
 227 #define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
 228 #define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
 229 #define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
 230 #define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
 231 #define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
 232 #define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
 233 #define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
 234 #define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
 235 #define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
 236 #define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
 237 #define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
 238 #define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
 239 #define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
 240 #define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
 241 #define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
 242 #define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
 243 #define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
 244 #define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
 245 #define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
 246 #define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
 247 #define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
 248 #define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
 249 #define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
 250 #define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
 251 #define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
 252 #define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
 253 #define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
 254 #define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
 255 #define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
 256 #define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
 257 #define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
 258 #define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
 259 #define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
 260 #define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
 261 #define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
 262 #define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
 263 #define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 264 #define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 265 #define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 266 #define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
 267 #define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
 268 #define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
 269 #define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
 270 #define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
 271 #define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
 272 #define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
 273 #define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
 274 #define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
 275 #define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
 276 #define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
 277 #define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
 278 #define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
 279 #define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
 280 #define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
 281 #define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
 282 #define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
 283 #define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
 284 #define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
 285 #define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
 286 #define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
 287 #define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
 288 #define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
 289 #define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
 290 #define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
 291 #define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
 292 #define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
 293 #define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
 294 #define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
 295 #define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
 296 #define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
 297 #define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
 298 #define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
 299 #define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
 300 #define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
 301 #define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
 302 #define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
 303 #define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
 304 #define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
 305 #define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
 306 #define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
 307 #define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
 308 #define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
 309 #define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
 310 #define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
 311 #define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
 312 #define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
 313 #define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
 314 #define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
 315 #define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
 316 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 317 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 318
 319 /* DMA request lines for 44xx */
 320 #define OMAP44XX_DMA_DSS_DISPC_REQ      6       /* S_DMA_5 */
 321 #define OMAP44XX_DMA_SYS_REQ2           7       /* S_DMA_6 */
 322 #define OMAP44XX_DMA_ISS_REQ1           9       /* S_DMA_8 */
 323 #define OMAP44XX_DMA_ISS_REQ2           10      /* S_DMA_9 */
 324 #define OMAP44XX_DMA_ISS_REQ3           12      /* S_DMA_11 */
 325 #define OMAP44XX_DMA_ISS_REQ4           13      /* S_DMA_12 */
 326 #define OMAP44XX_DMA_DSS_RFBI_REQ       14      /* S_DMA_13 */
 327 #define OMAP44XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
 328 #define OMAP44XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
 329 #define OMAP44XX_DMA_MCBSP2_TX          17      /* S_DMA_16 */
 330 #define OMAP44XX_DMA_MCBSP2_RX          18      /* S_DMA_17 */
 331 #define OMAP44XX_DMA_MCBSP3_TX          19      /* S_DMA_18 */
 332 #define OMAP44XX_DMA_MCBSP3_RX          20      /* S_DMA_19 */
 333 #define OMAP44XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
 334 #define OMAP44XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
 335 #define OMAP44XX_DMA_I2C3_TX            25      /* S_DMA_24 */
 336 #define OMAP44XX_DMA_I2C3_RX            26      /* S_DMA_25 */
 337 #define OMAP44XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 338 #define OMAP44XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 339 #define OMAP44XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 340 #define OMAP44XX_DMA_I2C2_RX            30      /* S_DMA_29 */
 341 #define OMAP44XX_DMA_MCBSP4_TX          31      /* S_DMA_30 */
 342 #define OMAP44XX_DMA_MCBSP4_RX          32      /* S_DMA_31 */
 343 #define OMAP44XX_DMA_MCBSP1_TX          33      /* S_DMA_32 */
 344 #define OMAP44XX_DMA_MCBSP1_RX          34      /* S_DMA_33 */
 345 #define OMAP44XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
 346 #define OMAP44XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
 347 #define OMAP44XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
 348 #define OMAP44XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
 349 #define OMAP44XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
 350 #define OMAP44XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
 351 #define OMAP44XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
 352 #define OMAP44XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
 353 #define OMAP44XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
 354 #define OMAP44XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
 355 #define OMAP44XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
 356 #define OMAP44XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
 357 #define OMAP44XX_DMA_MMC2_TX            47      /* S_DMA_46 */
 358 #define OMAP44XX_DMA_MMC2_RX            48      /* S_DMA_47 */
 359 #define OMAP44XX_DMA_UART1_TX           49      /* S_DMA_48 */
 360 #define OMAP44XX_DMA_UART1_RX           50      /* S_DMA_49 */
 361 #define OMAP44XX_DMA_UART2_TX           51      /* S_DMA_50 */
 362 #define OMAP44XX_DMA_UART2_RX           52      /* S_DMA_51 */
 363 #define OMAP44XX_DMA_UART3_TX           53      /* S_DMA_52 */
 364 #define OMAP44XX_DMA_UART3_RX           54      /* S_DMA_53 */
 365 #define OMAP44XX_DMA_UART4_TX           55      /* S_DMA_54 */
 366 #define OMAP44XX_DMA_UART4_RX           56      /* S_DMA_55 */
 367 #define OMAP44XX_DMA_MMC4_TX            57      /* S_DMA_56 */
 368 #define OMAP44XX_DMA_MMC4_RX            58      /* S_DMA_57 */
 369 #define OMAP44XX_DMA_MMC5_TX            59      /* S_DMA_58 */
 370 #define OMAP44XX_DMA_MMC5_RX            60      /* S_DMA_59 */
 371 #define OMAP44XX_DMA_MMC1_TX            61      /* S_DMA_60 */
 372 #define OMAP44XX_DMA_MMC1_RX            62      /* S_DMA_61 */
 373 #define OMAP44XX_DMA_SYS_REQ3           64      /* S_DMA_63 */
 374 #define OMAP44XX_DMA_MCPDM_UP           65      /* S_DMA_64 */
 375 #define OMAP44XX_DMA_MCPDM_DL           66      /* S_DMA_65 */
 376 #define OMAP44XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
 377 #define OMAP44XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
 378 #define OMAP44XX_DMA_DSS_DSI1_REQ0      72      /* S_DMA_71 */
 379 #define OMAP44XX_DMA_DSS_DSI1_REQ1      73      /* S_DMA_72 */
 380 #define OMAP44XX_DMA_DSS_DSI1_REQ2      74      /* S_DMA_73 */
 381 #define OMAP44XX_DMA_DSS_DSI1_REQ3      75      /* S_DMA_74 */
 382 #define OMAP44XX_DMA_DSS_HDMI_REQ       76      /* S_DMA_75 */
 383 #define OMAP44XX_DMA_MMC3_TX            77      /* S_DMA_76 */
 384 #define OMAP44XX_DMA_MMC3_RX            78      /* S_DMA_77 */
 385 #define OMAP44XX_DMA_USIM_TX            79      /* S_DMA_78 */
 386 #define OMAP44XX_DMA_USIM_RX            80      /* S_DMA_79 */
 387 #define OMAP44XX_DMA_DSS_DSI2_REQ0      81      /* S_DMA_80 */
 388 #define OMAP44XX_DMA_DSS_DSI2_REQ1      82      /* S_DMA_81 */
 389 #define OMAP44XX_DMA_DSS_DSI2_REQ2      83      /* S_DMA_82 */
 390 #define OMAP44XX_DMA_DSS_DSI2_REQ3      84      /* S_DMA_83 */
 391 #define OMAP44XX_DMA_ABE_REQ0           101     /* S_DMA_100 */
 392 #define OMAP44XX_DMA_ABE_REQ1           102     /* S_DMA_101 */
 393 #define OMAP44XX_DMA_ABE_REQ2           103     /* S_DMA_102 */
 394 #define OMAP44XX_DMA_ABE_REQ3           104     /* S_DMA_103 */
 395 #define OMAP44XX_DMA_ABE_REQ4           105     /* S_DMA_104 */
 396 #define OMAP44XX_DMA_ABE_REQ5           106     /* S_DMA_105 */
 397 #define OMAP44XX_DMA_ABE_REQ6           107     /* S_DMA_106 */
 398 #define OMAP44XX_DMA_ABE_REQ7           108     /* S_DMA_107 */
 399 #define OMAP44XX_DMA_I2C4_TX            124     /* S_DMA_123 */
 400 #define OMAP44XX_DMA_I2C4_RX            125     /* S_DMA_124 */
 401
 402 /*----------------------------------------------------------------------------*/
 403
 404 /* Hardware registers for LCD DMA */
 405 #define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
 406 #define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
 407 #define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
 408 #define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
 409 #define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
 410 #define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
 411
 412 #define OMAP1610_DMA_LCD_BASE           (0xfffee300)
 413 #define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
 414 #define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
 415 #define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
 416 #define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
 417 #define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
 418 #define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
 419 #define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
 420 #define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
 421 #define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
 422 #define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
 423 #define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
 424 #define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
 425 #define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
 426 #define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
 427 #define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
 428 #define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
 429 #define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
 430
 431 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 432 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 433 #define OMAP_DMA_HALF_IRQ               (1 << 2)
 434 #define OMAP_DMA_FRAME_IRQ              (1 << 3)
 435 #define OMAP_DMA_LAST_IRQ               (1 << 4)
 436 #define OMAP_DMA_BLOCK_IRQ              (1 << 5)
 437 #define OMAP1_DMA_SYNC_IRQ              (1 << 6)
 438 #define OMAP2_DMA_PKT_IRQ               (1 << 7)
 439 #define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
 440 #define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
 441 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
 442 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 443
 444 #define OMAP_DMA_DATA_TYPE_S8           0x00
 445 #define OMAP_DMA_DATA_TYPE_S16          0x01
 446 #define OMAP_DMA_DATA_TYPE_S32          0x02
 447
 448 #define OMAP_DMA_SYNC_ELEMENT           0x00
 449 #define OMAP_DMA_SYNC_FRAME             0x01
 450 #define OMAP_DMA_SYNC_BLOCK             0x02
 451 #define OMAP_DMA_SYNC_PACKET            0x03
 452
 453 #define OMAP_DMA_SRC_SYNC               0x01
 454 #define OMAP_DMA_DST_SYNC               0x00
 455
 456 #define OMAP_DMA_PORT_EMIFF             0x00
 457 #define OMAP_DMA_PORT_EMIFS             0x01
 458 #define OMAP_DMA_PORT_OCP_T1            0x02
 459 #define OMAP_DMA_PORT_TIPB              0x03
 460 #define OMAP_DMA_PORT_OCP_T2            0x04
 461 #define OMAP_DMA_PORT_MPUI              0x05
 462
 463 #define OMAP_DMA_AMODE_CONSTANT         0x00
 464 #define OMAP_DMA_AMODE_POST_INC         0x01
 465 #define OMAP_DMA_AMODE_SINGLE_IDX       0x02
 466 #define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
 467
 468 #define DMA_DEFAULT_FIFO_DEPTH          0x10
 469 #define DMA_DEFAULT_ARB_RATE            0x01
 470 /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
 471 #define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
 472 #define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
 473 #define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
 474 #define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
 475 #define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
 476 #define DMA_THREAD_FIFO_75              (0x01 << 14)
 477 #define DMA_THREAD_FIFO_25              (0x02 << 14)
 478 #define DMA_THREAD_FIFO_50              (0x03 << 14)
 479
 480 /* DMA4_OCP_SYSCONFIG bits */
 481 #define DMA_SYSCONFIG_MIDLEMODE_MASK            (3 << 12)
 482 #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK        (3 << 8)
 483 #define DMA_SYSCONFIG_EMUFREE                   (1 << 5)
 484 #define DMA_SYSCONFIG_SIDLEMODE_MASK            (3 << 3)
 485 #define DMA_SYSCONFIG_SOFTRESET                 (1 << 2)
 486 #define DMA_SYSCONFIG_AUTOIDLE                  (1 << 0)
 487
 488 #define DMA_SYSCONFIG_MIDLEMODE(n)              ((n) << 12)
 489 #define DMA_SYSCONFIG_SIDLEMODE(n)              ((n) << 3)
 490
 491 #define DMA_IDLEMODE_SMARTIDLE                  0x2
 492 #define DMA_IDLEMODE_NO_IDLE                    0x1
 493 #define DMA_IDLEMODE_FORCE_IDLE                 0x0
 494
 495 /* Chaining modes*/
 496 #ifndef CONFIG_ARCH_OMAP1
 497 #define OMAP_DMA_STATIC_CHAIN           0x1
 498 #define OMAP_DMA_DYNAMIC_CHAIN          0x2
 499 #define OMAP_DMA_CHAIN_ACTIVE           0x1
 500 #define OMAP_DMA_CHAIN_INACTIVE         0x0
 501 #endif
 502
 503 #define DMA_CH_PRIO_HIGH                0x1
 504 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
 505
 506 /* LCD DMA block numbers */
 507 enum {
 508         OMAP_LCD_DMA_B1_TOP,
 509         OMAP_LCD_DMA_B1_BOTTOM,
 510         OMAP_LCD_DMA_B2_TOP,
 511         OMAP_LCD_DMA_B2_BOTTOM
 512 };
 513
 514 enum omap_dma_burst_mode {
 515         OMAP_DMA_DATA_BURST_DIS = 0,
 516         OMAP_DMA_DATA_BURST_4,
 517         OMAP_DMA_DATA_BURST_8,
 518         OMAP_DMA_DATA_BURST_16,
 519 };
 520
 521 enum end_type {
 522         OMAP_DMA_LITTLE_ENDIAN = 0,
 523         OMAP_DMA_BIG_ENDIAN
 524 };
 525
 526 enum omap_dma_color_mode {
 527         OMAP_DMA_COLOR_DIS = 0,
 528         OMAP_DMA_CONSTANT_FILL,
 529         OMAP_DMA_TRANSPARENT_COPY
 530 };
 531
 532 enum omap_dma_write_mode {
 533         OMAP_DMA_WRITE_NON_POSTED = 0,
 534         OMAP_DMA_WRITE_POSTED,
 535         OMAP_DMA_WRITE_LAST_NON_POSTED
 536 };
 537
 538 enum omap_dma_channel_mode {
 539         OMAP_DMA_LCH_2D = 0,
 540         OMAP_DMA_LCH_G,
 541         OMAP_DMA_LCH_P,
 542         OMAP_DMA_LCH_PD
 543 };
 544
 545 struct omap_dma_channel_params {
 546         int data_type;          /* data type 8,16,32 */
 547         int elem_count;         /* number of elements in a frame */
 548         int frame_count;        /* number of frames in a element */
 549
 550         int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 551         int src_amode;          /* constant, post increment, indexed,
 552                                         double indexed */
 553         unsigned long src_start;        /* source address : physical */
 554         int src_ei;             /* source element index */
 555         int src_fi;             /* source frame index */
 556
 557         int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 558         int dst_amode;          /* constant, post increment, indexed,
 559                                         double indexed */
 560         unsigned long dst_start;        /* source address : physical */
 561         int dst_ei;             /* source element index */
 562         int dst_fi;             /* source frame index */
 563
 564         int trigger;            /* trigger attached if the channel is
 565                                         synchronized */
 566         int sync_mode;          /* sycn on element, frame , block or packet */
 567         int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
 568
 569         int ie;                 /* interrupt enabled */
 570
 571         unsigned char read_prio;/* read priority */
 572         unsigned char write_prio;/* write priority */
 573
 574 #ifndef CONFIG_ARCH_OMAP1
 575         enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
 576 #endif
 577 };
 578
 579
 580 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 581 extern int omap_request_dma(int dev_id, const char *dev_name,
 582                         void (*callback)(int lch, u16 ch_status, void *data),
 583                         void *data, int *dma_ch);
 584 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
 585 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
 586 extern void omap_free_dma(int ch);
 587 extern void omap_start_dma(int lch);
 588 extern void omap_stop_dma(int lch);
 589 extern void omap_set_dma_transfer_params(int lch, int data_type,
 590                                          int elem_count, int frame_count,
 591                                          int sync_mode,
 592                                          int dma_trigger, int src_or_dst_synch);
 593 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
 594                                     u32 color);
 595 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
 596 extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
 597
 598 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 599                                     unsigned long src_start,
 600                                     int src_ei, int src_fi);
 601 extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
 602 extern void omap_set_dma_src_data_pack(int lch, int enable);
 603 extern void omap_set_dma_src_burst_mode(int lch,
 604                                         enum omap_dma_burst_mode burst_mode);
 605
 606 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 607                                      unsigned long dest_start,
 608                                      int dst_ei, int dst_fi);
 609 extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
 610 extern void omap_set_dma_dest_data_pack(int lch, int enable);
 611 extern void omap_set_dma_dest_burst_mode(int lch,
 612                                          enum omap_dma_burst_mode burst_mode);
 613
 614 extern void omap_set_dma_params(int lch,
 615                                 struct omap_dma_channel_params *params);
 616
 617 extern void omap_dma_link_lch(int lch_head, int lch_queue);
 618 extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
 619
 620 extern int omap_set_dma_callback(int lch,
 621                         void (*callback)(int lch, u16 ch_status, void *data),
 622                         void *data);
 623 extern dma_addr_t omap_get_dma_src_pos(int lch);
 624 extern dma_addr_t omap_get_dma_dst_pos(int lch);
 625 extern void omap_clear_dma(int lch);
 626 extern int omap_get_dma_active_status(int lch);
 627 extern int omap_dma_running(void);
 628 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
 629                                        int tparams);
 630 extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 631                                  unsigned char write_prio);
 632 extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
 633 extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
 634 extern int omap_get_dma_index(int lch, int *ei, int *fi);
 635
 636 void omap_dma_global_context_save(void);
 637 void omap_dma_global_context_restore(void);
 638
 639 extern void omap_dma_disable_irq(int lch);
 640
 641 /* Chaining APIs */
 642 #ifndef CONFIG_ARCH_OMAP1
 643 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
 644                                   void (*callback) (int lch, u16 ch_status,
 645                                                     void *data),
 646                                   int *chain_id, int no_of_chans,
 647                                   int chain_mode,
 648                                   struct omap_dma_channel_params params);
 649 extern int omap_free_dma_chain(int chain_id);
 650 extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
 651                                      int dest_start, int elem_count,
 652                                      int frame_count, void *callbk_data);
 653 extern int omap_start_dma_chain_transfers(int chain_id);
 654 extern int omap_stop_dma_chain_transfers(int chain_id);
 655 extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
 656 extern int omap_get_dma_chain_dst_pos(int chain_id);
 657 extern int omap_get_dma_chain_src_pos(int chain_id);
 658
 659 extern int omap_modify_dma_chain_params(int chain_id,
 660                                         struct omap_dma_channel_params params);
 661 extern int omap_dma_chain_status(int chain_id);
 662 #endif
 663
 664 /* LCD DMA functions */
 665 extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
 666                                 void *data);
 667 extern void omap_free_lcd_dma(void);
 668 extern void omap_setup_lcd_dma(void);
 669 extern void omap_enable_lcd_dma(void);
 670 extern void omap_stop_lcd_dma(void);
 671 extern void omap_set_lcd_dma_ext_controller(int external);
 672 extern void omap_set_lcd_dma_single_transfer(int single);
 673 extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 674                                 int data_type);
 675 extern void omap_set_lcd_dma_b1_rotation(int rotate);
 676 extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
 677 extern void omap_set_lcd_dma_b1_mirror(int mirror);
 678 extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
 679
 680 #endif /* __ASM_ARCH_DMA_H */