arch/arm/plat-omap/include/plat/usb.h

   1 // include/asm-arm/mach-omap/usb.h
   2
   3 #ifndef __ASM_ARCH_OMAP_USB_H
   4 #define __ASM_ARCH_OMAP_USB_H
   5
   6 #include <plat/board.h>
   7
   8 #define OMAP3_HS_USB_PORTS      3
   9 enum ehci_hcd_omap_mode {
  10         EHCI_HCD_OMAP_MODE_UNKNOWN,
  11         EHCI_HCD_OMAP_MODE_PHY,
  12         EHCI_HCD_OMAP_MODE_TLL,
  13 };
  14
  15 struct ehci_hcd_omap_platform_data {
  16         enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
  17         unsigned                        phy_reset:1;
  18
  19         /* have to be valid if phy_reset is true and portx is in phy mode */
  20         int     reset_gpio_port[OMAP3_HS_USB_PORTS];
  21         /* flag for aux regulators */
  22         u8      aux[OMAP3_HS_USB_PORTS];
  23 };
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 #define OMAP1_OTG_BASE                  0xfffb0400
  28 #define OMAP1_UDC_BASE                  0xfffb4000
  29 #define OMAP1_OHCI_BASE                 0xfffba000
  30
  31 #define OMAP2_OHCI_BASE                 0x4805e000
  32 #define OMAP2_UDC_BASE                  0x4805e200
  33 #define OMAP2_OTG_BASE                  0x4805e300
  34
  35 #ifdef CONFIG_ARCH_OMAP1
  36
  37 #define OTG_BASE                        OMAP1_OTG_BASE
  38 #define UDC_BASE                        OMAP1_UDC_BASE
  39 #define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
  40
  41 #else
  42
  43 #define OTG_BASE                        OMAP2_OTG_BASE
  44 #define UDC_BASE                        OMAP2_UDC_BASE
  45 #define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
  46
  47 extern void usb_musb_init(void);
  48
  49 extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
  50
  51 #endif
  52
  53 void omap_usb_init(struct omap_usb_config *pdata);
  54
  55 /*-------------------------------------------------------------------------*/
  56
  57 /*
  58  * OTG and transceiver registers, for OMAPs starting with ARM926
  59  */
  60 #define OTG_REV                         (OTG_BASE + 0x00)
  61 #define OTG_SYSCON_1                    (OTG_BASE + 0x04)
  62 #       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
  63 #       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
  64 #       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
  65 #       define   OTG_IDLE_EN            (1 << 15)
  66 #       define   HST_IDLE_EN            (1 << 14)
  67 #       define   DEV_IDLE_EN            (1 << 13)
  68 #       define   OTG_RESET_DONE         (1 << 2)
  69 #       define   OTG_SOFT_RESET         (1 << 1)
  70 #define OTG_SYSCON_2                    (OTG_BASE + 0x08)
  71 #       define   OTG_EN                 (1 << 31)
  72 #       define   USBX_SYNCHRO           (1 << 30)
  73 #       define   OTG_MST16              (1 << 29)
  74 #       define   SRP_GPDATA             (1 << 28)
  75 #       define   SRP_GPDVBUS            (1 << 27)
  76 #       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
  77 #       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
  78 #       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
  79 #       define   SRP_DPW                (1 << 14)
  80 #       define   SRP_DATA               (1 << 13)
  81 #       define   SRP_VBUS               (1 << 12)
  82 #       define   OTG_PADEN              (1 << 10)
  83 #       define   HMC_PADEN              (1 << 9)
  84 #       define   UHOST_EN               (1 << 8)
  85 #       define   HMC_TLLSPEED           (1 << 7)
  86 #       define   HMC_TLLATTACH          (1 << 6)
  87 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
  88 #define OTG_CTRL                        (OTG_BASE + 0x0c)
  89 #       define   OTG_USB2_EN            (1 << 29)
  90 #       define   OTG_USB2_DP            (1 << 28)
  91 #       define   OTG_USB2_DM            (1 << 27)
  92 #       define   OTG_USB1_EN            (1 << 26)
  93 #       define   OTG_USB1_DP            (1 << 25)
  94 #       define   OTG_USB1_DM            (1 << 24)
  95 #       define   OTG_USB0_EN            (1 << 23)
  96 #       define   OTG_USB0_DP            (1 << 22)
  97 #       define   OTG_USB0_DM            (1 << 21)
  98 #       define   OTG_ASESSVLD           (1 << 20)
  99 #       define   OTG_BSESSEND           (1 << 19)
 100 #       define   OTG_BSESSVLD           (1 << 18)
 101 #       define   OTG_VBUSVLD            (1 << 17)
 102 #       define   OTG_ID                 (1 << 16)
 103 #       define   OTG_DRIVER_SEL         (1 << 15)
 104 #       define   OTG_A_SETB_HNPEN       (1 << 12)
 105 #       define   OTG_A_BUSREQ           (1 << 11)
 106 #       define   OTG_B_HNPEN            (1 << 9)
 107 #       define   OTG_B_BUSREQ           (1 << 8)
 108 #       define   OTG_BUSDROP            (1 << 7)
 109 #       define   OTG_PULLDOWN           (1 << 5)
 110 #       define   OTG_PULLUP             (1 << 4)
 111 #       define   OTG_DRV_VBUS           (1 << 3)
 112 #       define   OTG_PD_VBUS            (1 << 2)
 113 #       define   OTG_PU_VBUS            (1 << 1)
 114 #       define   OTG_PU_ID              (1 << 0)
 115 #define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
 116 #       define   DRIVER_SWITCH          (1 << 15)
 117 #       define   A_VBUS_ERR             (1 << 13)
 118 #       define   A_REQ_TMROUT           (1 << 12)
 119 #       define   A_SRP_DETECT           (1 << 11)
 120 #       define   B_HNP_FAIL             (1 << 10)
 121 #       define   B_SRP_TMROUT           (1 << 9)
 122 #       define   B_SRP_DONE             (1 << 8)
 123 #       define   B_SRP_STARTED          (1 << 7)
 124 #       define   OPRT_CHG               (1 << 0)
 125 #define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
 126         // same bits as in IRQ_EN
 127 #define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
 128 #       define   OTGVPD                 (1 << 14)
 129 #       define   OTGVPU                 (1 << 13)
 130 #       define   OTGPUID                (1 << 12)
 131 #       define   USB2VDR                (1 << 10)
 132 #       define   USB2PDEN               (1 << 9)
 133 #       define   USB2PUEN               (1 << 8)
 134 #       define   USB1VDR                (1 << 6)
 135 #       define   USB1PDEN               (1 << 5)
 136 #       define   USB1PUEN               (1 << 4)
 137 #       define   USB0VDR                (1 << 2)
 138 #       define   USB0PDEN               (1 << 1)
 139 #       define   USB0PUEN               (1 << 0)
 140 #define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
 141 #define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
 142
 143 /*-------------------------------------------------------------------------*/
 144
 145 /* OMAP1 */
 146 #define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
 147 #       define  CONF_USB2_UNI_R         (1 << 8)
 148 #       define  CONF_USB1_UNI_R         (1 << 7)
 149 #       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
 150 #       define  CONF_USB0_ISOLATE_R     (1 << 3)
 151 #       define  CONF_USB_PWRDN_DM_R     (1 << 2)
 152 #       define  CONF_USB_PWRDN_DP_R     (1 << 1)
 153
 154 /* OMAP2 */
 155 #       define  USB_UNIDIR                      0x0
 156 #       define  USB_UNIDIR_TLL                  0x1
 157 #       define  USB_BIDIR                       0x2
 158 #       define  USB_BIDIR_TLL                   0x3
 159 #       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
 160 #       define  USBT2TLL5PI             (1 << 17)
 161 #       define  USB0PUENACTLOI          (1 << 16)
 162 #       define  USBSTANDBYCTRL          (1 << 15)
 163 /* AM3517 */
 164 /* USB 2.0 OTG module registers */
 165 #define USB_REVISION_REG        0x00
 166 #define USB_CTRL_REG            0x04
 167 #define USB_STAT_REG            0x08
 168 #define USB_EMULATION_REG       0x0c
 169 /* 0x10 Reserved */
 170 #define USB_AUTOREQ_REG         0x14
 171 #define USB_SRP_FIX_TIME_REG    0x18
 172 #define USB_TEARDOWN_REG        0x1c
 173 #define EP_INTR_SRC_REG         0x20
 174 #define EP_INTR_SRC_SET_REG     0x24
 175 #define EP_INTR_SRC_CLEAR_REG   0x28
 176 #define EP_INTR_MASK_REG        0x2c
 177 #define EP_INTR_MASK_SET_REG    0x30
 178 #define EP_INTR_MASK_CLEAR_REG  0x34
 179 #define EP_INTR_SRC_MASKED_REG  0x38
 180 #define CORE_INTR_SRC_REG       0x40
 181 #define CORE_INTR_SRC_SET_REG   0x44
 182 #define CORE_INTR_SRC_CLEAR_REG 0x48
 183 #define CORE_INTR_MASK_REG      0x4c
 184 #define CORE_INTR_MASK_SET_REG  0x50
 185 #define CORE_INTR_MASK_CLEAR_REG 0x54
 186 #define CORE_INTR_SRC_MASKED_REG 0x58
 187 /* 0x5c Reserved */
 188 #define USB_END_OF_INTR_REG     0x60
 189 #define MOP_SOP_INTR_ENABLE     0x64
 190 /* 0x68-0x6c Reserved */
 191 #define USB_TX_MODE_REG         0x70    /* Transparent, CDC, [Generic] RNDIS */
 192 #define USB_RX_MODE_REG         0x74    /* Transparent, CDC, [Generic] RNDIS */
 193 #define EP_COUNT_MODE_REG       0x78
 194 #define USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x80 + (((n) - 1) << 2))
 195
 196 #define QUEUE_THRESHOLD_INTR_ENABLE_REG 0xc0
 197 #define QUEUE_63_THRESHOLD_REG  0xc4
 198 #define QUEUE_63_THRESHOLD_INTR_CLEAR_REG 0xc8
 199 #define QUEUE_65_THRESHOLD_REG  0xd4
 200 #define QUEUE_65_THRESHOLD_INTR_CLEAR_REG 0xd8
 201
 202 /* Control register bits */
 203 #define USB_SOFT_RESET_MASK     1
 204
 205 /* Mode register bits */
 206 #define USB_MODE_SHIFT(n)       ((((n) - 1) << 1))
 207 #define USB_MODE_MASK(n)        (3 << USB_MODE_SHIFT(n))
 208 #define USB_RX_MODE_SHIFT(n)    USB_MODE_SHIFT(n)
 209 #define USB_TX_MODE_SHIFT(n)    USB_MODE_SHIFT(n)
 210 #define USB_RX_MODE_MASK(n)     USB_MODE_MASK(n)
 211 #define USB_TX_MODE_MASK(n)     USB_MODE_MASK(n)
 212 #define USB_TRANSPARENT_MODE    0
 213 #define USB_RNDIS_MODE          1
 214 #define USB_CDC_MODE            2
 215 #define USB_GENERIC_RNDIS_MODE  3
 216
 217 /* AutoReq register bits */
 218 #define USB_RX_AUTOREQ_SHIFT(n) (((n) - 1) << 1)
 219 #define USB_RX_AUTOREQ_MASK(n)  (3 << USB_RX_AUTOREQ_SHIFT(n))
 220 #define USB_NO_AUTOREQ          0
 221 #define USB_AUTOREQ_ALL_BUT_EOP 1
 222 #define USB_AUTOREQ_ALWAYS      3
 223
 224 /* Teardown register bits */
 225 #define USB_TX_TDOWN_SHIFT(n)   (16 + (n))
 226 #define USB_TX_TDOWN_MASK(n)    (1 << USB_TX_TDOWN_SHIFT(n))
 227 #define USB_RX_TDOWN_SHIFT(n)   (n)
 228 #define USB_RX_TDOWN_MASK(n)    (1 << USB_RX_TDOWN_SHIFT(n))
 229
 230 /* USB interrupt register bits */
 231 #define USB_INTR_USB_SHIFT      16
 232 #define USB_INTR_USB_MASK       (0x1ff << USB_INTR_USB_SHIFT) /* 8 Mentor */
 233                                         /* interrupts and DRVVBUS interrupt */
 234 #define USB_INTR_DRVVBUS        0x100
 235 #define USB_INTR_RX_SHIFT       16
 236 #define USB_INTR_TX_SHIFT       0
 237
 238 #define USB_MENTOR_CORE_OFFSET  0x400
 239
 240 #define USB_CPPI41_NUM_CH       15
 241
 242 #endif  /* __ASM_ARCH_OMAP_USB_H */