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First Support on Ginger and OMAP TI
[linux-ginger.git] / arch / blackfin / mach-common / ints-priority.c
blob660ea1bec54ca28041e6eaa69ba3a23f4d99f290
1 /*
2 * Set up the interrupt priorities
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
10 *
11 * Licensed under the GPL-2
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #ifdef CONFIG_IPIPE
19 #include <linux/ipipe.h>
20 #endif
21 #ifdef CONFIG_KGDB
22 #include <linux/kgdb.h>
23 #endif
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
26 #include <asm/gpio.h>
27 #include <asm/irq_handler.h>
28
29 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
30
31 #ifdef BF537_FAMILY
32 # define BF537_GENERIC_ERROR_INT_DEMUX
33 #else
34 # undef BF537_GENERIC_ERROR_INT_DEMUX
35 #endif
36
37 /*
38 * NOTES:
39 * - we have separated the physical Hardware interrupt from the
40 * levels that the LINUX kernel sees (see the description in irq.h)
41 * -
42 */
43
44 #ifndef CONFIG_SMP
45 /* Initialize this to an actual value to force it into the .data
46 * section so that we know it is properly initialized at entry into
47 * the kernel but before bss is initialized to zero (which is where
48 * it would live otherwise). The 0x1f magic represents the IRQs we
49 * cannot actually mask out in hardware.
50 */
51 unsigned long bfin_irq_flags = 0x1f;
52 EXPORT_SYMBOL(bfin_irq_flags);
53 #endif
54
55 /* The number of spurious interrupts */
56 atomic_t num_spurious;
57
58 #ifdef CONFIG_PM
59 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
60 unsigned vr_wakeup;
61 #endif
62
63 struct ivgx {
64 /* irq number for request_irq, available in mach-bf5xx/irq.h */
65 unsigned int irqno;
66 /* corresponding bit in the SIC_ISR register */
67 unsigned int isrflag;
68 } ivg_table[NR_PERI_INTS];
69
70 struct ivg_slice {
71 /* position of first irq in ivg_table for given ivg */
72 struct ivgx *ifirst;
73 struct ivgx *istop;
74 } ivg7_13[IVG13 - IVG7 + 1];
75
76
77 /*
78 * Search SIC_IAR and fill tables with the irqvalues
79 * and their positions in the SIC_ISR register.
80 */
81 static void __init search_IAR(void)
82 {
83 unsigned ivg, irq_pos = 0;
84 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
85 int irqn;
86
87 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
88
89 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
90 int iar_shift = (irqn & 7) * 4;
91 if (ivg == (0xf &
92 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
93 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
94 bfin_read32((unsigned long *)SIC_IAR0 +
95 ((irqn % 32) >> 3) + ((irqn / 32) *
96 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
97 #else
98 bfin_read32((unsigned long *)SIC_IAR0 +
99 (irqn >> 3)) >> iar_shift)) {
100 #endif
101 ivg_table[irq_pos].irqno = IVG7 + irqn;
102 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
103 ivg7_13[ivg].istop++;
104 irq_pos++;
105 }
106 }
107 }
108 }
109
110 /*
111 * This is for core internal IRQs
112 */
113
114 static void bfin_ack_noop(unsigned int irq)
115 {
116 /* Dummy function. */
117 }
118
119 static void bfin_core_mask_irq(unsigned int irq)
120 {
121 bfin_irq_flags &= ~(1 << irq);
122 if (!irqs_disabled_hw())
123 local_irq_enable_hw();
124 }
125
126 static void bfin_core_unmask_irq(unsigned int irq)
127 {
128 bfin_irq_flags |= 1 << irq;
129 /*
130 * If interrupts are enabled, IMASK must contain the same value
131 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
132 * are currently disabled we need not do anything; one of the
133 * callers will take care of setting IMASK to the proper value
134 * when reenabling interrupts.
135 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
136 * what we need.
137 */
138 if (!irqs_disabled_hw())
139 local_irq_enable_hw();
140 return;
141 }
142
143 static void bfin_internal_mask_irq(unsigned int irq)
144 {
145 unsigned long flags;
146
147 #ifdef CONFIG_BF53x
148 local_irq_save_hw(flags);
149 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
150 ~(1 << SIC_SYSIRQ(irq)));
151 #else
152 unsigned mask_bank, mask_bit;
153 local_irq_save_hw(flags);
154 mask_bank = SIC_SYSIRQ(irq) / 32;
155 mask_bit = SIC_SYSIRQ(irq) % 32;
156 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
157 ~(1 << mask_bit));
158 #ifdef CONFIG_SMP
159 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
160 ~(1 << mask_bit));
161 #endif
162 #endif
163 local_irq_restore_hw(flags);
164 }
165
166 static void bfin_internal_unmask_irq(unsigned int irq)
167 {
168 unsigned long flags;
169
170 #ifdef CONFIG_BF53x
171 local_irq_save_hw(flags);
172 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
173 (1 << SIC_SYSIRQ(irq)));
174 #else
175 unsigned mask_bank, mask_bit;
176 local_irq_save_hw(flags);
177 mask_bank = SIC_SYSIRQ(irq) / 32;
178 mask_bit = SIC_SYSIRQ(irq) % 32;
179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit));
181 #ifdef CONFIG_SMP
182 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
183 (1 << mask_bit));
184 #endif
185 #endif
186 local_irq_restore_hw(flags);
187 }
188
189 #ifdef CONFIG_PM
190 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
191 {
192 u32 bank, bit, wakeup = 0;
193 unsigned long flags;
194 bank = SIC_SYSIRQ(irq) / 32;
195 bit = SIC_SYSIRQ(irq) % 32;
196
197 switch (irq) {
198 #ifdef IRQ_RTC
199 case IRQ_RTC:
200 wakeup |= WAKE;
201 break;
202 #endif
203 #ifdef IRQ_CAN0_RX
204 case IRQ_CAN0_RX:
205 wakeup |= CANWE;
206 break;
207 #endif
208 #ifdef IRQ_CAN1_RX
209 case IRQ_CAN1_RX:
210 wakeup |= CANWE;
211 break;
212 #endif
213 #ifdef IRQ_USB_INT0
214 case IRQ_USB_INT0:
215 wakeup |= USBWE;
216 break;
217 #endif
218 #ifdef IRQ_KEY
219 case IRQ_KEY:
220 wakeup |= KPADWE;
221 break;
222 #endif
223 #ifdef CONFIG_BF54x
224 case IRQ_CNT:
225 wakeup |= ROTWE;
226 break;
227 #endif
228 default:
229 break;
230 }
231
232 local_irq_save_hw(flags);
233
234 if (state) {
235 bfin_sic_iwr[bank] |= (1 << bit);
236 vr_wakeup |= wakeup;
237
238 } else {
239 bfin_sic_iwr[bank] &= ~(1 << bit);
240 vr_wakeup &= ~wakeup;
241 }
242
243 local_irq_restore_hw(flags);
244
245 return 0;
246 }
247 #endif
248
249 static struct irq_chip bfin_core_irqchip = {
250 .name = "CORE",
251 .ack = bfin_ack_noop,
252 .mask = bfin_core_mask_irq,
253 .unmask = bfin_core_unmask_irq,
254 };
255
256 static struct irq_chip bfin_internal_irqchip = {
257 .name = "INTN",
258 .ack = bfin_ack_noop,
259 .mask = bfin_internal_mask_irq,
260 .unmask = bfin_internal_unmask_irq,
261 .mask_ack = bfin_internal_mask_irq,
262 .disable = bfin_internal_mask_irq,
263 .enable = bfin_internal_unmask_irq,
264 #ifdef CONFIG_PM
265 .set_wake = bfin_internal_set_wake,
266 #endif
267 };
268
269 static void bfin_handle_irq(unsigned irq)
270 {
271 #ifdef CONFIG_IPIPE
272 struct pt_regs regs; /* Contents not used. */
273 ipipe_trace_irq_entry(irq);
274 __ipipe_handle_irq(irq, &regs);
275 ipipe_trace_irq_exit(irq);
276 #else /* !CONFIG_IPIPE */
277 struct irq_desc *desc = irq_desc + irq;
278 desc->handle_irq(irq, desc);
279 #endif /* !CONFIG_IPIPE */
280 }
281
282 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
283 static int error_int_mask;
284
285 static void bfin_generic_error_mask_irq(unsigned int irq)
286 {
287 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
288
289 if (!error_int_mask)
290 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
291 }
292
293 static void bfin_generic_error_unmask_irq(unsigned int irq)
294 {
295 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
296 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
297 }
298
299 static struct irq_chip bfin_generic_error_irqchip = {
300 .name = "ERROR",
301 .ack = bfin_ack_noop,
302 .mask_ack = bfin_generic_error_mask_irq,
303 .mask = bfin_generic_error_mask_irq,
304 .unmask = bfin_generic_error_unmask_irq,
305 };
306
307 static void bfin_demux_error_irq(unsigned int int_err_irq,
308 struct irq_desc *inta_desc)
309 {
310 int irq = 0;
311
312 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
313 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
314 irq = IRQ_MAC_ERROR;
315 else
316 #endif
317 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
318 irq = IRQ_SPORT0_ERROR;
319 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
320 irq = IRQ_SPORT1_ERROR;
321 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
322 irq = IRQ_PPI_ERROR;
323 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
324 irq = IRQ_CAN_ERROR;
325 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
326 irq = IRQ_SPI_ERROR;
327 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
328 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
329 irq = IRQ_UART0_ERROR;
330 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
331 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
332 irq = IRQ_UART1_ERROR;
333
334 if (irq) {
335 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
336 bfin_handle_irq(irq);
337 else {
338
339 switch (irq) {
340 case IRQ_PPI_ERROR:
341 bfin_write_PPI_STATUS(PPI_ERR_MASK);
342 break;
343 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
344 case IRQ_MAC_ERROR:
345 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
346 break;
347 #endif
348 case IRQ_SPORT0_ERROR:
349 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
350 break;
351
352 case IRQ_SPORT1_ERROR:
353 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
354 break;
355
356 case IRQ_CAN_ERROR:
357 bfin_write_CAN_GIS(CAN_ERR_MASK);
358 break;
359
360 case IRQ_SPI_ERROR:
361 bfin_write_SPI_STAT(SPI_ERR_MASK);
362 break;
363
364 default:
365 break;
366 }
367
368 pr_debug("IRQ %d:"
369 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
370 irq);
371 }
372 } else
373 printk(KERN_ERR
374 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
375 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
376 __func__, __FILE__, __LINE__);
377
378 }
379 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
380
381 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
382 {
383 #ifdef CONFIG_IPIPE
384 _set_irq_handler(irq, handle_level_irq);
385 #else
386 struct irq_desc *desc = irq_desc + irq;
387 /* May not call generic set_irq_handler() due to spinlock
388 recursion. */
389 desc->handle_irq = handle;
390 #endif
391 }
392
393 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
394 extern void bfin_gpio_irq_prepare(unsigned gpio);
395
396 #if !defined(CONFIG_BF54x)
397
398 static void bfin_gpio_ack_irq(unsigned int irq)
399 {
400 /* AFAIK ack_irq in case mask_ack is provided
401 * get's only called for edge sense irqs
402 */
403 set_gpio_data(irq_to_gpio(irq), 0);
404 }
405
406 static void bfin_gpio_mask_ack_irq(unsigned int irq)
407 {
408 struct irq_desc *desc = irq_desc + irq;
409 u32 gpionr = irq_to_gpio(irq);
410
411 if (desc->handle_irq == handle_edge_irq)
412 set_gpio_data(gpionr, 0);
413
414 set_gpio_maska(gpionr, 0);
415 }
416
417 static void bfin_gpio_mask_irq(unsigned int irq)
418 {
419 set_gpio_maska(irq_to_gpio(irq), 0);
420 }
421
422 static void bfin_gpio_unmask_irq(unsigned int irq)
423 {
424 set_gpio_maska(irq_to_gpio(irq), 1);
425 }
426
427 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
428 {
429 u32 gpionr = irq_to_gpio(irq);
430
431 if (__test_and_set_bit(gpionr, gpio_enabled))
432 bfin_gpio_irq_prepare(gpionr);
433
434 bfin_gpio_unmask_irq(irq);
435
436 return 0;
437 }
438
439 static void bfin_gpio_irq_shutdown(unsigned int irq)
440 {
441 u32 gpionr = irq_to_gpio(irq);
442
443 bfin_gpio_mask_irq(irq);
444 __clear_bit(gpionr, gpio_enabled);
445 bfin_gpio_irq_free(gpionr);
446 }
447
448 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
449 {
450 int ret;
451 char buf[16];
452 u32 gpionr = irq_to_gpio(irq);
453
454 if (type == IRQ_TYPE_PROBE) {
455 /* only probe unenabled GPIO interrupt lines */
456 if (test_bit(gpionr, gpio_enabled))
457 return 0;
458 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
459 }
460
461 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
462 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
463
464 snprintf(buf, 16, "gpio-irq%d", irq);
465 ret = bfin_gpio_irq_request(gpionr, buf);
466 if (ret)
467 return ret;
468
469 if (__test_and_set_bit(gpionr, gpio_enabled))
470 bfin_gpio_irq_prepare(gpionr);
471
472 } else {
473 __clear_bit(gpionr, gpio_enabled);
474 return 0;
475 }
476
477 set_gpio_inen(gpionr, 0);
478 set_gpio_dir(gpionr, 0);
479
480 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
481 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
482 set_gpio_both(gpionr, 1);
483 else
484 set_gpio_both(gpionr, 0);
485
486 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
487 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
488 else
489 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
490
491 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
492 set_gpio_edge(gpionr, 1);
493 set_gpio_inen(gpionr, 1);
494 set_gpio_data(gpionr, 0);
495
496 } else {
497 set_gpio_edge(gpionr, 0);
498 set_gpio_inen(gpionr, 1);
499 }
500
501 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
502 bfin_set_irq_handler(irq, handle_edge_irq);
503 else
504 bfin_set_irq_handler(irq, handle_level_irq);
505
506 return 0;
507 }
508
509 #ifdef CONFIG_PM
510 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
511 {
512 unsigned gpio = irq_to_gpio(irq);
513
514 if (state)
515 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
516 else
517 gpio_pm_wakeup_free(gpio);
518
519 return 0;
520 }
521 #endif
522
523 static void bfin_demux_gpio_irq(unsigned int inta_irq,
524 struct irq_desc *desc)
525 {
526 unsigned int i, gpio, mask, irq, search = 0;
527
528 switch (inta_irq) {
529 #if defined(CONFIG_BF53x)
530 case IRQ_PROG_INTA:
531 irq = IRQ_PF0;
532 search = 1;
533 break;
534 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
535 case IRQ_MAC_RX:
536 irq = IRQ_PH0;
537 break;
538 # endif
539 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
540 case IRQ_PORTF_INTA:
541 irq = IRQ_PF0;
542 break;
543 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
544 case IRQ_PORTF_INTA:
545 irq = IRQ_PF0;
546 break;
547 case IRQ_PORTG_INTA:
548 irq = IRQ_PG0;
549 break;
550 case IRQ_PORTH_INTA:
551 irq = IRQ_PH0;
552 break;
553 #elif defined(CONFIG_BF561)
554 case IRQ_PROG0_INTA:
555 irq = IRQ_PF0;
556 break;
557 case IRQ_PROG1_INTA:
558 irq = IRQ_PF16;
559 break;
560 case IRQ_PROG2_INTA:
561 irq = IRQ_PF32;
562 break;
563 #endif
564 default:
565 BUG();
566 return;
567 }
568
569 if (search) {
570 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
571 irq += i;
572
573 mask = get_gpiop_data(i) & get_gpiop_maska(i);
574
575 while (mask) {
576 if (mask & 1)
577 bfin_handle_irq(irq);
578 irq++;
579 mask >>= 1;
580 }
581 }
582 } else {
583 gpio = irq_to_gpio(irq);
584 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
585
586 do {
587 if (mask & 1)
588 bfin_handle_irq(irq);
589 irq++;
590 mask >>= 1;
591 } while (mask);
592 }
593
594 }
595
596 #else /* CONFIG_BF54x */
597
598 #define NR_PINT_SYS_IRQS 4
599 #define NR_PINT_BITS 32
600 #define NR_PINTS 160
601 #define IRQ_NOT_AVAIL 0xFF
602
603 #define PINT_2_BANK(x) ((x) >> 5)
604 #define PINT_2_BIT(x) ((x) & 0x1F)
605 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
606
607 static unsigned char irq2pint_lut[NR_PINTS];
608 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
609
610 struct pin_int_t {
611 unsigned int mask_set;
612 unsigned int mask_clear;
613 unsigned int request;
614 unsigned int assign;
615 unsigned int edge_set;
616 unsigned int edge_clear;
617 unsigned int invert_set;
618 unsigned int invert_clear;
619 unsigned int pinstate;
620 unsigned int latch;
621 };
622
623 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
624 (struct pin_int_t *)PINT0_MASK_SET,
625 (struct pin_int_t *)PINT1_MASK_SET,
626 (struct pin_int_t *)PINT2_MASK_SET,
627 (struct pin_int_t *)PINT3_MASK_SET,
628 };
629
630 inline unsigned int get_irq_base(u32 bank, u8 bmap)
631 {
632 unsigned int irq_base;
633
634 if (bank < 2) { /*PA-PB */
635 irq_base = IRQ_PA0 + bmap * 16;
636 } else { /*PC-PJ */
637 irq_base = IRQ_PC0 + bmap * 16;
638 }
639
640 return irq_base;
641 }
642
643 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
644 void init_pint_lut(void)
645 {
646 u16 bank, bit, irq_base, bit_pos;
647 u32 pint_assign;
648 u8 bmap;
649
650 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
651
652 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
653
654 pint_assign = pint[bank]->assign;
655
656 for (bit = 0; bit < NR_PINT_BITS; bit++) {
657
658 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
659
660 irq_base = get_irq_base(bank, bmap);
661
662 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
663 bit_pos = bit + bank * NR_PINT_BITS;
664
665 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
666 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
667 }
668 }
669 }
670
671 static void bfin_gpio_ack_irq(unsigned int irq)
672 {
673 struct irq_desc *desc = irq_desc + irq;
674 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
675 u32 pintbit = PINT_BIT(pint_val);
676 u32 bank = PINT_2_BANK(pint_val);
677
678 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
679 if (pint[bank]->invert_set & pintbit)
680 pint[bank]->invert_clear = pintbit;
681 else
682 pint[bank]->invert_set = pintbit;
683 }
684 pint[bank]->request = pintbit;
685
686 }
687
688 static void bfin_gpio_mask_ack_irq(unsigned int irq)
689 {
690 struct irq_desc *desc = irq_desc + irq;
691 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
692 u32 pintbit = PINT_BIT(pint_val);
693 u32 bank = PINT_2_BANK(pint_val);
694
695 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
696 if (pint[bank]->invert_set & pintbit)
697 pint[bank]->invert_clear = pintbit;
698 else
699 pint[bank]->invert_set = pintbit;
700 }
701
702 pint[bank]->request = pintbit;
703 pint[bank]->mask_clear = pintbit;
704 }
705
706 static void bfin_gpio_mask_irq(unsigned int irq)
707 {
708 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
709
710 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
711 }
712
713 static void bfin_gpio_unmask_irq(unsigned int irq)
714 {
715 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
716 u32 pintbit = PINT_BIT(pint_val);
717 u32 bank = PINT_2_BANK(pint_val);
718
719 pint[bank]->request = pintbit;
720 pint[bank]->mask_set = pintbit;
721 }
722
723 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
724 {
725 u32 gpionr = irq_to_gpio(irq);
726 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
727
728 if (pint_val == IRQ_NOT_AVAIL) {
729 printk(KERN_ERR
730 "GPIO IRQ %d :Not in PINT Assign table "
731 "Reconfigure Interrupt to Port Assignemt\n", irq);
732 return -ENODEV;
733 }
734
735 if (__test_and_set_bit(gpionr, gpio_enabled))
736 bfin_gpio_irq_prepare(gpionr);
737
738 bfin_gpio_unmask_irq(irq);
739
740 return 0;
741 }
742
743 static void bfin_gpio_irq_shutdown(unsigned int irq)
744 {
745 u32 gpionr = irq_to_gpio(irq);
746
747 bfin_gpio_mask_irq(irq);
748 __clear_bit(gpionr, gpio_enabled);
749 bfin_gpio_irq_free(gpionr);
750 }
751
752 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
753 {
754 int ret;
755 char buf[16];
756 u32 gpionr = irq_to_gpio(irq);
757 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
758 u32 pintbit = PINT_BIT(pint_val);
759 u32 bank = PINT_2_BANK(pint_val);
760
761 if (pint_val == IRQ_NOT_AVAIL)
762 return -ENODEV;
763
764 if (type == IRQ_TYPE_PROBE) {
765 /* only probe unenabled GPIO interrupt lines */
766 if (test_bit(gpionr, gpio_enabled))
767 return 0;
768 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
769 }
770
771 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
772 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
773
774 snprintf(buf, 16, "gpio-irq%d", irq);
775 ret = bfin_gpio_irq_request(gpionr, buf);
776 if (ret)
777 return ret;
778
779 if (__test_and_set_bit(gpionr, gpio_enabled))
780 bfin_gpio_irq_prepare(gpionr);
781
782 } else {
783 __clear_bit(gpionr, gpio_enabled);
784 return 0;
785 }
786
787 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
788 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
789 else
790 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
791
792 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
793 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
794 if (gpio_get_value(gpionr))
795 pint[bank]->invert_set = pintbit;
796 else
797 pint[bank]->invert_clear = pintbit;
798 }
799
800 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
801 pint[bank]->edge_set = pintbit;
802 bfin_set_irq_handler(irq, handle_edge_irq);
803 } else {
804 pint[bank]->edge_clear = pintbit;
805 bfin_set_irq_handler(irq, handle_level_irq);
806 }
807
808 return 0;
809 }
810
811 #ifdef CONFIG_PM
812 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
813 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
814
815 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
816 {
817 u32 pint_irq;
818 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
819 u32 bank = PINT_2_BANK(pint_val);
820 u32 pintbit = PINT_BIT(pint_val);
821
822 switch (bank) {
823 case 0:
824 pint_irq = IRQ_PINT0;
825 break;
826 case 2:
827 pint_irq = IRQ_PINT2;
828 break;
829 case 3:
830 pint_irq = IRQ_PINT3;
831 break;
832 case 1:
833 pint_irq = IRQ_PINT1;
834 break;
835 default:
836 return -EINVAL;
837 }
838
839 bfin_internal_set_wake(pint_irq, state);
840
841 if (state)
842 pint_wakeup_masks[bank] |= pintbit;
843 else
844 pint_wakeup_masks[bank] &= ~pintbit;
845
846 return 0;
847 }
848
849 u32 bfin_pm_setup(void)
850 {
851 u32 val, i;
852
853 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
854 val = pint[i]->mask_clear;
855 pint_saved_masks[i] = val;
856 if (val ^ pint_wakeup_masks[i]) {
857 pint[i]->mask_clear = val;
858 pint[i]->mask_set = pint_wakeup_masks[i];
859 }
860 }
861
862 return 0;
863 }
864
865 void bfin_pm_restore(void)
866 {
867 u32 i, val;
868
869 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
870 val = pint_saved_masks[i];
871 if (val ^ pint_wakeup_masks[i]) {
872 pint[i]->mask_clear = pint[i]->mask_clear;
873 pint[i]->mask_set = val;
874 }
875 }
876 }
877 #endif
878
879 static void bfin_demux_gpio_irq(unsigned int inta_irq,
880 struct irq_desc *desc)
881 {
882 u32 bank, pint_val;
883 u32 request, irq;
884
885 switch (inta_irq) {
886 case IRQ_PINT0:
887 bank = 0;
888 break;
889 case IRQ_PINT2:
890 bank = 2;
891 break;
892 case IRQ_PINT3:
893 bank = 3;
894 break;
895 case IRQ_PINT1:
896 bank = 1;
897 break;
898 default:
899 return;
900 }
901
902 pint_val = bank * NR_PINT_BITS;
903
904 request = pint[bank]->request;
905
906 while (request) {
907 if (request & 1) {
908 irq = pint2irq_lut[pint_val] + SYS_IRQS;
909 bfin_handle_irq(irq);
910 }
911 pint_val++;
912 request >>= 1;
913 }
914
915 }
916 #endif
917
918 static struct irq_chip bfin_gpio_irqchip = {
919 .name = "GPIO",
920 .ack = bfin_gpio_ack_irq,
921 .mask = bfin_gpio_mask_irq,
922 .mask_ack = bfin_gpio_mask_ack_irq,
923 .unmask = bfin_gpio_unmask_irq,
924 .disable = bfin_gpio_mask_irq,
925 .enable = bfin_gpio_unmask_irq,
926 .set_type = bfin_gpio_irq_type,
927 .startup = bfin_gpio_irq_startup,
928 .shutdown = bfin_gpio_irq_shutdown,
929 #ifdef CONFIG_PM
930 .set_wake = bfin_gpio_set_wake,
931 #endif
932 };
933
934 void __cpuinit init_exception_vectors(void)
935 {
936 /* cannot program in software:
937 * evt0 - emulation (jtag)
938 * evt1 - reset
939 */
940 bfin_write_EVT2(evt_nmi);
941 bfin_write_EVT3(trap);
942 bfin_write_EVT5(evt_ivhw);
943 bfin_write_EVT6(evt_timer);
944 bfin_write_EVT7(evt_evt7);
945 bfin_write_EVT8(evt_evt8);
946 bfin_write_EVT9(evt_evt9);
947 bfin_write_EVT10(evt_evt10);
948 bfin_write_EVT11(evt_evt11);
949 bfin_write_EVT12(evt_evt12);
950 bfin_write_EVT13(evt_evt13);
951 bfin_write_EVT14(evt_evt14);
952 bfin_write_EVT15(evt_system_call);
953 CSYNC();
954 }
955
956 /*
957 * This function should be called during kernel startup to initialize
958 * the BFin IRQ handling routines.
959 */
960
961 int __init init_arch_irq(void)
962 {
963 int irq;
964 unsigned long ilat = 0;
965 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
966 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
967 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
968 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
969 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
970 # ifdef CONFIG_BF54x
971 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
972 # endif
973 # ifdef CONFIG_SMP
974 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
975 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
976 # endif
977 #else
978 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
979 #endif
980
981 local_irq_disable();
982
983 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
984 /* Clear EMAC Interrupt Status bits so we can demux it later */
985 bfin_write_EMAC_SYSTAT(-1);
986 #endif
987
988 #ifdef CONFIG_BF54x
989 # ifdef CONFIG_PINTx_REASSIGN
990 pint[0]->assign = CONFIG_PINT0_ASSIGN;
991 pint[1]->assign = CONFIG_PINT1_ASSIGN;
992 pint[2]->assign = CONFIG_PINT2_ASSIGN;
993 pint[3]->assign = CONFIG_PINT3_ASSIGN;
994 # endif
995 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
996 init_pint_lut();
997 #endif
998
999 for (irq = 0; irq <= SYS_IRQS; irq++) {
1000 if (irq <= IRQ_CORETMR)
1001 set_irq_chip(irq, &bfin_core_irqchip);
1002 else
1003 set_irq_chip(irq, &bfin_internal_irqchip);
1004
1005 switch (irq) {
1006 #if defined(CONFIG_BF53x)
1007 case IRQ_PROG_INTA:
1008 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1009 case IRQ_MAC_RX:
1010 # endif
1011 #elif defined(CONFIG_BF54x)
1012 case IRQ_PINT0:
1013 case IRQ_PINT1:
1014 case IRQ_PINT2:
1015 case IRQ_PINT3:
1016 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1017 case IRQ_PORTF_INTA:
1018 case IRQ_PORTG_INTA:
1019 case IRQ_PORTH_INTA:
1020 #elif defined(CONFIG_BF561)
1021 case IRQ_PROG0_INTA:
1022 case IRQ_PROG1_INTA:
1023 case IRQ_PROG2_INTA:
1024 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1025 case IRQ_PORTF_INTA:
1026 #endif
1027
1028 set_irq_chained_handler(irq,
1029 bfin_demux_gpio_irq);
1030 break;
1031 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1032 case IRQ_GENERIC_ERROR:
1033 set_irq_chained_handler(irq, bfin_demux_error_irq);
1034 break;
1035 #endif
1036
1037 #ifdef CONFIG_SMP
1038 #ifdef CONFIG_TICKSOURCE_GPTMR0
1039 case IRQ_TIMER0:
1040 #endif
1041 #ifdef CONFIG_TICKSOURCE_CORETMR
1042 case IRQ_CORETMR:
1043 #endif
1044 case IRQ_SUPPLE_0:
1045 case IRQ_SUPPLE_1:
1046 set_irq_handler(irq, handle_percpu_irq);
1047 break;
1048 #endif
1049
1050 #ifdef CONFIG_IPIPE
1051 #ifndef CONFIG_TICKSOURCE_CORETMR
1052 case IRQ_TIMER0:
1053 set_irq_handler(irq, handle_simple_irq);
1054 break;
1055 #endif
1056 case IRQ_CORETMR:
1057 set_irq_handler(irq, handle_simple_irq);
1058 break;
1059 default:
1060 set_irq_handler(irq, handle_level_irq);
1061 break;
1062 #else /* !CONFIG_IPIPE */
1063 default:
1064 set_irq_handler(irq, handle_simple_irq);
1065 break;
1066 #endif /* !CONFIG_IPIPE */
1067 }
1068 }
1069
1070 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1071 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1072 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1073 handle_level_irq);
1074 #endif
1075
1076 /* if configured as edge, then will be changed to do_edge_IRQ */
1077 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1078 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1079 handle_level_irq);
1080
1081
1082 bfin_write_IMASK(0);
1083 CSYNC();
1084 ilat = bfin_read_ILAT();
1085 CSYNC();
1086 bfin_write_ILAT(ilat);
1087 CSYNC();
1088
1089 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1090 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1091 * local_irq_enable()
1092 */
1093 program_IAR();
1094 /* Therefore it's better to setup IARs before interrupts enabled */
1095 search_IAR();
1096
1097 /* Enable interrupts IVG7-15 */
1098 bfin_irq_flags |= IMASK_IVG15 |
1099 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1100 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1101
1102 /* This implicitly covers ANOMALY_05000171
1103 * Boot-ROM code modifies SICA_IWRx wakeup registers
1104 */
1105 #ifdef SIC_IWR0
1106 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1107 # ifdef SIC_IWR1
1108 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1109 * will screw up the bootrom as it relies on MDMA0/1 waking it
1110 * up from IDLE instructions. See this report for more info:
1111 * http://blackfin.uclinux.org/gf/tracker/4323
1112 */
1113 if (ANOMALY_05000435)
1114 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1115 else
1116 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1117 # endif
1118 # ifdef SIC_IWR2
1119 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1120 # endif
1121 #else
1122 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1123 #endif
1124
1125 return 0;
1126 }
1127
1128 #ifdef CONFIG_DO_IRQ_L1
1129 __attribute__((l1_text))
1130 #endif
1131 void do_irq(int vec, struct pt_regs *fp)
1132 {
1133 if (vec == EVT_IVTMR_P) {
1134 vec = IRQ_CORETMR;
1135 } else {
1136 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1137 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1138 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1139 unsigned long sic_status[3];
1140
1141 if (smp_processor_id()) {
1142 # ifdef SICB_ISR0
1143 /* This will be optimized out in UP mode. */
1144 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1145 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1146 # endif
1147 } else {
1148 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1149 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1150 }
1151 # ifdef SIC_ISR2
1152 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1153 # endif
1154 for (;; ivg++) {
1155 if (ivg >= ivg_stop) {
1156 atomic_inc(&num_spurious);
1157 return;
1158 }
1159 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1160 break;
1161 }
1162 #else
1163 unsigned long sic_status;
1164
1165 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1166
1167 for (;; ivg++) {
1168 if (ivg >= ivg_stop) {
1169 atomic_inc(&num_spurious);
1170 return;
1171 } else if (sic_status & ivg->isrflag)
1172 break;
1173 }
1174 #endif
1175 vec = ivg->irqno;
1176 }
1177 asm_do_IRQ(vec, fp);
1178 }
1179
1180 #ifdef CONFIG_IPIPE
1181
1182 int __ipipe_get_irq_priority(unsigned irq)
1183 {
1184 int ient, prio;
1185
1186 if (irq <= IRQ_CORETMR)
1187 return irq;
1188
1189 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1190 struct ivgx *ivg = ivg_table + ient;
1191 if (ivg->irqno == irq) {
1192 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1193 if (ivg7_13[prio].ifirst <= ivg &&
1194 ivg7_13[prio].istop > ivg)
1195 return IVG7 + prio;
1196 }
1197 }
1198 }
1199
1200 return IVG15;
1201 }
1202
1203 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1204 #ifdef CONFIG_DO_IRQ_L1
1205 __attribute__((l1_text))
1206 #endif
1207 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1208 {
1209 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1210 struct ipipe_domain *this_domain = __ipipe_current_domain;
1211 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1212 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1213 int irq, s;
1214
1215 if (likely(vec == EVT_IVTMR_P))
1216 irq = IRQ_CORETMR;
1217 else {
1218 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1219 unsigned long sic_status[3];
1220
1221 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1222 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1223 # ifdef SIC_ISR2
1224 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1225 # endif
1226 for (;; ivg++) {
1227 if (ivg >= ivg_stop) {
1228 atomic_inc(&num_spurious);
1229 return 0;
1230 }
1231 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1232 break;
1233 }
1234 #else
1235 unsigned long sic_status;
1236
1237 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1238
1239 for (;; ivg++) {
1240 if (ivg >= ivg_stop) {
1241 atomic_inc(&num_spurious);
1242 return 0;
1243 } else if (sic_status & ivg->isrflag)
1244 break;
1245 }
1246 #endif
1247 irq = ivg->irqno;
1248 }
1249
1250 if (irq == IRQ_SYSTMR) {
1251 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1252 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1253 #endif
1254 /* This is basically what we need from the register frame. */
1255 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1256 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1257 if (this_domain != ipipe_root_domain)
1258 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1259 else
1260 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1261 }
1262
1263 if (this_domain == ipipe_root_domain) {
1264 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1265 barrier();
1266 }
1267
1268 ipipe_trace_irq_entry(irq);
1269 __ipipe_handle_irq(irq, regs);
1270 ipipe_trace_irq_exit(irq);
1271
1272 if (this_domain == ipipe_root_domain) {
1273 set_thread_flag(TIF_IRQ_SYNC);
1274 if (!s) {
1275 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1276 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1277 }
1278 }
1279
1280 return 0;
1281 }
1282
1283 #endif /* CONFIG_IPIPE */
Linux for Ginger Game Console