arch/cris/arch-v10/kernel/time.c

   1 /*
   2  *  linux/arch/cris/arch-v10/kernel/time.c
   3  *
   4  *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   5  *  Copyright (C) 1999-2002 Axis Communications AB
   6  *
   7  */
   8
   9 #include <linux/timex.h>
  10 #include <linux/time.h>
  11 #include <linux/jiffies.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/swap.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 #include <linux/mm.h>
  17 #include <arch/svinto.h>
  18 #include <asm/types.h>
  19 #include <asm/signal.h>
  20 #include <asm/io.h>
  21 #include <asm/delay.h>
  22 #include <asm/rtc.h>
  23 #include <asm/irq_regs.h>
  24
  25 /* define this if you need to use print_timestamp */
  26 /* it will make jiffies at 96 hz instead of 100 hz though */
  27 #undef USE_CASCADE_TIMERS
  28
  29 extern void update_xtime_from_cmos(void);
  30 extern int set_rtc_mmss(unsigned long nowtime);
  31 extern int have_rtc;
  32
  33 unsigned long get_ns_in_jiffie(void)
  34 {
  35         unsigned char timer_count, t1;
  36         unsigned short presc_count;
  37         unsigned long ns;
  38         unsigned long flags;
  39
  40         local_irq_save(flags);
  41         timer_count = *R_TIMER0_DATA;
  42         presc_count = *R_TIM_PRESC_STATUS;
  43         /* presc_count might be wrapped */
  44         t1 = *R_TIMER0_DATA;
  45
  46         if (timer_count != t1){
  47                 /* it wrapped, read prescaler again...  */
  48                 presc_count = *R_TIM_PRESC_STATUS;
  49                 timer_count = t1;
  50         }
  51         local_irq_restore(flags);
  52         if (presc_count >= PRESCALE_VALUE/2 ){
  53                 presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
  54         } else {
  55                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
  56         }
  57
  58         ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
  59              ( (presc_count) * (1000000000/PRESCALE_FREQ));
  60         return ns;
  61 }
  62
  63 unsigned long do_slow_gettimeoffset(void)
  64 {
  65         unsigned long count, t1;
  66         unsigned long usec_count = 0;
  67         unsigned short presc_count;
  68
  69         static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
  70         static unsigned long jiffies_p = 0;
  71
  72         /*
  73          * cache volatile jiffies temporarily; we have IRQs turned off.
  74          */
  75         unsigned long jiffies_t;
  76
  77         /* The timer interrupt comes from Etrax timer 0. In order to get
  78          * better precision, we check the current value. It might have
  79          * underflowed already though.
  80          */
  81
  82 #ifndef CONFIG_SVINTO_SIM
  83         /* Not available in the xsim simulator. */
  84         count = *R_TIMER0_DATA;
  85         presc_count = *R_TIM_PRESC_STATUS;
  86         /* presc_count might be wrapped */
  87         t1 = *R_TIMER0_DATA;
  88         if (count != t1){
  89                 /* it wrapped, read prescaler again...  */
  90                 presc_count = *R_TIM_PRESC_STATUS;
  91                 count = t1;
  92         }
  93 #else
  94         count = 0;
  95         presc_count = 0;
  96 #endif
  97
  98         jiffies_t = jiffies;
  99
 100         /*
 101          * avoiding timer inconsistencies (they are rare, but they happen)...
 102          * there are one problem that must be avoided here:
 103          *  1. the timer counter underflows
 104          */
 105         if( jiffies_t == jiffies_p ) {
 106                 if( count > count_p ) {
 107                         /* Timer wrapped, use new count and prescale
 108                          * increase the time corresponding to one jiffie
 109                          */
 110                         usec_count = 1000000/HZ;
 111                 }
 112         } else
 113                 jiffies_p = jiffies_t;
 114         count_p = count;
 115         if (presc_count >= PRESCALE_VALUE/2 ){
 116                 presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
 117         } else {
 118                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
 119         }
 120         /* Convert timer value to usec */
 121         usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
 122                       (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
 123
 124         return usec_count;
 125 }
 126
 127 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
 128  *
 129  * 3.10.4 Watchdog timer
 130
 131  * When the watchdog timer is started, it generates an NMI if the watchdog
 132  * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
 133  * stopped after an additional 3.3 ms, the watchdog resets the chip.
 134  * The watchdog timer is stopped after reset. The watchdog timer is controlled
 135  * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
 136  * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
 137  * described in the table below:
 138  *
 139  *   Watchdog    Value written:
 140  *   state:      To enable:  To key:      Operation:
 141  *   --------    ----------  -------      ----------
 142  *   stopped         0         X          No effect.
 143  *   stopped         1       key_val      Start watchdog with key = key_val.
 144  *   started         0       ~key         Stop watchdog
 145  *   started         1       ~key         Restart watchdog with key = ~key.
 146  *   started         X       new_key_val  Change key to new_key_val.
 147  *
 148  * Note: '~' is the bitwise NOT operator.
 149  *
 150  */
 151
 152 /* right now, starting the watchdog is the same as resetting it */
 153 #define start_watchdog reset_watchdog
 154
 155 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 156 static int watchdog_key = 0;  /* arbitrary number */
 157 #endif
 158
 159 /* number of pages to consider "out of memory". it is normal that the memory
 160  * is used though, so put this really low.
 161  */
 162
 163 #define WATCHDOG_MIN_FREE_PAGES 8
 164
 165 void
 166 reset_watchdog(void)
 167 {
 168 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 169         /* only keep watchdog happy as long as we have memory left! */
 170         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 171                 /* reset the watchdog with the inverse of the old key */
 172                 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 173                 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 174                         IO_STATE(R_WATCHDOG, enable, start);
 175         }
 176 #endif
 177 }
 178
 179 /* stop the watchdog - we still need the correct key */
 180
 181 void
 182 stop_watchdog(void)
 183 {
 184 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 185         watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 186         *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 187                 IO_STATE(R_WATCHDOG, enable, stop);
 188 #endif
 189 }
 190
 191 /* last time the cmos clock got updated */
 192 static long last_rtc_update = 0;
 193
 194 /*
 195  * timer_interrupt() needs to keep up the real-time clock,
 196  * as well as call the "do_timer()" routine every clocktick
 197  */
 198
 199 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
 200
 201 extern void cris_do_profile(struct pt_regs *regs);
 202
 203 static inline irqreturn_t
 204 timer_interrupt(int irq, void *dev_id)
 205 {
 206         struct pt_regs *regs = get_irq_regs();
 207         /* acknowledge the timer irq */
 208
 209 #ifdef USE_CASCADE_TIMERS
 210         *R_TIMER_CTRL =
 211                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 212                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 213                 IO_STATE( R_TIMER_CTRL, i1, clr) |
 214                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 215                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 216                 IO_STATE( R_TIMER_CTRL, i0, clr) |
 217                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 218                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 219 #else
 220         *R_TIMER_CTRL = r_timer_ctrl_shadow |
 221                 IO_STATE(R_TIMER_CTRL, i0, clr);
 222 #endif
 223
 224         /* reset watchdog otherwise it resets us! */
 225         reset_watchdog();
 226
 227         /* Update statistics. */
 228         update_process_times(user_mode(regs));
 229
 230         /* call the real timer interrupt handler */
 231
 232         do_timer(1);
 233
 234         cris_do_profile(regs); /* Save profiling information */
 235
 236         /*
 237          * If we have an externally synchronized Linux clock, then update
 238          * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 239          * called as close as possible to 500 ms before the new second starts.
 240          *
 241          * The division here is not time critical since it will run once in
 242          * 11 minutes
 243          */
 244         if (ntp_synced() &&
 245             xtime.tv_sec > last_rtc_update + 660 &&
 246             (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
 247             (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
 248                 if (set_rtc_mmss(xtime.tv_sec) == 0)
 249                         last_rtc_update = xtime.tv_sec;
 250                 else
 251                         last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
 252         }
 253         return IRQ_HANDLED;
 254 }
 255
 256 /* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
 257  * it needs to be IRQF_DISABLED to make the jiffies update work properly
 258  */
 259
 260 static struct irqaction irq2  = {
 261         .handler = timer_interrupt,
 262         .flags = IRQF_SHARED | IRQF_DISABLED,
 263         .name = "timer",
 264 };
 265
 266 void __init
 267 time_init(void)
 268 {
 269         /* probe for the RTC and read it if it exists
 270          * Before the RTC can be probed the loops_per_usec variable needs
 271          * to be initialized to make usleep work. A better value for
 272          * loops_per_usec is calculated by the kernel later once the
 273          * clock has started.
 274          */
 275         loops_per_usec = 50;
 276
 277         if(RTC_INIT() < 0) {
 278                 /* no RTC, start at 1980 */
 279                 xtime.tv_sec = 0;
 280                 xtime.tv_nsec = 0;
 281                 have_rtc = 0;
 282         } else {
 283                 /* get the current time */
 284                 have_rtc = 1;
 285                 update_xtime_from_cmos();
 286         }
 287
 288         /*
 289          * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
 290          * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
 291          */
 292         set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
 293
 294         /* Setup the etrax timers
 295          * Base frequency is 25000 hz, divider 250 -> 100 HZ
 296          * In normal mode, we use timer0, so timer1 is free. In cascade
 297          * mode (which we sometimes use for debugging) both timers are used.
 298          * Remember that linux/timex.h contains #defines that rely on the
 299          * timer settings below (hz and divide factor) !!!
 300          */
 301
 302 #ifdef USE_CASCADE_TIMERS
 303         *R_TIMER_CTRL =
 304                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 305                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 306                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 307                 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
 308                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 309                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 310                 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
 311                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 312
 313         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 314                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 315                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 316                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 317                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 318                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 319                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 320                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 321                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 322 #else
 323         *R_TIMER_CTRL =
 324                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 325                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 326                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 327                 IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
 328                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 329                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 330                 IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
 331                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 332
 333         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 334                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 335                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 336                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 337                 IO_STATE(R_TIMER_CTRL, tm1,       run)      |
 338                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 339                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 340                 IO_STATE(R_TIMER_CTRL, tm0,       run)      |
 341                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 342
 343         *R_TIMER_PRESCALE = PRESCALE_VALUE;
 344 #endif
 345
 346         *R_IRQ_MASK0_SET =
 347                 IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
 348
 349         /* now actually register the timer irq handler that calls timer_interrupt() */
 350
 351         setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
 352
 353         /* enable watchdog if we should use one */
 354
 355 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 356         printk("Enabling watchdog...\n");
 357         start_watchdog();
 358
 359         /* If we use the hardware watchdog, we want to trap it as an NMI
 360            and dump registers before it resets us.  For this to happen, we
 361            must set the "m" NMI enable flag (which once set, is unset only
 362            when an NMI is taken).
 363
 364            The same goes for the external NMI, but that doesn't have any
 365            driver or infrastructure support yet.  */
 366         asm ("setf m");
 367
 368         *R_IRQ_MASK0_SET =
 369                 IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
 370         *R_VECT_MASK_SET =
 371                 IO_STATE(R_VECT_MASK_SET, nmi, set);
 372 #endif
 373 }