arch/mips/alchemy/common/clocks.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Simple Au1xx0 clocks routines.
   4  *
   5  * Copyright 2001, 2008 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc. <source@mvista.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <asm/time.h>
  32 #include <asm/mach-au1x00/au1000.h>
  33
  34 /*
  35  * I haven't found anyone that doesn't use a 12 MHz source clock,
  36  * but just in case.....
  37  */
  38 #define AU1000_SRC_CLK  12000000
  39
  40 static unsigned int au1x00_clock; /*  Hz */
  41 static unsigned long uart_baud_base;
  42
  43 static DEFINE_SPINLOCK(time_lock);
  44
  45 /*
  46  * Set the au1000_clock
  47  */
  48 void set_au1x00_speed(unsigned int new_freq)
  49 {
  50         au1x00_clock = new_freq;
  51 }
  52
  53 unsigned int get_au1x00_speed(void)
  54 {
  55         return au1x00_clock;
  56 }
  57 EXPORT_SYMBOL(get_au1x00_speed);
  58
  59 /*
  60  * The UART baud base is not known at compile time ... if
  61  * we want to be able to use the same code on different
  62  * speed CPUs.
  63  */
  64 unsigned long get_au1x00_uart_baud_base(void)
  65 {
  66         return uart_baud_base;
  67 }
  68
  69 void set_au1x00_uart_baud_base(unsigned long new_baud_base)
  70 {
  71         uart_baud_base = new_baud_base;
  72 }
  73
  74 /*
  75  * We read the real processor speed from the PLL.  This is important
  76  * because it is more accurate than computing it from the 32 KHz
  77  * counter, if it exists.  If we don't have an accurate processor
  78  * speed, all of the peripherals that derive their clocks based on
  79  * this advertised speed will introduce error and sometimes not work
  80  * properly.  This function is futher convoluted to still allow configurations
  81  * to do that in case they have really, really old silicon with a
  82  * write-only PLL register.                     -- Dan
  83  */
  84 unsigned long au1xxx_calc_clock(void)
  85 {
  86         unsigned long cpu_speed;
  87         unsigned long flags;
  88
  89         spin_lock_irqsave(&time_lock, flags);
  90
  91         /*
  92          * On early Au1000, sys_cpupll was write-only. Since these
  93          * silicon versions of Au1000 are not sold by AMD, we don't bend
  94          * over backwards trying to determine the frequency.
  95          */
  96         if (au1xxx_cpu_has_pll_wo())
  97 #ifdef CONFIG_SOC_AU1000_FREQUENCY
  98                 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
  99 #else
 100                 cpu_speed = 396000000;
 101 #endif
 102         else
 103                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
 104
 105         /* On Alchemy CPU:counter ratio is 1:1 */
 106         mips_hpt_frequency = cpu_speed;
 107         /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
 108         set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
 109                                                           & 0x03) + 2) * 16));
 110
 111         spin_unlock_irqrestore(&time_lock, flags);
 112
 113         set_au1x00_speed(cpu_speed);
 114
 115         return cpu_speed;
 116 }